xref: /linux/arch/arm/mach-imx/cpu.c (revision 4eb7ae7a301d3586c3351e81d5c3cfe2304a1a6a)
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/err.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/module.h>
5 #include <linux/io.h>
6 #include <linux/of.h>
7 #include <linux/of_address.h>
8 #include <linux/regmap.h>
9 #include <linux/slab.h>
10 #include <linux/sys_soc.h>
11 
12 #include "hardware.h"
13 #include "common.h"
14 
15 #define OCOTP_UID_H	0x420
16 #define OCOTP_UID_L	0x410
17 
18 unsigned int __mxc_cpu_type;
19 static unsigned int imx_soc_revision;
20 
21 void mxc_set_cpu_type(unsigned int type)
22 {
23 	__mxc_cpu_type = type;
24 }
25 
26 void imx_set_soc_revision(unsigned int rev)
27 {
28 	imx_soc_revision = rev;
29 }
30 
31 unsigned int imx_get_soc_revision(void)
32 {
33 	return imx_soc_revision;
34 }
35 
36 void imx_print_silicon_rev(const char *cpu, int srev)
37 {
38 	if (srev == IMX_CHIP_REVISION_UNKNOWN)
39 		pr_info("CPU identified as %s, unknown revision\n", cpu);
40 	else
41 		pr_info("CPU identified as %s, silicon rev %d.%d\n",
42 				cpu, (srev >> 4) & 0xf, srev & 0xf);
43 }
44 
45 void __init imx_set_aips(void __iomem *base)
46 {
47 	unsigned int reg;
48 /*
49  * Set all MPROTx to be non-bufferable, trusted for R/W,
50  * not forced to user-mode.
51  */
52 	imx_writel(0x77777777, base + 0x0);
53 	imx_writel(0x77777777, base + 0x4);
54 
55 /*
56  * Set all OPACRx to be non-bufferable, to not require
57  * supervisor privilege level for access, allow for
58  * write access and untrusted master access.
59  */
60 	imx_writel(0x0, base + 0x40);
61 	imx_writel(0x0, base + 0x44);
62 	imx_writel(0x0, base + 0x48);
63 	imx_writel(0x0, base + 0x4C);
64 	reg = imx_readl(base + 0x50) & 0x00FFFFFF;
65 	imx_writel(reg, base + 0x50);
66 }
67 
68 void __init imx_aips_allow_unprivileged_access(
69 		const char *compat)
70 {
71 	void __iomem *aips_base_addr;
72 	struct device_node *np;
73 
74 	for_each_compatible_node(np, NULL, compat) {
75 		aips_base_addr = of_iomap(np, 0);
76 		WARN_ON(!aips_base_addr);
77 		imx_set_aips(aips_base_addr);
78 	}
79 }
80 
81 struct device * __init imx_soc_device_init(void)
82 {
83 	struct soc_device_attribute *soc_dev_attr;
84 	const char *ocotp_compat = NULL;
85 	struct soc_device *soc_dev;
86 	struct device_node *root;
87 	struct regmap *ocotp;
88 	const char *soc_id;
89 	u64 soc_uid = 0;
90 	u32 val;
91 	int ret;
92 
93 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
94 	if (!soc_dev_attr)
95 		return NULL;
96 
97 	soc_dev_attr->family = "Freescale i.MX";
98 
99 	root = of_find_node_by_path("/");
100 	ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
101 	of_node_put(root);
102 	if (ret)
103 		goto free_soc;
104 
105 	switch (__mxc_cpu_type) {
106 	case MXC_CPU_MX1:
107 		soc_id = "i.MX1";
108 		break;
109 	case MXC_CPU_MX21:
110 		soc_id = "i.MX21";
111 		break;
112 	case MXC_CPU_MX25:
113 		soc_id = "i.MX25";
114 		break;
115 	case MXC_CPU_MX27:
116 		soc_id = "i.MX27";
117 		break;
118 	case MXC_CPU_MX31:
119 		soc_id = "i.MX31";
120 		break;
121 	case MXC_CPU_MX35:
122 		soc_id = "i.MX35";
123 		break;
124 	case MXC_CPU_MX51:
125 		soc_id = "i.MX51";
126 		break;
127 	case MXC_CPU_MX53:
128 		soc_id = "i.MX53";
129 		break;
130 	case MXC_CPU_IMX6SL:
131 		ocotp_compat = "fsl,imx6sl-ocotp";
132 		soc_id = "i.MX6SL";
133 		break;
134 	case MXC_CPU_IMX6DL:
135 		ocotp_compat = "fsl,imx6q-ocotp";
136 		soc_id = "i.MX6DL";
137 		break;
138 	case MXC_CPU_IMX6SX:
139 		ocotp_compat = "fsl,imx6sx-ocotp";
140 		soc_id = "i.MX6SX";
141 		break;
142 	case MXC_CPU_IMX6Q:
143 		ocotp_compat = "fsl,imx6q-ocotp";
144 		soc_id = "i.MX6Q";
145 		break;
146 	case MXC_CPU_IMX6UL:
147 		ocotp_compat = "fsl,imx6ul-ocotp";
148 		soc_id = "i.MX6UL";
149 		break;
150 	case MXC_CPU_IMX6ULL:
151 		ocotp_compat = "fsl,imx6ul-ocotp";
152 		soc_id = "i.MX6ULL";
153 		break;
154 	case MXC_CPU_IMX6ULZ:
155 		ocotp_compat = "fsl,imx6ul-ocotp";
156 		soc_id = "i.MX6ULZ";
157 		break;
158 	case MXC_CPU_IMX6SLL:
159 		ocotp_compat = "fsl,imx6sll-ocotp";
160 		soc_id = "i.MX6SLL";
161 		break;
162 	case MXC_CPU_IMX7D:
163 		ocotp_compat = "fsl,imx7d-ocotp";
164 		soc_id = "i.MX7D";
165 		break;
166 	case MXC_CPU_IMX7ULP:
167 		soc_id = "i.MX7ULP";
168 		break;
169 	default:
170 		soc_id = "Unknown";
171 	}
172 	soc_dev_attr->soc_id = soc_id;
173 
174 	if (ocotp_compat) {
175 		ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat);
176 		if (IS_ERR(ocotp))
177 			pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat);
178 
179 		regmap_read(ocotp, OCOTP_UID_H, &val);
180 		soc_uid = val;
181 		regmap_read(ocotp, OCOTP_UID_L, &val);
182 		soc_uid <<= 32;
183 		soc_uid |= val;
184 	}
185 
186 	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
187 					   (imx_soc_revision >> 4) & 0xf,
188 					   imx_soc_revision & 0xf);
189 	if (!soc_dev_attr->revision)
190 		goto free_soc;
191 
192 	soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
193 	if (!soc_dev_attr->serial_number)
194 		goto free_rev;
195 
196 	soc_dev = soc_device_register(soc_dev_attr);
197 	if (IS_ERR(soc_dev))
198 		goto free_serial_number;
199 
200 	return soc_device_to_device(soc_dev);
201 
202 free_serial_number:
203 	kfree(soc_dev_attr->serial_number);
204 free_rev:
205 	kfree(soc_dev_attr->revision);
206 free_soc:
207 	kfree(soc_dev_attr);
208 	return NULL;
209 }
210