xref: /linux/arch/arm/mach-imx/cpu.c (revision 0d456bad36d42d16022be045c8a53ddbb59ee478)
1 
2 #include <linux/module.h>
3 #include <linux/io.h>
4 
5 #include "hardware.h"
6 
7 unsigned int __mxc_cpu_type;
8 EXPORT_SYMBOL(__mxc_cpu_type);
9 
10 void mxc_set_cpu_type(unsigned int type)
11 {
12 	__mxc_cpu_type = type;
13 }
14 
15 void imx_print_silicon_rev(const char *cpu, int srev)
16 {
17 	if (srev == IMX_CHIP_REVISION_UNKNOWN)
18 		pr_info("CPU identified as %s, unknown revision\n", cpu);
19 	else
20 		pr_info("CPU identified as %s, silicon rev %d.%d\n",
21 				cpu, (srev >> 4) & 0xf, srev & 0xf);
22 }
23 
24 void __init imx_set_aips(void __iomem *base)
25 {
26 	unsigned int reg;
27 /*
28  * Set all MPROTx to be non-bufferable, trusted for R/W,
29  * not forced to user-mode.
30  */
31 	__raw_writel(0x77777777, base + 0x0);
32 	__raw_writel(0x77777777, base + 0x4);
33 
34 /*
35  * Set all OPACRx to be non-bufferable, to not require
36  * supervisor privilege level for access, allow for
37  * write access and untrusted master access.
38  */
39 	__raw_writel(0x0, base + 0x40);
40 	__raw_writel(0x0, base + 0x44);
41 	__raw_writel(0x0, base + 0x48);
42 	__raw_writel(0x0, base + 0x4C);
43 	reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
44 	__raw_writel(reg, base + 0x50);
45 }
46