1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. 4 */ 5 6 7 #ifndef __ASM_ARCH_MXC_COMMON_H__ 8 #define __ASM_ARCH_MXC_COMMON_H__ 9 10 #include <linux/reboot.h> 11 12 struct irq_data; 13 struct platform_device; 14 struct pt_regs; 15 struct clk; 16 struct device_node; 17 18 void mx31_map_io(void); 19 void mx35_map_io(void); 20 void imx31_init_early(void); 21 void imx35_init_early(void); 22 void mxc_set_cpu_type(unsigned int type); 23 void mxc_restart(enum reboot_mode, const char *); 24 void mxc_arch_reset_init(void __iomem *); 25 void imx_set_aips(void __iomem *); 26 void imx_aips_allow_unprivileged_access(const char *compat); 27 void imx_set_soc_revision(unsigned int rev); 28 void imx_init_revision_from_anatop(void); 29 void imx6_enable_rbc(bool enable); 30 void imx_gpc_check_dt(void); 31 void imx_gpc_set_arm_power_in_lpm(bool power_off); 32 void imx_gpc_set_l2_mem_power_in_lpm(bool power_off); 33 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); 34 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); 35 void imx25_pm_init(void); 36 void imx27_pm_init(void); 37 void imx5_pmu_init(void); 38 39 enum mxc_cpu_pwr_mode { 40 WAIT_CLOCKED, /* wfi only */ 41 WAIT_UNCLOCKED, /* WAIT */ 42 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ 43 STOP_POWER_ON, /* just STOP */ 44 STOP_POWER_OFF, /* STOP + SRPG */ 45 }; 46 47 enum ulp_cpu_pwr_mode { 48 ULP_PM_HSRUN, /* High speed run mode */ 49 ULP_PM_RUN, /* Run mode */ 50 ULP_PM_WAIT, /* Wait mode */ 51 ULP_PM_STOP, /* Stop mode */ 52 ULP_PM_VLPS, /* Very low power stop mode */ 53 ULP_PM_VLLS, /* very low leakage stop mode */ 54 }; 55 56 void imx_enable_cpu(int cpu, bool enable); 57 void imx_set_cpu_jump(int cpu, void *jump_addr); 58 u32 imx_get_cpu_arg(int cpu); 59 void imx_set_cpu_arg(int cpu, u32 arg); 60 #ifdef CONFIG_SMP 61 void v7_secondary_startup(void); 62 void imx_scu_map_io(void); 63 void imx_smp_prepare(void); 64 #else 65 static inline void imx_scu_map_io(void) {} 66 static inline void imx_smp_prepare(void) {} 67 #endif 68 void imx_src_init(void); 69 void imx7_src_init(void); 70 void imx_gpc_pre_suspend(bool arm_power_off); 71 void imx_gpc_post_resume(void); 72 void imx_gpc_mask_all(void); 73 void imx_gpc_restore_all(void); 74 void imx_gpc_hwirq_mask(unsigned int hwirq); 75 void imx_gpc_hwirq_unmask(unsigned int hwirq); 76 void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); 77 void imx_anatop_init(void); 78 void imx_anatop_pre_suspend(void); 79 void imx_anatop_post_resume(void); 80 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); 81 void imx6_set_int_mem_clk_lpm(bool enable); 82 int imx_mmdc_get_ddr_type(void); 83 int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode); 84 85 void imx_cpu_die(unsigned int cpu); 86 int imx_cpu_kill(unsigned int cpu); 87 88 #ifdef CONFIG_SUSPEND 89 void imx53_suspend(void __iomem *ocram_vbase); 90 extern const u32 imx53_suspend_sz; 91 void imx6_suspend(void __iomem *ocram_vbase); 92 #else 93 static inline void imx53_suspend(void __iomem *ocram_vbase) {} 94 static __maybe_unused const u32 imx53_suspend_sz; 95 static inline void imx6_suspend(void __iomem *ocram_vbase) {} 96 #endif 97 98 void v7_cpu_resume(void); 99 100 void imx6_pm_ccm_init(const char *ccm_compat); 101 void imx6q_pm_init(void); 102 void imx6dl_pm_init(void); 103 void imx6sl_pm_init(void); 104 void imx6sx_pm_init(void); 105 void imx6ul_pm_init(void); 106 void imx7ulp_pm_init(void); 107 108 #ifdef CONFIG_PM 109 void imx51_pm_init(void); 110 void imx53_pm_init(void); 111 #else 112 static inline void imx51_pm_init(void) {} 113 static inline void imx53_pm_init(void) {} 114 #endif 115 116 #ifdef CONFIG_NEON 117 int mx51_neon_fixup(void); 118 #else 119 static inline int mx51_neon_fixup(void) { return 0; } 120 #endif 121 122 #ifdef CONFIG_CACHE_L2X0 123 void imx_init_l2cache(void); 124 #else 125 static inline void imx_init_l2cache(void) {} 126 #endif 127 128 extern const struct smp_operations imx_smp_ops; 129 extern const struct smp_operations imx7_smp_ops; 130 extern const struct smp_operations ls1021a_smp_ops; 131 132 #endif 133