1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/io.h> 24 #include <linux/of.h> 25 #include <asm/mach/irq.h> 26 #include <asm/exception.h> 27 28 #include "common.h" 29 #include "hardware.h" 30 #include "irq-common.h" 31 32 #define AVIC_INTCNTL 0x00 /* int control reg */ 33 #define AVIC_NIMASK 0x04 /* int mask reg */ 34 #define AVIC_INTENNUM 0x08 /* int enable number reg */ 35 #define AVIC_INTDISNUM 0x0C /* int disable number reg */ 36 #define AVIC_INTENABLEH 0x10 /* int enable reg high */ 37 #define AVIC_INTENABLEL 0x14 /* int enable reg low */ 38 #define AVIC_INTTYPEH 0x18 /* int type reg high */ 39 #define AVIC_INTTYPEL 0x1C /* int type reg low */ 40 #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ 41 #define AVIC_NIVECSR 0x40 /* norm int vector/status */ 42 #define AVIC_FIVECSR 0x44 /* fast int vector/status */ 43 #define AVIC_INTSRCH 0x48 /* int source reg high */ 44 #define AVIC_INTSRCL 0x4C /* int source reg low */ 45 #define AVIC_INTFRCH 0x50 /* int force reg high */ 46 #define AVIC_INTFRCL 0x54 /* int force reg low */ 47 #define AVIC_NIPNDH 0x58 /* norm int pending high */ 48 #define AVIC_NIPNDL 0x5C /* norm int pending low */ 49 #define AVIC_FIPNDH 0x60 /* fast int pending high */ 50 #define AVIC_FIPNDL 0x64 /* fast int pending low */ 51 52 #define AVIC_NUM_IRQS 64 53 54 static void __iomem *avic_base; 55 static struct irq_domain *domain; 56 57 #ifdef CONFIG_FIQ 58 static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) 59 { 60 unsigned int irqt; 61 62 if (hwirq >= AVIC_NUM_IRQS) 63 return -EINVAL; 64 65 if (hwirq < AVIC_NUM_IRQS / 2) { 66 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); 67 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); 68 } else { 69 hwirq -= AVIC_NUM_IRQS / 2; 70 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); 71 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); 72 } 73 74 return 0; 75 } 76 #endif /* CONFIG_FIQ */ 77 78 79 static struct mxc_extra_irq avic_extra_irq = { 80 #ifdef CONFIG_FIQ 81 .set_irq_fiq = avic_set_irq_fiq, 82 #endif 83 }; 84 85 #ifdef CONFIG_PM 86 static u32 avic_saved_mask_reg[2]; 87 88 static void avic_irq_suspend(struct irq_data *d) 89 { 90 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 91 struct irq_chip_type *ct = gc->chip_types; 92 int idx = d->hwirq >> 5; 93 94 avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); 95 imx_writel(gc->wake_active, avic_base + ct->regs.mask); 96 } 97 98 static void avic_irq_resume(struct irq_data *d) 99 { 100 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 101 struct irq_chip_type *ct = gc->chip_types; 102 int idx = d->hwirq >> 5; 103 104 imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); 105 } 106 107 #else 108 #define avic_irq_suspend NULL 109 #define avic_irq_resume NULL 110 #endif 111 112 static __init void avic_init_gc(int idx, unsigned int irq_start) 113 { 114 struct irq_chip_generic *gc; 115 struct irq_chip_type *ct; 116 117 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, 118 handle_level_irq); 119 gc->private = &avic_extra_irq; 120 gc->wake_enabled = IRQ_MSK(32); 121 122 ct = gc->chip_types; 123 ct->chip.irq_mask = irq_gc_mask_clr_bit; 124 ct->chip.irq_unmask = irq_gc_mask_set_bit; 125 ct->chip.irq_ack = irq_gc_mask_clr_bit; 126 ct->chip.irq_set_wake = irq_gc_set_wake; 127 ct->chip.irq_suspend = avic_irq_suspend; 128 ct->chip.irq_resume = avic_irq_resume; 129 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; 130 ct->regs.ack = ct->regs.mask; 131 132 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 133 } 134 135 static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) 136 { 137 u32 nivector; 138 139 do { 140 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; 141 if (nivector == 0xffff) 142 break; 143 144 handle_domain_irq(domain, nivector, regs); 145 } while (1); 146 } 147 148 /* 149 * This function initializes the AVIC hardware and disables all the 150 * interrupts. It registers the interrupt enable and disable functions 151 * to the kernel for each interrupt source. 152 */ 153 void __init mxc_init_irq(void __iomem *irqbase) 154 { 155 struct device_node *np; 156 int irq_base; 157 int i; 158 159 avic_base = irqbase; 160 161 /* put the AVIC into the reset value with 162 * all interrupts disabled 163 */ 164 imx_writel(0, avic_base + AVIC_INTCNTL); 165 imx_writel(0x1f, avic_base + AVIC_NIMASK); 166 167 /* disable all interrupts */ 168 imx_writel(0, avic_base + AVIC_INTENABLEH); 169 imx_writel(0, avic_base + AVIC_INTENABLEL); 170 171 /* all IRQ no FIQ */ 172 imx_writel(0, avic_base + AVIC_INTTYPEH); 173 imx_writel(0, avic_base + AVIC_INTTYPEL); 174 175 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); 176 WARN_ON(irq_base < 0); 177 178 np = of_find_compatible_node(NULL, NULL, "fsl,avic"); 179 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, 180 &irq_domain_simple_ops, NULL); 181 WARN_ON(!domain); 182 183 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) 184 avic_init_gc(i, irq_base); 185 186 /* Set default priority value (0) for all IRQ's */ 187 for (i = 0; i < 8; i++) 188 imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); 189 190 set_handle_irq(avic_handle_irq); 191 192 #ifdef CONFIG_FIQ 193 /* Initialize FIQ */ 194 init_FIQ(FIQ_START); 195 #endif 196 197 printk(KERN_INFO "MXC IRQ initialized\n"); 198 } 199