1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/io.h> 24 #include <linux/of.h> 25 #include <asm/mach/irq.h> 26 #include <asm/exception.h> 27 28 #include "common.h" 29 #include "hardware.h" 30 #include "irq-common.h" 31 32 #define AVIC_INTCNTL 0x00 /* int control reg */ 33 #define AVIC_NIMASK 0x04 /* int mask reg */ 34 #define AVIC_INTENNUM 0x08 /* int enable number reg */ 35 #define AVIC_INTDISNUM 0x0C /* int disable number reg */ 36 #define AVIC_INTENABLEH 0x10 /* int enable reg high */ 37 #define AVIC_INTENABLEL 0x14 /* int enable reg low */ 38 #define AVIC_INTTYPEH 0x18 /* int type reg high */ 39 #define AVIC_INTTYPEL 0x1C /* int type reg low */ 40 #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ 41 #define AVIC_NIVECSR 0x40 /* norm int vector/status */ 42 #define AVIC_FIVECSR 0x44 /* fast int vector/status */ 43 #define AVIC_INTSRCH 0x48 /* int source reg high */ 44 #define AVIC_INTSRCL 0x4C /* int source reg low */ 45 #define AVIC_INTFRCH 0x50 /* int force reg high */ 46 #define AVIC_INTFRCL 0x54 /* int force reg low */ 47 #define AVIC_NIPNDH 0x58 /* norm int pending high */ 48 #define AVIC_NIPNDL 0x5C /* norm int pending low */ 49 #define AVIC_FIPNDH 0x60 /* fast int pending high */ 50 #define AVIC_FIPNDL 0x64 /* fast int pending low */ 51 52 #define AVIC_NUM_IRQS 64 53 54 void __iomem *avic_base; 55 static struct irq_domain *domain; 56 57 static u32 avic_saved_mask_reg[2]; 58 59 #ifdef CONFIG_MXC_IRQ_PRIOR 60 static int avic_irq_set_priority(unsigned char irq, unsigned char prio) 61 { 62 struct irq_data *d = irq_get_irq_data(irq); 63 unsigned int temp; 64 unsigned int mask = 0x0F << irq % 8 * 4; 65 66 irq = d->hwirq; 67 68 if (irq >= AVIC_NUM_IRQS) 69 return -EINVAL; 70 71 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); 72 temp &= ~mask; 73 temp |= prio & mask; 74 75 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); 76 77 return 0; 78 } 79 #endif 80 81 #ifdef CONFIG_FIQ 82 static int avic_set_irq_fiq(unsigned int irq, unsigned int type) 83 { 84 struct irq_data *d = irq_get_irq_data(irq); 85 unsigned int irqt; 86 87 irq = d->hwirq; 88 89 if (irq >= AVIC_NUM_IRQS) 90 return -EINVAL; 91 92 if (irq < AVIC_NUM_IRQS / 2) { 93 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); 94 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); 95 } else { 96 irq -= AVIC_NUM_IRQS / 2; 97 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); 98 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); 99 } 100 101 return 0; 102 } 103 #endif /* CONFIG_FIQ */ 104 105 106 static struct mxc_extra_irq avic_extra_irq = { 107 #ifdef CONFIG_MXC_IRQ_PRIOR 108 .set_priority = avic_irq_set_priority, 109 #endif 110 #ifdef CONFIG_FIQ 111 .set_irq_fiq = avic_set_irq_fiq, 112 #endif 113 }; 114 115 #ifdef CONFIG_PM 116 static void avic_irq_suspend(struct irq_data *d) 117 { 118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 119 struct irq_chip_type *ct = gc->chip_types; 120 int idx = d->hwirq >> 5; 121 122 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); 123 __raw_writel(gc->wake_active, avic_base + ct->regs.mask); 124 } 125 126 static void avic_irq_resume(struct irq_data *d) 127 { 128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 129 struct irq_chip_type *ct = gc->chip_types; 130 int idx = d->hwirq >> 5; 131 132 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); 133 } 134 135 #else 136 #define avic_irq_suspend NULL 137 #define avic_irq_resume NULL 138 #endif 139 140 static __init void avic_init_gc(int idx, unsigned int irq_start) 141 { 142 struct irq_chip_generic *gc; 143 struct irq_chip_type *ct; 144 145 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, 146 handle_level_irq); 147 gc->private = &avic_extra_irq; 148 gc->wake_enabled = IRQ_MSK(32); 149 150 ct = gc->chip_types; 151 ct->chip.irq_mask = irq_gc_mask_clr_bit; 152 ct->chip.irq_unmask = irq_gc_mask_set_bit; 153 ct->chip.irq_ack = irq_gc_mask_clr_bit; 154 ct->chip.irq_set_wake = irq_gc_set_wake; 155 ct->chip.irq_suspend = avic_irq_suspend; 156 ct->chip.irq_resume = avic_irq_resume; 157 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; 158 ct->regs.ack = ct->regs.mask; 159 160 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 161 } 162 163 asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) 164 { 165 u32 nivector; 166 167 do { 168 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; 169 if (nivector == 0xffff) 170 break; 171 172 handle_IRQ(irq_find_mapping(domain, nivector), regs); 173 } while (1); 174 } 175 176 /* 177 * This function initializes the AVIC hardware and disables all the 178 * interrupts. It registers the interrupt enable and disable functions 179 * to the kernel for each interrupt source. 180 */ 181 void __init mxc_init_irq(void __iomem *irqbase) 182 { 183 struct device_node *np; 184 int irq_base; 185 int i; 186 187 avic_base = irqbase; 188 189 /* put the AVIC into the reset value with 190 * all interrupts disabled 191 */ 192 __raw_writel(0, avic_base + AVIC_INTCNTL); 193 __raw_writel(0x1f, avic_base + AVIC_NIMASK); 194 195 /* disable all interrupts */ 196 __raw_writel(0, avic_base + AVIC_INTENABLEH); 197 __raw_writel(0, avic_base + AVIC_INTENABLEL); 198 199 /* all IRQ no FIQ */ 200 __raw_writel(0, avic_base + AVIC_INTTYPEH); 201 __raw_writel(0, avic_base + AVIC_INTTYPEL); 202 203 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); 204 WARN_ON(irq_base < 0); 205 206 np = of_find_compatible_node(NULL, NULL, "fsl,avic"); 207 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, 208 &irq_domain_simple_ops, NULL); 209 WARN_ON(!domain); 210 211 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) 212 avic_init_gc(i, irq_base); 213 214 /* Set default priority value (0) for all IRQ's */ 215 for (i = 0; i < 8; i++) 216 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); 217 218 #ifdef CONFIG_FIQ 219 /* Initialize FIQ */ 220 init_FIQ(FIQ_START); 221 #endif 222 223 printk(KERN_INFO "MXC IRQ initialized\n"); 224 } 225