1220e6cf7SRob Herring /* 2220e6cf7SRob Herring * Copyright 2011 Calxeda, Inc. 3220e6cf7SRob Herring * 4220e6cf7SRob Herring * This program is free software; you can redistribute it and/or modify it 5220e6cf7SRob Herring * under the terms and conditions of the GNU General Public License, 6220e6cf7SRob Herring * version 2, as published by the Free Software Foundation. 7220e6cf7SRob Herring * 8220e6cf7SRob Herring * This program is distributed in the hope it will be useful, but WITHOUT 9220e6cf7SRob Herring * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10220e6cf7SRob Herring * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11220e6cf7SRob Herring * more details. 12220e6cf7SRob Herring * 13220e6cf7SRob Herring * You should have received a copy of the GNU General Public License along with 14220e6cf7SRob Herring * this program. If not, see <http://www.gnu.org/licenses/>. 15220e6cf7SRob Herring */ 16220e6cf7SRob Herring #ifndef _MACH_HIGHBANK__SYSREGS_H_ 17220e6cf7SRob Herring #define _MACH_HIGHBANK__SYSREGS_H_ 18220e6cf7SRob Herring 19220e6cf7SRob Herring #include <linux/io.h> 20*7a2848d3SRob Herring #include <linux/smp.h> 21*7a2848d3SRob Herring #include <asm/smp_plat.h> 22*7a2848d3SRob Herring #include <asm/smp_scu.h> 23*7a2848d3SRob Herring #include "core.h" 24220e6cf7SRob Herring 25220e6cf7SRob Herring extern void __iomem *sregs_base; 26220e6cf7SRob Herring 27220e6cf7SRob Herring #define HB_SREG_A9_PWR_REQ 0xf00 28220e6cf7SRob Herring #define HB_SREG_A9_BOOT_STAT 0xf04 29220e6cf7SRob Herring #define HB_SREG_A9_BOOT_DATA 0xf08 30220e6cf7SRob Herring 31220e6cf7SRob Herring #define HB_PWR_SUSPEND 0 32220e6cf7SRob Herring #define HB_PWR_SOFT_RESET 1 33220e6cf7SRob Herring #define HB_PWR_HARD_RESET 2 34220e6cf7SRob Herring #define HB_PWR_SHUTDOWN 3 35220e6cf7SRob Herring 36*7a2848d3SRob Herring #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4)) 37*7a2848d3SRob Herring 38*7a2848d3SRob Herring static inline void highbank_set_core_pwr(void) 39*7a2848d3SRob Herring { 40*7a2848d3SRob Herring int cpu = cpu_logical_map(smp_processor_id()); 41*7a2848d3SRob Herring if (scu_base_addr) 42*7a2848d3SRob Herring scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); 43*7a2848d3SRob Herring else 44*7a2848d3SRob Herring writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); 45*7a2848d3SRob Herring } 46*7a2848d3SRob Herring 47220e6cf7SRob Herring static inline void hignbank_set_pwr_suspend(void) 48220e6cf7SRob Herring { 49220e6cf7SRob Herring writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); 50*7a2848d3SRob Herring highbank_set_core_pwr(); 51220e6cf7SRob Herring } 52220e6cf7SRob Herring 53220e6cf7SRob Herring static inline void hignbank_set_pwr_shutdown(void) 54220e6cf7SRob Herring { 55220e6cf7SRob Herring writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); 56*7a2848d3SRob Herring highbank_set_core_pwr(); 57220e6cf7SRob Herring } 58220e6cf7SRob Herring 59220e6cf7SRob Herring static inline void hignbank_set_pwr_soft_reset(void) 60220e6cf7SRob Herring { 61220e6cf7SRob Herring writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); 62*7a2848d3SRob Herring highbank_set_core_pwr(); 63220e6cf7SRob Herring } 64220e6cf7SRob Herring 65220e6cf7SRob Herring static inline void hignbank_set_pwr_hard_reset(void) 66220e6cf7SRob Herring { 67220e6cf7SRob Herring writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); 68*7a2848d3SRob Herring highbank_set_core_pwr(); 69220e6cf7SRob Herring } 70220e6cf7SRob Herring 71220e6cf7SRob Herring #endif 72