1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/mach-footbridge/include/mach/hardware.h 4 * 5 * Copyright (C) 1998-1999 Russell King. 6 * 7 * This file contains the hardware definitions of the EBSA-285. 8 */ 9 #ifndef __ASM_ARCH_HARDWARE_H 10 #define __ASM_ARCH_HARDWARE_H 11 12 /* Virtual Physical Size 13 * 0xff800000 0x40000000 1MB X-Bus 14 * 0xff000000 0x7c000000 1MB PCI I/O space 15 * 0xfe000000 0x42000000 1MB CSR 16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) 17 * 0xfc000000 0x79000000 1MB PCI IACK/special space 18 * 0xfb000000 0x7a000000 16MB PCI Config type 1 19 * 0xfa000000 0x7b000000 16MB PCI Config type 0 20 * 0xf9000000 0x50000000 1MB Cache flush 21 * 0xf0000000 0x80000000 16MB ISA memory 22 */ 23 24 #define XBUS_SIZE 0x00100000 25 #define XBUS_BASE 0xff800000 26 27 #define ARMCSR_SIZE 0x00100000 28 #define ARMCSR_BASE 0xfe000000 29 30 #define WFLUSH_SIZE 0x00100000 31 #define WFLUSH_BASE 0xfd000000 32 33 #define PCIIACK_SIZE 0x00100000 34 #define PCIIACK_BASE 0xfc000000 35 36 #define PCICFG1_SIZE 0x01000000 37 #define PCICFG1_BASE 0xfb000000 38 39 #define PCICFG0_SIZE 0x01000000 40 #define PCICFG0_BASE 0xfa000000 41 42 #define PCIMEM_SIZE 0x01000000 43 #define PCIMEM_BASE 0xf0000000 44 45 #define XBUS_CS2 0x40012000 46 47 #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 48 #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) 49 #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) 50 #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) 51 #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) 52 53 #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ 54 55 56 /* PIC irq control */ 57 #define PIC_LO 0x20 58 #define PIC_MASK_LO 0x21 59 #define PIC_HI 0xA0 60 #define PIC_MASK_HI 0xA1 61 62 /* GPIO pins */ 63 #define GPIO_CCLK 0x800 64 #define GPIO_DSCLK 0x400 65 #define GPIO_E2CLK 0x200 66 #define GPIO_IOLOAD 0x100 67 #define GPIO_RED_LED 0x080 68 #define GPIO_WDTIMER 0x040 69 #define GPIO_DATA 0x020 70 #define GPIO_IOCLK 0x010 71 #define GPIO_DONE 0x008 72 #define GPIO_FAN 0x004 73 #define GPIO_GREEN_LED 0x002 74 #define GPIO_RESET 0x001 75 76 /* CPLD pins */ 77 #define CPLD_DS_ENABLE 8 78 #define CPLD_7111_DISABLE 4 79 #define CPLD_UNMUTE 2 80 #define CPLD_FLASH_WR_ENABLE 1 81 82 #ifndef __ASSEMBLY__ 83 extern raw_spinlock_t nw_gpio_lock; 84 extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); 85 extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); 86 extern unsigned int nw_gpio_read(void); 87 extern void nw_cpld_modify(unsigned int mask, unsigned int set); 88 #endif 89 90 #endif 91