1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285 4 * 5 * Copyright (C) 1998-2001 Russell King 6 * Copyright (C) 1998-2000 Phil Blundell 7 */ 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/interrupt.h> 11 #include <linux/mm.h> 12 #include <linux/slab.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/io.h> 17 #include <linux/spinlock.h> 18 19 #include <asm/irq.h> 20 #include <asm/mach/pci.h> 21 #include <asm/hardware/dec21285.h> 22 23 #define MAX_SLOTS 21 24 25 #define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \ 26 PCI_STATUS_REC_TARGET_ABORT)<<16) 27 28 #define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \ 29 PCI_STATUS_REC_MASTER_ABORT | \ 30 PCI_STATUS_REC_TARGET_ABORT | \ 31 PCI_STATUS_PARITY) << 16) 32 33 extern int setup_arm_irq(int, struct irqaction *); 34 35 static unsigned long 36 dc21285_base_address(struct pci_bus *bus, unsigned int devfn) 37 { 38 unsigned long addr = 0; 39 40 if (bus->number == 0) { 41 if (PCI_SLOT(devfn) == 0) 42 /* 43 * For devfn 0, point at the 21285 44 */ 45 addr = ARMCSR_BASE; 46 else { 47 devfn -= 1 << 3; 48 49 if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) 50 addr = PCICFG0_BASE | 0xc00000 | (devfn << 8); 51 } 52 } else 53 addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8); 54 55 return addr; 56 } 57 58 static int 59 dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where, 60 int size, u32 *value) 61 { 62 unsigned long addr = dc21285_base_address(bus, devfn); 63 u32 v = 0xffffffff; 64 65 if (addr) 66 switch (size) { 67 case 1: 68 asm("ldrb %0, [%1, %2]" 69 : "=r" (v) : "r" (addr), "r" (where) : "cc"); 70 break; 71 case 2: 72 asm("ldrh %0, [%1, %2]" 73 : "=r" (v) : "r" (addr), "r" (where) : "cc"); 74 break; 75 case 4: 76 asm("ldr %0, [%1, %2]" 77 : "=r" (v) : "r" (addr), "r" (where) : "cc"); 78 break; 79 } 80 81 *value = v; 82 83 v = *CSR_PCICMD; 84 if (v & PCICMD_ABORT) { 85 *CSR_PCICMD = v & (0xffff|PCICMD_ABORT); 86 return -1; 87 } 88 89 return PCIBIOS_SUCCESSFUL; 90 } 91 92 static int 93 dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where, 94 int size, u32 value) 95 { 96 unsigned long addr = dc21285_base_address(bus, devfn); 97 u32 v; 98 99 if (addr) 100 switch (size) { 101 case 1: 102 asm("strb %0, [%1, %2]" 103 : : "r" (value), "r" (addr), "r" (where) 104 : "cc"); 105 break; 106 case 2: 107 asm("strh %0, [%1, %2]" 108 : : "r" (value), "r" (addr), "r" (where) 109 : "cc"); 110 break; 111 case 4: 112 asm("str %0, [%1, %2]" 113 : : "r" (value), "r" (addr), "r" (where) 114 : "cc"); 115 break; 116 } 117 118 v = *CSR_PCICMD; 119 if (v & PCICMD_ABORT) { 120 *CSR_PCICMD = v & (0xffff|PCICMD_ABORT); 121 return -1; 122 } 123 124 return PCIBIOS_SUCCESSFUL; 125 } 126 127 struct pci_ops dc21285_ops = { 128 .read = dc21285_read_config, 129 .write = dc21285_write_config, 130 }; 131 132 static struct timer_list serr_timer; 133 static struct timer_list perr_timer; 134 135 static void dc21285_enable_error(struct timer_list *timer) 136 { 137 del_timer(timer); 138 139 if (timer == &serr_timer) 140 enable_irq(IRQ_PCI_SERR); 141 else if (timer == &perr_timer) 142 enable_irq(IRQ_PCI_PERR); 143 } 144 145 /* 146 * Warn on PCI errors. 147 */ 148 static irqreturn_t dc21285_abort_irq(int irq, void *dev_id) 149 { 150 unsigned int cmd; 151 unsigned int status; 152 153 cmd = *CSR_PCICMD; 154 status = cmd >> 16; 155 cmd = cmd & 0xffff; 156 157 if (status & PCI_STATUS_REC_MASTER_ABORT) { 158 printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", 159 instruction_pointer(get_irq_regs())); 160 cmd |= PCI_STATUS_REC_MASTER_ABORT << 16; 161 } 162 163 if (status & PCI_STATUS_REC_TARGET_ABORT) { 164 printk(KERN_DEBUG "PCI: target abort: "); 165 pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT | 166 PCI_STATUS_SIG_TARGET_ABORT | 167 PCI_STATUS_REC_TARGET_ABORT, 1); 168 printk("\n"); 169 170 cmd |= PCI_STATUS_REC_TARGET_ABORT << 16; 171 } 172 173 *CSR_PCICMD = cmd; 174 175 return IRQ_HANDLED; 176 } 177 178 static irqreturn_t dc21285_serr_irq(int irq, void *dev_id) 179 { 180 struct timer_list *timer = dev_id; 181 unsigned int cntl; 182 183 printk(KERN_DEBUG "PCI: system error received: "); 184 pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1); 185 printk("\n"); 186 187 cntl = *CSR_SA110_CNTL & 0xffffdf07; 188 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR; 189 190 /* 191 * back off this interrupt 192 */ 193 disable_irq(irq); 194 timer->expires = jiffies + HZ; 195 add_timer(timer); 196 197 return IRQ_HANDLED; 198 } 199 200 static irqreturn_t dc21285_discard_irq(int irq, void *dev_id) 201 { 202 printk(KERN_DEBUG "PCI: discard timer expired\n"); 203 *CSR_SA110_CNTL &= 0xffffde07; 204 205 return IRQ_HANDLED; 206 } 207 208 static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id) 209 { 210 unsigned int cmd; 211 212 printk(KERN_DEBUG "PCI: data parity error detected: "); 213 pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1); 214 printk("\n"); 215 216 cmd = *CSR_PCICMD & 0xffff; 217 *CSR_PCICMD = cmd | 1 << 24; 218 219 return IRQ_HANDLED; 220 } 221 222 static irqreturn_t dc21285_parity_irq(int irq, void *dev_id) 223 { 224 struct timer_list *timer = dev_id; 225 unsigned int cmd; 226 227 printk(KERN_DEBUG "PCI: parity error detected: "); 228 pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1); 229 printk("\n"); 230 231 cmd = *CSR_PCICMD & 0xffff; 232 *CSR_PCICMD = cmd | 1 << 31; 233 234 /* 235 * back off this interrupt 236 */ 237 disable_irq(irq); 238 timer->expires = jiffies + HZ; 239 add_timer(timer); 240 241 return IRQ_HANDLED; 242 } 243 244 int __init dc21285_setup(int nr, struct pci_sys_data *sys) 245 { 246 struct resource *res; 247 248 if (nr || !footbridge_cfn_mode()) 249 return 0; 250 251 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); 252 if (!res) { 253 printk("out of memory for root bus resources"); 254 return 0; 255 } 256 257 res[0].flags = IORESOURCE_MEM; 258 res[0].name = "Footbridge non-prefetch"; 259 res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 260 res[1].name = "Footbridge prefetch"; 261 262 allocate_resource(&iomem_resource, &res[1], 0x20000000, 263 0xa0000000, 0xffffffff, 0x20000000, NULL, NULL); 264 allocate_resource(&iomem_resource, &res[0], 0x40000000, 265 0x80000000, 0xffffffff, 0x40000000, NULL, NULL); 266 267 sys->mem_offset = DC21285_PCI_MEM; 268 269 pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); 270 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 271 272 return 1; 273 } 274 275 #define dc21285_request_irq(_a, _b, _c, _d, _e) \ 276 WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0) 277 278 void __init dc21285_preinit(void) 279 { 280 unsigned int mem_size, mem_mask; 281 int cfn_mode; 282 283 pcibios_min_mem = 0x81000000; 284 285 mem_size = (unsigned int)high_memory - PAGE_OFFSET; 286 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) 287 if (mem_mask >= mem_size) 288 break; 289 290 /* 291 * These registers need to be set up whether we're the 292 * central function or not. 293 */ 294 *CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000; 295 *CSR_SDRAMBASEOFFSET = 0; 296 *CSR_ROMBASEMASK = 0x80000000; 297 *CSR_CSRBASEMASK = 0; 298 *CSR_CSRBASEOFFSET = 0; 299 *CSR_PCIADDR_EXTN = 0; 300 301 cfn_mode = __footbridge_cfn_mode(); 302 303 printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in " 304 "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ? 305 "central function" : "addin"); 306 307 if (footbridge_cfn_mode()) { 308 /* 309 * Clear any existing errors - we aren't 310 * interested in historical data... 311 */ 312 *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | 313 SA110_CNTL_RXSERR; 314 *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS; 315 } 316 317 timer_setup(&serr_timer, dc21285_enable_error, 0); 318 timer_setup(&perr_timer, dc21285_enable_error, 0); 319 320 /* 321 * We don't care if these fail. 322 */ 323 dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0, 324 "PCI system error", &serr_timer); 325 dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0, 326 "PCI parity error", &perr_timer); 327 dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0, 328 "PCI abort", NULL); 329 dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0, 330 "Discard timer", NULL); 331 dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0, 332 "PCI data parity", NULL); 333 334 if (cfn_mode) { 335 /* 336 * Map our SDRAM at a known address in PCI space, just in case 337 * the firmware had other ideas. Using a nonzero base is 338 * necessary, since some VGA cards forcefully use PCI addresses 339 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). 340 */ 341 *CSR_PCICSRBASE = 0xf4000000; 342 *CSR_PCICSRIOBASE = 0; 343 *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); 344 *CSR_PCIROMBASE = 0; 345 *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 346 PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS; 347 } else if (footbridge_cfn_mode() != 0) { 348 /* 349 * If we are not compiled to accept "add-in" mode, then 350 * we are using a constant virt_to_bus translation which 351 * can not hope to cater for the way the host BIOS has 352 * set up the machine. 353 */ 354 panic("PCI: this kernel is compiled for central " 355 "function mode only"); 356 } 357 } 358 359 void __init dc21285_postinit(void) 360 { 361 register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0); 362 } 363