1 /* 2 * linux/arch/arm/mach-footbridge/dc21285-timer.c 3 * 4 * Copyright (C) 1998 Russell King. 5 * Copyright (C) 1998 Phil Blundell 6 */ 7 #include <linux/clockchips.h> 8 #include <linux/clocksource.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 13 #include <asm/irq.h> 14 15 #include <asm/hardware/dec21285.h> 16 #include <asm/mach/time.h> 17 18 #include "common.h" 19 20 static cycle_t cksrc_dc21285_read(struct clocksource *cs) 21 { 22 return cs->mask - *CSR_TIMER2_VALUE; 23 } 24 25 static int cksrc_dc21285_enable(struct clocksource *cs) 26 { 27 *CSR_TIMER2_LOAD = cs->mask; 28 *CSR_TIMER2_CLR = 0; 29 *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; 30 return 0; 31 } 32 33 static void cksrc_dc21285_disable(struct clocksource *cs) 34 { 35 *CSR_TIMER2_CNTL = 0; 36 } 37 38 static struct clocksource cksrc_dc21285 = { 39 .name = "dc21285_timer2", 40 .rating = 200, 41 .read = cksrc_dc21285_read, 42 .enable = cksrc_dc21285_enable, 43 .disable = cksrc_dc21285_disable, 44 .mask = CLOCKSOURCE_MASK(24), 45 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 46 }; 47 48 static void ckevt_dc21285_set_mode(enum clock_event_mode mode, 49 struct clock_event_device *c) 50 { 51 switch (mode) { 52 case CLOCK_EVT_MODE_RESUME: 53 case CLOCK_EVT_MODE_PERIODIC: 54 *CSR_TIMER1_CLR = 0; 55 *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); 56 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | 57 TIMER_CNTL_DIV16; 58 break; 59 60 default: 61 *CSR_TIMER1_CNTL = 0; 62 break; 63 } 64 } 65 66 static struct clock_event_device ckevt_dc21285 = { 67 .name = "dc21285_timer1", 68 .features = CLOCK_EVT_FEAT_PERIODIC, 69 .rating = 200, 70 .irq = IRQ_TIMER1, 71 .set_mode = ckevt_dc21285_set_mode, 72 }; 73 74 static irqreturn_t timer1_interrupt(int irq, void *dev_id) 75 { 76 struct clock_event_device *ce = dev_id; 77 78 *CSR_TIMER1_CLR = 0; 79 80 ce->event_handler(ce); 81 82 return IRQ_HANDLED; 83 } 84 85 static struct irqaction footbridge_timer_irq = { 86 .name = "dc21285_timer1", 87 .handler = timer1_interrupt, 88 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 89 .dev_id = &ckevt_dc21285, 90 }; 91 92 /* 93 * Set up timer interrupt. 94 */ 95 static void __init footbridge_timer_init(void) 96 { 97 struct clock_event_device *ce = &ckevt_dc21285; 98 99 clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16); 100 101 setup_irq(ce->irq, &footbridge_timer_irq); 102 103 clockevents_calc_mult_shift(ce, mem_fclk_21285, 5); 104 ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce); 105 ce->min_delta_ns = clockevent_delta2ns(0x000004, ce); 106 ce->cpumask = cpumask_of(smp_processor_id()); 107 108 clockevents_register_device(ce); 109 } 110 111 struct sys_timer footbridge_timer = { 112 .init = footbridge_timer_init, 113 }; 114