1 /* 2 * linux/arch/arm/mach-footbridge/dc21285-timer.c 3 * 4 * Copyright (C) 1998 Russell King. 5 * Copyright (C) 1998 Phil Blundell 6 */ 7 #include <linux/clockchips.h> 8 #include <linux/clocksource.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/sched_clock.h> 13 14 #include <asm/irq.h> 15 16 #include <asm/hardware/dec21285.h> 17 #include <asm/mach/time.h> 18 #include <asm/system_info.h> 19 20 #include "common.h" 21 22 static cycle_t cksrc_dc21285_read(struct clocksource *cs) 23 { 24 return cs->mask - *CSR_TIMER2_VALUE; 25 } 26 27 static int cksrc_dc21285_enable(struct clocksource *cs) 28 { 29 *CSR_TIMER2_LOAD = cs->mask; 30 *CSR_TIMER2_CLR = 0; 31 *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; 32 return 0; 33 } 34 35 static void cksrc_dc21285_disable(struct clocksource *cs) 36 { 37 *CSR_TIMER2_CNTL = 0; 38 } 39 40 static struct clocksource cksrc_dc21285 = { 41 .name = "dc21285_timer2", 42 .rating = 200, 43 .read = cksrc_dc21285_read, 44 .enable = cksrc_dc21285_enable, 45 .disable = cksrc_dc21285_disable, 46 .mask = CLOCKSOURCE_MASK(24), 47 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 48 }; 49 50 static int ckevt_dc21285_set_next_event(unsigned long delta, 51 struct clock_event_device *c) 52 { 53 *CSR_TIMER1_CLR = 0; 54 *CSR_TIMER1_LOAD = delta; 55 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; 56 57 return 0; 58 } 59 60 static int ckevt_dc21285_shutdown(struct clock_event_device *c) 61 { 62 *CSR_TIMER1_CNTL = 0; 63 return 0; 64 } 65 66 static int ckevt_dc21285_set_periodic(struct clock_event_device *c) 67 { 68 *CSR_TIMER1_CLR = 0; 69 *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); 70 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | 71 TIMER_CNTL_DIV16; 72 return 0; 73 } 74 75 static struct clock_event_device ckevt_dc21285 = { 76 .name = "dc21285_timer1", 77 .features = CLOCK_EVT_FEAT_PERIODIC | 78 CLOCK_EVT_FEAT_ONESHOT, 79 .rating = 200, 80 .irq = IRQ_TIMER1, 81 .set_next_event = ckevt_dc21285_set_next_event, 82 .set_state_shutdown = ckevt_dc21285_shutdown, 83 .set_state_periodic = ckevt_dc21285_set_periodic, 84 .set_state_oneshot = ckevt_dc21285_shutdown, 85 .tick_resume = ckevt_dc21285_set_periodic, 86 }; 87 88 static irqreturn_t timer1_interrupt(int irq, void *dev_id) 89 { 90 struct clock_event_device *ce = dev_id; 91 92 *CSR_TIMER1_CLR = 0; 93 94 /* Stop the timer if in one-shot mode */ 95 if (clockevent_state_oneshot(ce)) 96 *CSR_TIMER1_CNTL = 0; 97 98 ce->event_handler(ce); 99 100 return IRQ_HANDLED; 101 } 102 103 static struct irqaction footbridge_timer_irq = { 104 .name = "dc21285_timer1", 105 .handler = timer1_interrupt, 106 .flags = IRQF_TIMER | IRQF_IRQPOLL, 107 .dev_id = &ckevt_dc21285, 108 }; 109 110 /* 111 * Set up timer interrupt. 112 */ 113 void __init footbridge_timer_init(void) 114 { 115 struct clock_event_device *ce = &ckevt_dc21285; 116 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); 117 118 clocksource_register_hz(&cksrc_dc21285, rate); 119 120 setup_irq(ce->irq, &footbridge_timer_irq); 121 122 ce->cpumask = cpumask_of(smp_processor_id()); 123 clockevents_config_and_register(ce, rate, 0x4, 0xffffff); 124 } 125 126 static u64 notrace footbridge_read_sched_clock(void) 127 { 128 return ~*CSR_TIMER3_VALUE; 129 } 130 131 void __init footbridge_sched_clock(void) 132 { 133 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); 134 135 *CSR_TIMER3_LOAD = 0; 136 *CSR_TIMER3_CLR = 0; 137 *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; 138 139 sched_clock_register(footbridge_read_sched_clock, 24, rate); 140 } 141