1 /* 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Suspend support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/of_address.h> 24 #include <linux/err.h> 25 #include <linux/regulator/machine.h> 26 27 #include <asm/cacheflush.h> 28 #include <asm/hardware/cache-l2x0.h> 29 #include <asm/firmware.h> 30 #include <asm/mcpm.h> 31 #include <asm/smp_scu.h> 32 #include <asm/suspend.h> 33 34 #include <plat/pm-common.h> 35 #include <plat/regs-srom.h> 36 37 #include "common.h" 38 #include "regs-pmu.h" 39 #include "exynos-pmu.h" 40 41 #define S5P_CHECK_SLEEP 0x00000BAD 42 43 #define REG_TABLE_END (-1U) 44 45 #define EXYNOS5420_CPU_STATE 0x28 46 47 /** 48 * struct exynos_wkup_irq - PMU IRQ to mask mapping 49 * @hwirq: Hardware IRQ signal of the PMU 50 * @mask: Mask in PMU wake-up mask register 51 */ 52 struct exynos_wkup_irq { 53 unsigned int hwirq; 54 u32 mask; 55 }; 56 57 static struct sleep_save exynos_core_save[] = { 58 /* SROM side */ 59 SAVE_ITEM(S5P_SROM_BW), 60 SAVE_ITEM(S5P_SROM_BC0), 61 SAVE_ITEM(S5P_SROM_BC1), 62 SAVE_ITEM(S5P_SROM_BC2), 63 SAVE_ITEM(S5P_SROM_BC3), 64 }; 65 66 struct exynos_pm_data { 67 const struct exynos_wkup_irq *wkup_irq; 68 unsigned int wake_disable_mask; 69 unsigned int *release_ret_regs; 70 71 void (*pm_prepare)(void); 72 void (*pm_resume_prepare)(void); 73 void (*pm_resume)(void); 74 int (*pm_suspend)(void); 75 int (*cpu_suspend)(unsigned long); 76 }; 77 78 static const struct exynos_pm_data *pm_data; 79 80 static int exynos5420_cpu_state; 81 static unsigned int exynos_pmu_spare3; 82 83 /* 84 * GIC wake-up support 85 */ 86 87 static u32 exynos_irqwake_intmask = 0xffffffff; 88 89 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = { 90 { 73, BIT(1) }, /* RTC alarm */ 91 { 74, BIT(2) }, /* RTC tick */ 92 { /* sentinel */ }, 93 }; 94 95 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 96 { 44, BIT(1) }, /* RTC alarm */ 97 { 45, BIT(2) }, /* RTC tick */ 98 { /* sentinel */ }, 99 }; 100 101 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 102 { 43, BIT(1) }, /* RTC alarm */ 103 { 44, BIT(2) }, /* RTC tick */ 104 { /* sentinel */ }, 105 }; 106 107 static unsigned int exynos_release_ret_regs[] = { 108 S5P_PAD_RET_MAUDIO_OPTION, 109 S5P_PAD_RET_GPIO_OPTION, 110 S5P_PAD_RET_UART_OPTION, 111 S5P_PAD_RET_MMCA_OPTION, 112 S5P_PAD_RET_MMCB_OPTION, 113 S5P_PAD_RET_EBIA_OPTION, 114 S5P_PAD_RET_EBIB_OPTION, 115 REG_TABLE_END, 116 }; 117 118 static unsigned int exynos3250_release_ret_regs[] = { 119 S5P_PAD_RET_MAUDIO_OPTION, 120 S5P_PAD_RET_GPIO_OPTION, 121 S5P_PAD_RET_UART_OPTION, 122 S5P_PAD_RET_MMCA_OPTION, 123 S5P_PAD_RET_MMCB_OPTION, 124 S5P_PAD_RET_EBIA_OPTION, 125 S5P_PAD_RET_EBIB_OPTION, 126 S5P_PAD_RET_MMC2_OPTION, 127 S5P_PAD_RET_SPI_OPTION, 128 REG_TABLE_END, 129 }; 130 131 static unsigned int exynos5420_release_ret_regs[] = { 132 EXYNOS_PAD_RET_DRAM_OPTION, 133 EXYNOS_PAD_RET_MAUDIO_OPTION, 134 EXYNOS_PAD_RET_JTAG_OPTION, 135 EXYNOS5420_PAD_RET_GPIO_OPTION, 136 EXYNOS5420_PAD_RET_UART_OPTION, 137 EXYNOS5420_PAD_RET_MMCA_OPTION, 138 EXYNOS5420_PAD_RET_MMCB_OPTION, 139 EXYNOS5420_PAD_RET_MMCC_OPTION, 140 EXYNOS5420_PAD_RET_HSI_OPTION, 141 EXYNOS_PAD_RET_EBIA_OPTION, 142 EXYNOS_PAD_RET_EBIB_OPTION, 143 EXYNOS5420_PAD_RET_SPI_OPTION, 144 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 145 REG_TABLE_END, 146 }; 147 148 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 149 { 150 const struct exynos_wkup_irq *wkup_irq; 151 152 if (!pm_data->wkup_irq) 153 return -ENOENT; 154 wkup_irq = pm_data->wkup_irq; 155 156 while (wkup_irq->mask) { 157 if (wkup_irq->hwirq == data->hwirq) { 158 if (!state) 159 exynos_irqwake_intmask |= wkup_irq->mask; 160 else 161 exynos_irqwake_intmask &= ~wkup_irq->mask; 162 return 0; 163 } 164 ++wkup_irq; 165 } 166 167 return -ENOENT; 168 } 169 170 static struct irq_chip exynos_pmu_chip = { 171 .name = "PMU", 172 .irq_eoi = irq_chip_eoi_parent, 173 .irq_mask = irq_chip_mask_parent, 174 .irq_unmask = irq_chip_unmask_parent, 175 .irq_retrigger = irq_chip_retrigger_hierarchy, 176 .irq_set_wake = exynos_irq_set_wake, 177 #ifdef CONFIG_SMP 178 .irq_set_affinity = irq_chip_set_affinity_parent, 179 #endif 180 }; 181 182 static int exynos_pmu_domain_xlate(struct irq_domain *domain, 183 struct device_node *controller, 184 const u32 *intspec, 185 unsigned int intsize, 186 unsigned long *out_hwirq, 187 unsigned int *out_type) 188 { 189 if (domain->of_node != controller) 190 return -EINVAL; /* Shouldn't happen, really... */ 191 if (intsize != 3) 192 return -EINVAL; /* Not GIC compliant */ 193 if (intspec[0] != 0) 194 return -EINVAL; /* No PPI should point to this domain */ 195 196 *out_hwirq = intspec[1]; 197 *out_type = intspec[2]; 198 return 0; 199 } 200 201 static int exynos_pmu_domain_alloc(struct irq_domain *domain, 202 unsigned int virq, 203 unsigned int nr_irqs, void *data) 204 { 205 struct of_phandle_args *args = data; 206 struct of_phandle_args parent_args; 207 irq_hw_number_t hwirq; 208 int i; 209 210 if (args->args_count != 3) 211 return -EINVAL; /* Not GIC compliant */ 212 if (args->args[0] != 0) 213 return -EINVAL; /* No PPI should point to this domain */ 214 215 hwirq = args->args[1]; 216 217 for (i = 0; i < nr_irqs; i++) 218 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 219 &exynos_pmu_chip, NULL); 220 221 parent_args = *args; 222 parent_args.np = domain->parent->of_node; 223 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args); 224 } 225 226 static const struct irq_domain_ops exynos_pmu_domain_ops = { 227 .xlate = exynos_pmu_domain_xlate, 228 .alloc = exynos_pmu_domain_alloc, 229 .free = irq_domain_free_irqs_common, 230 }; 231 232 static int __init exynos_pmu_irq_init(struct device_node *node, 233 struct device_node *parent) 234 { 235 struct irq_domain *parent_domain, *domain; 236 237 if (!parent) { 238 pr_err("%s: no parent, giving up\n", node->full_name); 239 return -ENODEV; 240 } 241 242 parent_domain = irq_find_host(parent); 243 if (!parent_domain) { 244 pr_err("%s: unable to obtain parent domain\n", node->full_name); 245 return -ENXIO; 246 } 247 248 pmu_base_addr = of_iomap(node, 0); 249 250 if (!pmu_base_addr) { 251 pr_err("%s: failed to find exynos pmu register\n", 252 node->full_name); 253 return -ENOMEM; 254 } 255 256 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, 257 node, &exynos_pmu_domain_ops, 258 NULL); 259 if (!domain) { 260 iounmap(pmu_base_addr); 261 return -ENOMEM; 262 } 263 264 return 0; 265 } 266 267 #define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init) 268 269 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); 270 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); 271 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); 272 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); 273 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu"); 274 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); 275 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); 276 277 static int exynos_cpu_do_idle(void) 278 { 279 /* issue the standby signal into the pm unit. */ 280 cpu_do_idle(); 281 282 pr_info("Failed to suspend the system\n"); 283 return 1; /* Aborting suspend */ 284 } 285 static void exynos_flush_cache_all(void) 286 { 287 flush_cache_all(); 288 outer_flush_all(); 289 } 290 291 static int exynos_cpu_suspend(unsigned long arg) 292 { 293 exynos_flush_cache_all(); 294 return exynos_cpu_do_idle(); 295 } 296 297 static int exynos3250_cpu_suspend(unsigned long arg) 298 { 299 flush_cache_all(); 300 return exynos_cpu_do_idle(); 301 } 302 303 static int exynos5420_cpu_suspend(unsigned long arg) 304 { 305 /* MCPM works with HW CPU identifiers */ 306 unsigned int mpidr = read_cpuid_mpidr(); 307 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 308 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 309 310 __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); 311 312 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { 313 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); 314 mcpm_cpu_suspend(); 315 } 316 317 pr_info("Failed to suspend the system\n"); 318 319 /* return value != 0 means failure */ 320 return 1; 321 } 322 323 static void exynos_pm_set_wakeup_mask(void) 324 { 325 /* Set wake-up mask registers */ 326 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 327 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 328 } 329 330 static void exynos_pm_enter_sleep_mode(void) 331 { 332 /* Set value of power down register for sleep mode */ 333 exynos_sys_powerdown_conf(SYS_SLEEP); 334 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 335 } 336 337 static void exynos_pm_prepare(void) 338 { 339 exynos_set_delayed_reset_assertion(false); 340 341 /* Set wake-up mask registers */ 342 exynos_pm_set_wakeup_mask(); 343 344 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 345 346 exynos_pm_enter_sleep_mode(); 347 348 /* ensure at least INFORM0 has the resume address */ 349 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 350 } 351 352 static void exynos3250_pm_prepare(void) 353 { 354 unsigned int tmp; 355 356 /* Set wake-up mask registers */ 357 exynos_pm_set_wakeup_mask(); 358 359 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION); 360 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 361 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION); 362 363 exynos_pm_enter_sleep_mode(); 364 365 /* ensure at least INFORM0 has the resume address */ 366 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 367 } 368 369 static void exynos5420_pm_prepare(void) 370 { 371 unsigned int tmp; 372 373 /* Set wake-up mask registers */ 374 exynos_pm_set_wakeup_mask(); 375 376 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 377 378 exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); 379 /* 380 * The cpu state needs to be saved and restored so that the 381 * secondary CPUs will enter low power start. Though the U-Boot 382 * is setting the cpu state with low power flag, the kernel 383 * needs to restore it back in case, the primary cpu fails to 384 * suspend for any reason. 385 */ 386 exynos5420_cpu_state = __raw_readl(sysram_base_addr + 387 EXYNOS5420_CPU_STATE); 388 389 exynos_pm_enter_sleep_mode(); 390 391 /* ensure at least INFORM0 has the resume address */ 392 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 393 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); 394 395 tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); 396 tmp &= ~EXYNOS5_USE_RETENTION; 397 pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); 398 399 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 400 tmp |= EXYNOS5420_UFS; 401 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 402 403 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); 404 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; 405 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION); 406 407 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 408 tmp |= EXYNOS5420_EMULATION; 409 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 410 411 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 412 tmp |= EXYNOS5420_EMULATION; 413 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 414 } 415 416 417 static int exynos_pm_suspend(void) 418 { 419 exynos_pm_central_suspend(); 420 421 /* Setting SEQ_OPTION register */ 422 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, 423 S5P_CENTRAL_SEQ_OPTION); 424 425 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 426 exynos_cpu_save_register(); 427 428 return 0; 429 } 430 431 static int exynos5420_pm_suspend(void) 432 { 433 u32 this_cluster; 434 435 exynos_pm_central_suspend(); 436 437 /* Setting SEQ_OPTION register */ 438 439 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); 440 if (!this_cluster) 441 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0, 442 S5P_CENTRAL_SEQ_OPTION); 443 else 444 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0, 445 S5P_CENTRAL_SEQ_OPTION); 446 return 0; 447 } 448 449 static void exynos_pm_release_retention(void) 450 { 451 unsigned int i; 452 453 for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) 454 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, 455 pm_data->release_ret_regs[i]); 456 } 457 458 static void exynos_pm_resume(void) 459 { 460 u32 cpuid = read_cpuid_part(); 461 462 if (exynos_pm_central_resume()) 463 goto early_wakeup; 464 465 /* For release retention */ 466 exynos_pm_release_retention(); 467 468 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 469 470 if (cpuid == ARM_CPU_PART_CORTEX_A9) 471 scu_enable(S5P_VA_SCU); 472 473 if (call_firmware_op(resume) == -ENOSYS 474 && cpuid == ARM_CPU_PART_CORTEX_A9) 475 exynos_cpu_restore_register(); 476 477 early_wakeup: 478 479 /* Clear SLEEP mode set in INFORM1 */ 480 pmu_raw_writel(0x0, S5P_INFORM1); 481 exynos_set_delayed_reset_assertion(true); 482 } 483 484 static void exynos3250_pm_resume(void) 485 { 486 u32 cpuid = read_cpuid_part(); 487 488 if (exynos_pm_central_resume()) 489 goto early_wakeup; 490 491 /* For release retention */ 492 exynos_pm_release_retention(); 493 494 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); 495 496 if (call_firmware_op(resume) == -ENOSYS 497 && cpuid == ARM_CPU_PART_CORTEX_A9) 498 exynos_cpu_restore_register(); 499 500 early_wakeup: 501 502 /* Clear SLEEP mode set in INFORM1 */ 503 pmu_raw_writel(0x0, S5P_INFORM1); 504 } 505 506 static void exynos5420_prepare_pm_resume(void) 507 { 508 if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) 509 WARN_ON(mcpm_cpu_powered_up()); 510 } 511 512 static void exynos5420_pm_resume(void) 513 { 514 unsigned long tmp; 515 516 /* Restore the CPU0 low power state register */ 517 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); 518 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, 519 EXYNOS5_ARM_CORE0_SYS_PWR_REG); 520 521 /* Restore the sysram cpu state register */ 522 __raw_writel(exynos5420_cpu_state, 523 sysram_base_addr + EXYNOS5420_CPU_STATE); 524 525 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, 526 S5P_CENTRAL_SEQ_OPTION); 527 528 if (exynos_pm_central_resume()) 529 goto early_wakeup; 530 531 /* For release retention */ 532 exynos_pm_release_retention(); 533 534 pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); 535 536 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 537 538 early_wakeup: 539 540 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); 541 tmp &= ~EXYNOS5420_UFS; 542 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); 543 544 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION); 545 tmp &= ~EXYNOS5420_EMULATION; 546 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION); 547 548 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION); 549 tmp &= ~EXYNOS5420_EMULATION; 550 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); 551 552 /* Clear SLEEP mode set in INFORM1 */ 553 pmu_raw_writel(0x0, S5P_INFORM1); 554 } 555 556 /* 557 * Suspend Ops 558 */ 559 560 static int exynos_suspend_enter(suspend_state_t state) 561 { 562 int ret; 563 564 s3c_pm_debug_init(); 565 566 S3C_PMDBG("%s: suspending the system...\n", __func__); 567 568 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 569 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 570 571 if (exynos_irqwake_intmask == -1U 572 && exynos_get_eint_wake_mask() == -1U) { 573 pr_err("%s: No wake-up sources!\n", __func__); 574 pr_err("%s: Aborting sleep\n", __func__); 575 return -EINVAL; 576 } 577 578 s3c_pm_save_uarts(); 579 if (pm_data->pm_prepare) 580 pm_data->pm_prepare(); 581 flush_cache_all(); 582 s3c_pm_check_store(); 583 584 ret = call_firmware_op(suspend); 585 if (ret == -ENOSYS) 586 ret = cpu_suspend(0, pm_data->cpu_suspend); 587 if (ret) 588 return ret; 589 590 if (pm_data->pm_resume_prepare) 591 pm_data->pm_resume_prepare(); 592 s3c_pm_restore_uarts(); 593 594 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 595 pmu_raw_readl(S5P_WAKEUP_STAT)); 596 597 s3c_pm_check_restore(); 598 599 S3C_PMDBG("%s: resuming the system...\n", __func__); 600 601 return 0; 602 } 603 604 static int exynos_suspend_prepare(void) 605 { 606 int ret; 607 608 /* 609 * REVISIT: It would be better if struct platform_suspend_ops 610 * .prepare handler get the suspend_state_t as a parameter to 611 * avoid hard-coding the suspend to mem state. It's safe to do 612 * it now only because the suspend_valid_only_mem function is 613 * used as the .valid callback used to check if a given state 614 * is supported by the platform anyways. 615 */ 616 ret = regulator_suspend_prepare(PM_SUSPEND_MEM); 617 if (ret) { 618 pr_err("Failed to prepare regulators for suspend (%d)\n", ret); 619 return ret; 620 } 621 622 s3c_pm_check_prepare(); 623 624 return 0; 625 } 626 627 static void exynos_suspend_finish(void) 628 { 629 int ret; 630 631 s3c_pm_check_cleanup(); 632 633 ret = regulator_suspend_finish(); 634 if (ret) 635 pr_warn("Failed to resume regulators from suspend (%d)\n", ret); 636 } 637 638 static const struct platform_suspend_ops exynos_suspend_ops = { 639 .enter = exynos_suspend_enter, 640 .prepare = exynos_suspend_prepare, 641 .finish = exynos_suspend_finish, 642 .valid = suspend_valid_only_mem, 643 }; 644 645 static const struct exynos_pm_data exynos3250_pm_data = { 646 .wkup_irq = exynos3250_wkup_irq, 647 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 648 .release_ret_regs = exynos3250_release_ret_regs, 649 .pm_suspend = exynos_pm_suspend, 650 .pm_resume = exynos3250_pm_resume, 651 .pm_prepare = exynos3250_pm_prepare, 652 .cpu_suspend = exynos3250_cpu_suspend, 653 }; 654 655 static const struct exynos_pm_data exynos4_pm_data = { 656 .wkup_irq = exynos4_wkup_irq, 657 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 658 .release_ret_regs = exynos_release_ret_regs, 659 .pm_suspend = exynos_pm_suspend, 660 .pm_resume = exynos_pm_resume, 661 .pm_prepare = exynos_pm_prepare, 662 .cpu_suspend = exynos_cpu_suspend, 663 }; 664 665 static const struct exynos_pm_data exynos5250_pm_data = { 666 .wkup_irq = exynos5250_wkup_irq, 667 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 668 .release_ret_regs = exynos_release_ret_regs, 669 .pm_suspend = exynos_pm_suspend, 670 .pm_resume = exynos_pm_resume, 671 .pm_prepare = exynos_pm_prepare, 672 .cpu_suspend = exynos_cpu_suspend, 673 }; 674 675 static const struct exynos_pm_data exynos5420_pm_data = { 676 .wkup_irq = exynos5250_wkup_irq, 677 .wake_disable_mask = (0x7F << 7) | (0x1F << 1), 678 .release_ret_regs = exynos5420_release_ret_regs, 679 .pm_resume_prepare = exynos5420_prepare_pm_resume, 680 .pm_resume = exynos5420_pm_resume, 681 .pm_suspend = exynos5420_pm_suspend, 682 .pm_prepare = exynos5420_pm_prepare, 683 .cpu_suspend = exynos5420_cpu_suspend, 684 }; 685 686 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { 687 { 688 .compatible = "samsung,exynos3250-pmu", 689 .data = &exynos3250_pm_data, 690 }, { 691 .compatible = "samsung,exynos4210-pmu", 692 .data = &exynos4_pm_data, 693 }, { 694 .compatible = "samsung,exynos4212-pmu", 695 .data = &exynos4_pm_data, 696 }, { 697 .compatible = "samsung,exynos4412-pmu", 698 .data = &exynos4_pm_data, 699 }, { 700 .compatible = "samsung,exynos5250-pmu", 701 .data = &exynos5250_pm_data, 702 }, { 703 .compatible = "samsung,exynos5420-pmu", 704 .data = &exynos5420_pm_data, 705 }, 706 { /*sentinel*/ }, 707 }; 708 709 static struct syscore_ops exynos_pm_syscore_ops; 710 711 void __init exynos_pm_init(void) 712 { 713 const struct of_device_id *match; 714 struct device_node *np; 715 u32 tmp; 716 717 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); 718 if (!np) { 719 pr_err("Failed to find PMU node\n"); 720 return; 721 } 722 723 if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) { 724 pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); 725 return; 726 } 727 728 pm_data = (const struct exynos_pm_data *) match->data; 729 730 /* All wakeup disable */ 731 tmp = pmu_raw_readl(S5P_WAKEUP_MASK); 732 tmp |= pm_data->wake_disable_mask; 733 pmu_raw_writel(tmp, S5P_WAKEUP_MASK); 734 735 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; 736 exynos_pm_syscore_ops.resume = pm_data->pm_resume; 737 738 register_syscore_ops(&exynos_pm_syscore_ops); 739 suspend_set_ops(&exynos_suspend_ops); 740 } 741