1d710aa31STomasz Figa/* 2d710aa31STomasz Figa * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3d710aa31STomasz Figa * http://www.samsung.com 4d710aa31STomasz Figa * 5d710aa31STomasz Figa * Exynos low-level resume code 6d710aa31STomasz Figa * 7d710aa31STomasz Figa * This program is free software; you can redistribute it and/or modify 8d710aa31STomasz Figa * it under the terms of the GNU General Public License as published by 9d710aa31STomasz Figa * the Free Software Foundation; either version 2 of the License, or 10d710aa31STomasz Figa * (at your option) any later version. 11d710aa31STomasz Figa * 12d710aa31STomasz Figa * This program is distributed in the hope that it will be useful, 13d710aa31STomasz Figa * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d710aa31STomasz Figa * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d710aa31STomasz Figa * GNU General Public License for more details. 16d710aa31STomasz Figa */ 17d710aa31STomasz Figa 18d710aa31STomasz Figa#include <linux/linkage.h> 1930ad527aSTomasz Figa#include <asm/asm-offsets.h> 2030ad527aSTomasz Figa#include <asm/hardware/cache-l2x0.h> 212b9d9c32STomasz Figa#include "smc.h" 22d710aa31STomasz Figa 23d710aa31STomasz Figa#define CPU_MASK 0xff0ffff0 24d710aa31STomasz Figa#define CPU_CORTEX_A9 0x410fc090 25d710aa31STomasz Figa 2612833bacSArd Biesheuvel .text 27d710aa31STomasz Figa .align 28d710aa31STomasz Figa 29d710aa31STomasz Figa /* 30d710aa31STomasz Figa * sleep magic, to allow the bootloader to check for an valid 31d710aa31STomasz Figa * image to resume to. Must be the first word before the 32d710aa31STomasz Figa * exynos_cpu_resume entry. 33d710aa31STomasz Figa */ 34d710aa31STomasz Figa 35d710aa31STomasz Figa .word 0x2bedf00d 36d710aa31STomasz Figa 37d710aa31STomasz Figa /* 38d710aa31STomasz Figa * exynos_cpu_resume 39d710aa31STomasz Figa * 40d710aa31STomasz Figa * resume code entry for bootloader to call 41d710aa31STomasz Figa */ 42d710aa31STomasz Figa 43d710aa31STomasz FigaENTRY(exynos_cpu_resume) 44d710aa31STomasz Figa#ifdef CONFIG_CACHE_L2X0 45d710aa31STomasz Figa mrc p15, 0, r0, c0, c0, 0 46d710aa31STomasz Figa ldr r1, =CPU_MASK 47d710aa31STomasz Figa and r0, r0, r1 48d710aa31STomasz Figa ldr r1, =CPU_CORTEX_A9 49d710aa31STomasz Figa cmp r0, r1 5025a9ef63SRussell King bleq l2c310_early_resume 51d710aa31STomasz Figa#endif 52d710aa31STomasz Figa b cpu_resume 53d710aa31STomasz FigaENDPROC(exynos_cpu_resume) 542b9d9c32STomasz Figa 552b9d9c32STomasz Figa .align 562b9d9c32STomasz Figa 572b9d9c32STomasz FigaENTRY(exynos_cpu_resume_ns) 582b9d9c32STomasz Figa mrc p15, 0, r0, c0, c0, 0 592b9d9c32STomasz Figa ldr r1, =CPU_MASK 602b9d9c32STomasz Figa and r0, r0, r1 612b9d9c32STomasz Figa ldr r1, =CPU_CORTEX_A9 622b9d9c32STomasz Figa cmp r0, r1 632b9d9c32STomasz Figa bne skip_cp15 642b9d9c32STomasz Figa 6512833bacSArd Biesheuvel adr r0, _cp15_save_power 662b9d9c32STomasz Figa ldr r1, [r0] 6712833bacSArd Biesheuvel ldr r1, [r0, r1] 6812833bacSArd Biesheuvel adr r0, _cp15_save_diag 692b9d9c32STomasz Figa ldr r2, [r0] 7012833bacSArd Biesheuvel ldr r2, [r0, r2] 712b9d9c32STomasz Figa mov r0, #SMC_CMD_C15RESUME 722b9d9c32STomasz Figa dsb 732b9d9c32STomasz Figa smc #0 7430ad527aSTomasz Figa#ifdef CONFIG_CACHE_L2X0 7530ad527aSTomasz Figa adr r0, 1f 7630ad527aSTomasz Figa ldr r2, [r0] 7730ad527aSTomasz Figa add r0, r2, r0 7830ad527aSTomasz Figa 7930ad527aSTomasz Figa /* Check that the address has been initialised. */ 8030ad527aSTomasz Figa ldr r1, [r0, #L2X0_R_PHY_BASE] 8130ad527aSTomasz Figa teq r1, #0 8230ad527aSTomasz Figa beq skip_l2x0 8330ad527aSTomasz Figa 8430ad527aSTomasz Figa /* Check if controller has been enabled. */ 8530ad527aSTomasz Figa ldr r2, [r1, #L2X0_CTRL] 8630ad527aSTomasz Figa tst r2, #0x1 8730ad527aSTomasz Figa bne skip_l2x0 8830ad527aSTomasz Figa 8930ad527aSTomasz Figa ldr r1, [r0, #L2X0_R_TAG_LATENCY] 9030ad527aSTomasz Figa ldr r2, [r0, #L2X0_R_DATA_LATENCY] 9130ad527aSTomasz Figa ldr r3, [r0, #L2X0_R_PREFETCH_CTRL] 9230ad527aSTomasz Figa mov r0, #SMC_CMD_L2X0SETUP1 9330ad527aSTomasz Figa smc #0 9430ad527aSTomasz Figa 9530ad527aSTomasz Figa /* Reload saved regs pointer because smc corrupts registers. */ 9630ad527aSTomasz Figa adr r0, 1f 9730ad527aSTomasz Figa ldr r2, [r0] 9830ad527aSTomasz Figa add r0, r2, r0 9930ad527aSTomasz Figa 10030ad527aSTomasz Figa ldr r1, [r0, #L2X0_R_PWR_CTRL] 10130ad527aSTomasz Figa ldr r2, [r0, #L2X0_R_AUX_CTRL] 10230ad527aSTomasz Figa mov r0, #SMC_CMD_L2X0SETUP2 10330ad527aSTomasz Figa smc #0 10430ad527aSTomasz Figa 10530ad527aSTomasz Figa mov r0, #SMC_CMD_L2X0INVALL 10630ad527aSTomasz Figa smc #0 10730ad527aSTomasz Figa 10830ad527aSTomasz Figa mov r1, #1 10930ad527aSTomasz Figa mov r0, #SMC_CMD_L2X0CTRL 11030ad527aSTomasz Figa smc #0 11130ad527aSTomasz Figaskip_l2x0: 11230ad527aSTomasz Figa#endif /* CONFIG_CACHE_L2X0 */ 1132b9d9c32STomasz Figaskip_cp15: 1142b9d9c32STomasz Figa b cpu_resume 1152b9d9c32STomasz FigaENDPROC(exynos_cpu_resume_ns) 11612833bacSArd Biesheuvel 11712833bacSArd Biesheuvel .align 11812833bacSArd Biesheuvel_cp15_save_power: 11912833bacSArd Biesheuvel .long cp15_save_power - . 12012833bacSArd Biesheuvel_cp15_save_diag: 12112833bacSArd Biesheuvel .long cp15_save_diag - . 12212833bacSArd Biesheuvel#ifdef CONFIG_CACHE_L2X0 12312833bacSArd Biesheuvel1: .long l2x0_saved_regs - . 12412833bacSArd Biesheuvel#endif /* CONFIG_CACHE_L2X0 */ 12512833bacSArd Biesheuvel 12612833bacSArd Biesheuvel .data 127*1abd3502SRussell King .align 2 1282b9d9c32STomasz Figa .globl cp15_save_diag 1292b9d9c32STomasz Figacp15_save_diag: 1302b9d9c32STomasz Figa .long 0 @ cp15 diagnostic 1312b9d9c32STomasz Figa .globl cp15_save_power 1322b9d9c32STomasz Figacp15_save_power: 1332b9d9c32STomasz Figa .long 0 @ cp15 power control 134