1 /* 2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * EXYNOS - Power Management support 6 * 7 * Based on arch/arm/mach-s3c2410/pm.c 8 * Copyright (c) 2006 Simtec Electronics 9 * Ben Dooks <ben@simtec.co.uk> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/suspend.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/io.h> 20 #include <linux/irqchip/arm-gic.h> 21 #include <linux/err.h> 22 #include <linux/clk.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/hardware/cache-l2x0.h> 26 #include <asm/smp_scu.h> 27 #include <asm/suspend.h> 28 29 #include <plat/cpu.h> 30 #include <plat/pm-common.h> 31 #include <plat/pll.h> 32 #include <plat/regs-srom.h> 33 34 #include <mach/map.h> 35 36 #include "common.h" 37 #include "regs-pmu.h" 38 39 /** 40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping 41 * @hwirq: Hardware IRQ signal of the GIC 42 * @mask: Mask in PMU wake-up mask register 43 */ 44 struct exynos_wkup_irq { 45 unsigned int hwirq; 46 u32 mask; 47 }; 48 49 static struct sleep_save exynos5_sys_save[] = { 50 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), 51 }; 52 53 static struct sleep_save exynos_core_save[] = { 54 /* SROM side */ 55 SAVE_ITEM(S5P_SROM_BW), 56 SAVE_ITEM(S5P_SROM_BC0), 57 SAVE_ITEM(S5P_SROM_BC1), 58 SAVE_ITEM(S5P_SROM_BC2), 59 SAVE_ITEM(S5P_SROM_BC3), 60 }; 61 62 /* 63 * GIC wake-up support 64 */ 65 66 static u32 exynos_irqwake_intmask = 0xffffffff; 67 68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = { 69 { 76, BIT(1) }, /* RTC alarm */ 70 { 77, BIT(2) }, /* RTC tick */ 71 { /* sentinel */ }, 72 }; 73 74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { 75 { 75, BIT(1) }, /* RTC alarm */ 76 { 76, BIT(2) }, /* RTC tick */ 77 { /* sentinel */ }, 78 }; 79 80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 81 { 82 const struct exynos_wkup_irq *wkup_irq; 83 84 if (soc_is_exynos5250()) 85 wkup_irq = exynos5250_wkup_irq; 86 else 87 wkup_irq = exynos4_wkup_irq; 88 89 while (wkup_irq->mask) { 90 if (wkup_irq->hwirq == data->hwirq) { 91 if (!state) 92 exynos_irqwake_intmask |= wkup_irq->mask; 93 else 94 exynos_irqwake_intmask &= ~wkup_irq->mask; 95 return 0; 96 } 97 ++wkup_irq; 98 } 99 100 return -ENOENT; 101 } 102 103 /** 104 * exynos_core_power_down : power down the specified cpu 105 * @cpu : the cpu to power down 106 * 107 * Power down the specified cpu. The sequence must be finished by a 108 * call to cpu_do_idle() 109 * 110 */ 111 void exynos_cpu_power_down(int cpu) 112 { 113 __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 114 } 115 116 /** 117 * exynos_cpu_power_up : power up the specified cpu 118 * @cpu : the cpu to power up 119 * 120 * Power up the specified cpu 121 */ 122 void exynos_cpu_power_up(int cpu) 123 { 124 __raw_writel(S5P_CORE_LOCAL_PWR_EN, 125 EXYNOS_ARM_CORE_CONFIGURATION(cpu)); 126 } 127 128 /** 129 * exynos_cpu_power_state : returns the power state of the cpu 130 * @cpu : the cpu to retrieve the power state from 131 * 132 */ 133 int exynos_cpu_power_state(int cpu) 134 { 135 return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & 136 S5P_CORE_LOCAL_PWR_EN); 137 } 138 139 /* For Cortex-A9 Diagnostic and Power control register */ 140 static unsigned int save_arm_register[2]; 141 142 static int exynos_cpu_suspend(unsigned long arg) 143 { 144 #ifdef CONFIG_CACHE_L2X0 145 outer_flush_all(); 146 #endif 147 148 if (soc_is_exynos5250()) 149 flush_cache_all(); 150 151 /* issue the standby signal into the pm unit. */ 152 cpu_do_idle(); 153 154 pr_info("Failed to suspend the system\n"); 155 return 1; /* Aborting suspend */ 156 } 157 158 static void exynos_pm_prepare(void) 159 { 160 unsigned int tmp; 161 162 /* Set wake-up mask registers */ 163 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); 164 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 165 166 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 167 168 if (soc_is_exynos5250()) { 169 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); 170 /* Disable USE_RETENTION of JPEG_MEM_OPTION */ 171 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); 172 tmp &= ~EXYNOS5_OPTION_USE_RETENTION; 173 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); 174 } 175 176 /* Set value of power down register for sleep mode */ 177 178 exynos_sys_powerdown_conf(SYS_SLEEP); 179 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 180 181 /* ensure at least INFORM0 has the resume address */ 182 183 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); 184 } 185 186 static int exynos_pm_suspend(void) 187 { 188 unsigned long tmp; 189 190 /* Setting Central Sequence Register for power down mode */ 191 192 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 193 tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 194 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 195 196 /* Setting SEQ_OPTION register */ 197 198 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); 199 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); 200 201 if (!soc_is_exynos5250()) { 202 /* Save Power control register */ 203 asm ("mrc p15, 0, %0, c15, c0, 0" 204 : "=r" (tmp) : : "cc"); 205 save_arm_register[0] = tmp; 206 207 /* Save Diagnostic register */ 208 asm ("mrc p15, 0, %0, c15, c0, 1" 209 : "=r" (tmp) : : "cc"); 210 save_arm_register[1] = tmp; 211 } 212 213 return 0; 214 } 215 216 static void exynos_pm_resume(void) 217 { 218 unsigned long tmp; 219 220 /* 221 * If PMU failed while entering sleep mode, WFI will be 222 * ignored by PMU and then exiting cpu_do_idle(). 223 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 224 * in this situation. 225 */ 226 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 227 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 228 tmp |= S5P_CENTRAL_LOWPWR_CFG; 229 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 230 /* clear the wakeup state register */ 231 __raw_writel(0x0, S5P_WAKEUP_STAT); 232 /* No need to perform below restore code */ 233 goto early_wakeup; 234 } 235 if (!soc_is_exynos5250()) { 236 /* Restore Power control register */ 237 tmp = save_arm_register[0]; 238 asm volatile ("mcr p15, 0, %0, c15, c0, 0" 239 : : "r" (tmp) 240 : "cc"); 241 242 /* Restore Diagnostic register */ 243 tmp = save_arm_register[1]; 244 asm volatile ("mcr p15, 0, %0, c15, c0, 1" 245 : : "r" (tmp) 246 : "cc"); 247 } 248 249 /* For release retention */ 250 251 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 252 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); 253 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); 254 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); 255 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); 256 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); 257 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); 258 259 if (soc_is_exynos5250()) 260 s3c_pm_do_restore(exynos5_sys_save, 261 ARRAY_SIZE(exynos5_sys_save)); 262 263 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); 264 265 if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250()) 266 scu_enable(S5P_VA_SCU); 267 268 early_wakeup: 269 270 /* Clear SLEEP mode set in INFORM1 */ 271 __raw_writel(0x0, S5P_INFORM1); 272 273 return; 274 } 275 276 static struct syscore_ops exynos_pm_syscore_ops = { 277 .suspend = exynos_pm_suspend, 278 .resume = exynos_pm_resume, 279 }; 280 281 /* 282 * Suspend Ops 283 */ 284 285 static int exynos_suspend_enter(suspend_state_t state) 286 { 287 int ret; 288 289 s3c_pm_debug_init(); 290 291 S3C_PMDBG("%s: suspending the system...\n", __func__); 292 293 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, 294 exynos_irqwake_intmask, exynos_get_eint_wake_mask()); 295 296 if (exynos_irqwake_intmask == -1U 297 && exynos_get_eint_wake_mask() == -1U) { 298 pr_err("%s: No wake-up sources!\n", __func__); 299 pr_err("%s: Aborting sleep\n", __func__); 300 return -EINVAL; 301 } 302 303 s3c_pm_save_uarts(); 304 exynos_pm_prepare(); 305 flush_cache_all(); 306 s3c_pm_check_store(); 307 308 ret = cpu_suspend(0, exynos_cpu_suspend); 309 if (ret) 310 return ret; 311 312 s3c_pm_restore_uarts(); 313 314 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, 315 __raw_readl(S5P_WAKEUP_STAT)); 316 317 s3c_pm_check_restore(); 318 319 S3C_PMDBG("%s: resuming the system...\n", __func__); 320 321 return 0; 322 } 323 324 static int exynos_suspend_prepare(void) 325 { 326 s3c_pm_check_prepare(); 327 328 return 0; 329 } 330 331 static void exynos_suspend_finish(void) 332 { 333 s3c_pm_check_cleanup(); 334 } 335 336 static const struct platform_suspend_ops exynos_suspend_ops = { 337 .enter = exynos_suspend_enter, 338 .prepare = exynos_suspend_prepare, 339 .finish = exynos_suspend_finish, 340 .valid = suspend_valid_only_mem, 341 }; 342 343 void __init exynos_pm_init(void) 344 { 345 u32 tmp; 346 347 /* Platform-specific GIC callback */ 348 gic_arch_extn.irq_set_wake = exynos_irq_set_wake; 349 350 /* All wakeup disable */ 351 tmp = __raw_readl(S5P_WAKEUP_MASK); 352 tmp |= ((0xFF << 8) | (0x1F << 1)); 353 __raw_writel(tmp, S5P_WAKEUP_MASK); 354 355 register_syscore_ops(&exynos_pm_syscore_ops); 356 suspend_set_ops(&exynos_suspend_ops); 357 } 358