1 /* 2 * Copyright (C) 2012 Samsung Electronics. 3 * Kyungmin Park <kyungmin.park@samsung.com> 4 * Tomasz Figa <t.figa@samsung.com> 5 * 6 * This program is free software,you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/io.h> 13 #include <linux/init.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 17 #include <asm/cacheflush.h> 18 #include <asm/cputype.h> 19 #include <asm/firmware.h> 20 #include <asm/hardware/cache-l2x0.h> 21 #include <asm/suspend.h> 22 23 #include <mach/map.h> 24 25 #include "common.h" 26 #include "smc.h" 27 28 #define EXYNOS_SLEEP_MAGIC 0x00000bad 29 #define EXYNOS_AFTR_MAGIC 0xfcba0d10 30 #define EXYNOS_BOOT_ADDR 0x8 31 #define EXYNOS_BOOT_FLAG 0xc 32 33 static void exynos_save_cp15(void) 34 { 35 /* Save Power control and Diagnostic registers */ 36 asm ("mrc p15, 0, %0, c15, c0, 0\n" 37 "mrc p15, 0, %1, c15, c0, 1\n" 38 : "=r" (cp15_save_power), "=r" (cp15_save_diag) 39 : : "cc"); 40 } 41 42 static int exynos_do_idle(unsigned long mode) 43 { 44 switch (mode) { 45 case FW_DO_IDLE_AFTR: 46 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 47 exynos_save_cp15(); 48 __raw_writel(virt_to_phys(exynos_cpu_resume_ns), 49 sysram_ns_base_addr + 0x24); 50 __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); 51 if (soc_is_exynos3250()) { 52 flush_cache_all(); 53 exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE, 54 SMC_POWERSTATE_IDLE, 0); 55 exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER, 56 SMC_POWERSTATE_IDLE, 0); 57 } else 58 exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); 59 break; 60 case FW_DO_IDLE_SLEEP: 61 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 62 } 63 return 0; 64 } 65 66 static int exynos_cpu_boot(int cpu) 67 { 68 /* 69 * Exynos3250 doesn't need to send smc command for secondary CPU boot 70 * because Exynos3250 removes WFE in secure mode. 71 */ 72 if (soc_is_exynos3250()) 73 return 0; 74 75 /* 76 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. 77 * But, Exynos4212 has only one secondary CPU so second parameter 78 * isn't used for informing secure firmware about CPU id. 79 */ 80 if (soc_is_exynos4212()) 81 cpu = 0; 82 83 exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); 84 return 0; 85 } 86 87 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) 88 { 89 void __iomem *boot_reg; 90 91 if (!sysram_ns_base_addr) 92 return -ENODEV; 93 94 boot_reg = sysram_ns_base_addr + 0x1c; 95 96 /* 97 * Almost all Exynos-series of SoCs that run in secure mode don't need 98 * additional offset for every CPU, with Exynos4412 being the only 99 * exception. 100 */ 101 if (soc_is_exynos4412()) 102 boot_reg += 4 * cpu; 103 104 __raw_writel(boot_addr, boot_reg); 105 return 0; 106 } 107 108 static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr) 109 { 110 void __iomem *boot_reg; 111 112 if (!sysram_ns_base_addr) 113 return -ENODEV; 114 115 boot_reg = sysram_ns_base_addr + 0x1c; 116 117 if (soc_is_exynos4412()) 118 boot_reg += 4 * cpu; 119 120 *boot_addr = __raw_readl(boot_reg); 121 return 0; 122 } 123 124 static int exynos_cpu_suspend(unsigned long arg) 125 { 126 flush_cache_all(); 127 outer_flush_all(); 128 129 exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); 130 131 pr_info("Failed to suspend the system\n"); 132 writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 133 return 1; 134 } 135 136 static int exynos_suspend(void) 137 { 138 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) 139 exynos_save_cp15(); 140 141 writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 142 writel(virt_to_phys(exynos_cpu_resume_ns), 143 sysram_ns_base_addr + EXYNOS_BOOT_ADDR); 144 145 return cpu_suspend(0, exynos_cpu_suspend); 146 } 147 148 static int exynos_resume(void) 149 { 150 writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); 151 152 return 0; 153 } 154 155 static const struct firmware_ops exynos_firmware_ops = { 156 .do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL, 157 .set_cpu_boot_addr = exynos_set_cpu_boot_addr, 158 .get_cpu_boot_addr = exynos_get_cpu_boot_addr, 159 .cpu_boot = exynos_cpu_boot, 160 .suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL, 161 .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL, 162 }; 163 164 static void exynos_l2_write_sec(unsigned long val, unsigned reg) 165 { 166 static int l2cache_enabled; 167 168 switch (reg) { 169 case L2X0_CTRL: 170 if (val & L2X0_CTRL_EN) { 171 /* 172 * Before the cache can be enabled, due to firmware 173 * design, SMC_CMD_L2X0INVALL must be called. 174 */ 175 if (!l2cache_enabled) { 176 exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); 177 l2cache_enabled = 1; 178 } 179 } else { 180 l2cache_enabled = 0; 181 } 182 exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); 183 break; 184 185 case L2X0_DEBUG_CTRL: 186 exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); 187 break; 188 189 default: 190 WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); 191 } 192 } 193 194 static void exynos_l2_configure(const struct l2x0_regs *regs) 195 { 196 exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency, 197 regs->prefetch_ctrl); 198 exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0); 199 } 200 201 void __init exynos_firmware_init(void) 202 { 203 struct device_node *nd; 204 const __be32 *addr; 205 206 nd = of_find_compatible_node(NULL, NULL, 207 "samsung,secure-firmware"); 208 if (!nd) 209 return; 210 211 addr = of_get_address(nd, 0, NULL, NULL); 212 if (!addr) { 213 pr_err("%s: No address specified.\n", __func__); 214 return; 215 } 216 217 pr_info("Running under secure firmware.\n"); 218 219 register_firmware_ops(&exynos_firmware_ops); 220 221 /* 222 * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310), 223 * running under secure firmware, require certain registers of L2 224 * cache controller to be written in secure mode. Here .write_sec 225 * callback is provided to perform necessary SMC calls. 226 */ 227 if (IS_ENABLED(CONFIG_CACHE_L2X0) && 228 read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { 229 outer_cache.write_sec = exynos_l2_write_sec; 230 outer_cache.configure = exynos_l2_configure; 231 } 232 } 233 234 #define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28) 235 #define BOOT_MODE_MASK 0x1f 236 237 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode) 238 { 239 unsigned int tmp; 240 241 tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); 242 243 if (mode & BOOT_MODE_MASK) 244 tmp &= ~BOOT_MODE_MASK; 245 246 tmp |= mode; 247 __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); 248 } 249 250 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode) 251 { 252 unsigned int tmp; 253 254 tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); 255 tmp &= ~mode; 256 __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); 257 } 258