1 /* 2 * arch/arm/mach-dove/irq.c 3 * 4 * Dove IRQ handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/gpio.h> 15 #include <linux/io.h> 16 #include <asm/mach/arch.h> 17 #include <plat/irq.h> 18 #include <asm/mach/irq.h> 19 #include <mach/pm.h> 20 #include <mach/bridge-regs.h> 21 #include <plat/orion-gpio.h> 22 #include "common.h" 23 24 static void pmu_irq_mask(struct irq_data *d) 25 { 26 int pin = irq_to_pmu(d->irq); 27 u32 u; 28 29 u = readl(PMU_INTERRUPT_MASK); 30 u &= ~(1 << (pin & 31)); 31 writel(u, PMU_INTERRUPT_MASK); 32 } 33 34 static void pmu_irq_unmask(struct irq_data *d) 35 { 36 int pin = irq_to_pmu(d->irq); 37 u32 u; 38 39 u = readl(PMU_INTERRUPT_MASK); 40 u |= 1 << (pin & 31); 41 writel(u, PMU_INTERRUPT_MASK); 42 } 43 44 static void pmu_irq_ack(struct irq_data *d) 45 { 46 int pin = irq_to_pmu(d->irq); 47 u32 u; 48 49 u = ~(1 << (pin & 31)); 50 writel(u, PMU_INTERRUPT_CAUSE); 51 } 52 53 static struct irq_chip pmu_irq_chip = { 54 .name = "pmu_irq", 55 .irq_mask = pmu_irq_mask, 56 .irq_unmask = pmu_irq_unmask, 57 .irq_ack = pmu_irq_ack, 58 }; 59 60 static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) 61 { 62 unsigned long cause = readl(PMU_INTERRUPT_CAUSE); 63 64 cause &= readl(PMU_INTERRUPT_MASK); 65 if (cause == 0) { 66 do_bad_IRQ(irq, desc); 67 return; 68 } 69 70 for (irq = 0; irq < NR_PMU_IRQS; irq++) { 71 if (!(cause & (1 << irq))) 72 continue; 73 irq = pmu_to_irq(irq); 74 generic_handle_irq(irq); 75 } 76 } 77 78 static int __initdata gpio0_irqs[4] = { 79 IRQ_DOVE_GPIO_0_7, 80 IRQ_DOVE_GPIO_8_15, 81 IRQ_DOVE_GPIO_16_23, 82 IRQ_DOVE_GPIO_24_31, 83 }; 84 85 static int __initdata gpio1_irqs[4] = { 86 IRQ_DOVE_HIGH_GPIO, 87 0, 88 0, 89 0, 90 }; 91 92 static int __initdata gpio2_irqs[4] = { 93 0, 94 0, 95 0, 96 0, 97 }; 98 99 void __init dove_init_irq(void) 100 { 101 int i; 102 103 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); 104 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); 105 106 /* 107 * Initialize gpiolib for GPIOs 0-71. 108 */ 109 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, 110 IRQ_DOVE_GPIO_START, gpio0_irqs); 111 112 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, 113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs); 114 115 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, 116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs); 117 118 /* 119 * Mask and clear PMU interrupts 120 */ 121 writel(0, PMU_INTERRUPT_MASK); 122 writel(0, PMU_INTERRUPT_CAUSE); 123 124 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { 125 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); 126 irq_set_status_flags(i, IRQ_LEVEL); 127 set_irq_flags(i, IRQF_VALID); 128 } 129 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); 130 } 131