1 /* 2 * arch/arm/mach-dove/common.c 3 * 4 * Core functions for Marvell Dove 88AP510 System On Chip 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/platform_data/dma-mv_xor.h> 18 #include <linux/platform_data/usb-ehci-orion.h> 19 #include <linux/platform_device.h> 20 #include <linux/soc/dove/pmu.h> 21 #include <asm/hardware/cache-tauros2.h> 22 #include <asm/mach/arch.h> 23 #include <asm/mach/map.h> 24 #include <asm/mach/time.h> 25 #include <plat/common.h> 26 #include <plat/irq.h> 27 #include <plat/time.h> 28 #include "bridge-regs.h" 29 #include "pm.h" 30 #include "common.h" 31 32 /* These can go away once Dove uses the mvebu-mbus DT binding */ 33 #define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 34 #define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 35 #define DOVE_MBUS_PCIE0_IO_TARGET 0x4 36 #define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 37 #define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 38 #define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 39 #define DOVE_MBUS_PCIE1_IO_TARGET 0x8 40 #define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 41 #define DOVE_MBUS_CESA_TARGET 0x3 42 #define DOVE_MBUS_CESA_ATTR 0x1 43 #define DOVE_MBUS_BOOTROM_TARGET 0x1 44 #define DOVE_MBUS_BOOTROM_ATTR 0xfd 45 #define DOVE_MBUS_SCRATCHPAD_TARGET 0xd 46 #define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 47 48 /***************************************************************************** 49 * I/O Address Mapping 50 ****************************************************************************/ 51 static struct map_desc __maybe_unused dove_io_desc[] __initdata = { 52 { 53 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, 54 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 55 .length = DOVE_SB_REGS_SIZE, 56 .type = MT_DEVICE, 57 }, { 58 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, 59 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 60 .length = DOVE_NB_REGS_SIZE, 61 .type = MT_DEVICE, 62 }, 63 }; 64 65 void __init dove_map_io(void) 66 { 67 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); 68 } 69 70 /***************************************************************************** 71 * CLK tree 72 ****************************************************************************/ 73 static int dove_tclk; 74 75 static DEFINE_SPINLOCK(gating_lock); 76 static struct clk *tclk; 77 78 static struct clk __init *dove_register_gate(const char *name, 79 const char *parent, u8 bit_idx) 80 { 81 return clk_register_gate(NULL, name, parent, 0, 82 (void __iomem *)CLOCK_GATING_CONTROL, 83 bit_idx, 0, &gating_lock); 84 } 85 86 static void __init dove_clk_init(void) 87 { 88 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; 89 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; 90 struct clk *xor0, *xor1, *ge, *gephy; 91 92 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); 93 94 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); 95 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); 96 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); 97 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); 98 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); 99 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); 100 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); 101 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); 102 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); 103 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); 104 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); 105 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); 106 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); 107 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); 108 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); 109 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); 110 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); 111 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); 112 113 orion_clkdev_add(NULL, "orion_spi.0", tclk); 114 orion_clkdev_add(NULL, "orion_spi.1", tclk); 115 orion_clkdev_add(NULL, "orion_wdt", tclk); 116 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); 117 118 orion_clkdev_add(NULL, "orion-ehci.0", usb0); 119 orion_clkdev_add(NULL, "orion-ehci.1", usb1); 120 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); 121 orion_clkdev_add(NULL, "sata_mv.0", sata); 122 orion_clkdev_add("0", "pcie", pex0); 123 orion_clkdev_add("1", "pcie", pex1); 124 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); 125 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); 126 orion_clkdev_add(NULL, "orion_nand", nand); 127 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); 128 orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); 129 orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); 130 orion_clkdev_add(NULL, "mv_crypto", crypto); 131 orion_clkdev_add(NULL, "dove-ac97", ac97); 132 orion_clkdev_add(NULL, "dove-pdma", pdma); 133 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); 134 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); 135 } 136 137 /***************************************************************************** 138 * EHCI0 139 ****************************************************************************/ 140 void __init dove_ehci0_init(void) 141 { 142 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 143 } 144 145 /***************************************************************************** 146 * EHCI1 147 ****************************************************************************/ 148 void __init dove_ehci1_init(void) 149 { 150 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 151 } 152 153 /***************************************************************************** 154 * GE00 155 ****************************************************************************/ 156 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 157 { 158 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 159 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, 160 1600); 161 } 162 163 /***************************************************************************** 164 * SoC RTC 165 ****************************************************************************/ 166 static void __init dove_rtc_init(void) 167 { 168 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); 169 } 170 171 /***************************************************************************** 172 * SATA 173 ****************************************************************************/ 174 void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 175 { 176 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 177 178 } 179 180 /***************************************************************************** 181 * UART0 182 ****************************************************************************/ 183 void __init dove_uart0_init(void) 184 { 185 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, 186 IRQ_DOVE_UART_0, tclk); 187 } 188 189 /***************************************************************************** 190 * UART1 191 ****************************************************************************/ 192 void __init dove_uart1_init(void) 193 { 194 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, 195 IRQ_DOVE_UART_1, tclk); 196 } 197 198 /***************************************************************************** 199 * UART2 200 ****************************************************************************/ 201 void __init dove_uart2_init(void) 202 { 203 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, 204 IRQ_DOVE_UART_2, tclk); 205 } 206 207 /***************************************************************************** 208 * UART3 209 ****************************************************************************/ 210 void __init dove_uart3_init(void) 211 { 212 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, 213 IRQ_DOVE_UART_3, tclk); 214 } 215 216 /***************************************************************************** 217 * SPI 218 ****************************************************************************/ 219 void __init dove_spi0_init(void) 220 { 221 orion_spi_init(DOVE_SPI0_PHYS_BASE); 222 } 223 224 void __init dove_spi1_init(void) 225 { 226 orion_spi_1_init(DOVE_SPI1_PHYS_BASE); 227 } 228 229 /***************************************************************************** 230 * I2C 231 ****************************************************************************/ 232 void __init dove_i2c_init(void) 233 { 234 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); 235 } 236 237 /***************************************************************************** 238 * Time handling 239 ****************************************************************************/ 240 void __init dove_init_early(void) 241 { 242 orion_time_set_base(TIMER_VIRT_BASE); 243 mvebu_mbus_init("marvell,dove-mbus", 244 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, 245 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); 246 } 247 248 static int __init dove_find_tclk(void) 249 { 250 return 166666667; 251 } 252 253 void __init dove_timer_init(void) 254 { 255 dove_tclk = dove_find_tclk(); 256 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 257 IRQ_DOVE_BRIDGE, dove_tclk); 258 } 259 260 /***************************************************************************** 261 * XOR 0 262 ****************************************************************************/ 263 static void __init dove_xor0_init(void) 264 { 265 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 266 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 267 } 268 269 /***************************************************************************** 270 * XOR 1 271 ****************************************************************************/ 272 static void __init dove_xor1_init(void) 273 { 274 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, 275 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); 276 } 277 278 /***************************************************************************** 279 * SDIO 280 ****************************************************************************/ 281 static u64 sdio_dmamask = DMA_BIT_MASK(32); 282 283 static struct resource dove_sdio0_resources[] = { 284 { 285 .start = DOVE_SDIO0_PHYS_BASE, 286 .end = DOVE_SDIO0_PHYS_BASE + 0xff, 287 .flags = IORESOURCE_MEM, 288 }, { 289 .start = IRQ_DOVE_SDIO0, 290 .end = IRQ_DOVE_SDIO0, 291 .flags = IORESOURCE_IRQ, 292 }, 293 }; 294 295 static struct platform_device dove_sdio0 = { 296 .name = "sdhci-dove", 297 .id = 0, 298 .dev = { 299 .dma_mask = &sdio_dmamask, 300 .coherent_dma_mask = DMA_BIT_MASK(32), 301 }, 302 .resource = dove_sdio0_resources, 303 .num_resources = ARRAY_SIZE(dove_sdio0_resources), 304 }; 305 306 void __init dove_sdio0_init(void) 307 { 308 platform_device_register(&dove_sdio0); 309 } 310 311 static struct resource dove_sdio1_resources[] = { 312 { 313 .start = DOVE_SDIO1_PHYS_BASE, 314 .end = DOVE_SDIO1_PHYS_BASE + 0xff, 315 .flags = IORESOURCE_MEM, 316 }, { 317 .start = IRQ_DOVE_SDIO1, 318 .end = IRQ_DOVE_SDIO1, 319 .flags = IORESOURCE_IRQ, 320 }, 321 }; 322 323 static struct platform_device dove_sdio1 = { 324 .name = "sdhci-dove", 325 .id = 1, 326 .dev = { 327 .dma_mask = &sdio_dmamask, 328 .coherent_dma_mask = DMA_BIT_MASK(32), 329 }, 330 .resource = dove_sdio1_resources, 331 .num_resources = ARRAY_SIZE(dove_sdio1_resources), 332 }; 333 334 void __init dove_sdio1_init(void) 335 { 336 platform_device_register(&dove_sdio1); 337 } 338 339 void __init dove_setup_cpu_wins(void) 340 { 341 /* 342 * The PCIe windows will no longer be statically allocated 343 * here once Dove is migrated to the pci-mvebu driver. The 344 * non-PCIe windows will no longer be created here once Dove 345 * fully moves to DT. 346 */ 347 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, 348 DOVE_MBUS_PCIE0_IO_ATTR, 349 DOVE_PCIE0_IO_PHYS_BASE, 350 DOVE_PCIE0_IO_SIZE, 351 DOVE_PCIE0_IO_BUS_BASE); 352 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, 353 DOVE_MBUS_PCIE1_IO_ATTR, 354 DOVE_PCIE1_IO_PHYS_BASE, 355 DOVE_PCIE1_IO_SIZE, 356 DOVE_PCIE1_IO_BUS_BASE); 357 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, 358 DOVE_MBUS_PCIE0_MEM_ATTR, 359 DOVE_PCIE0_MEM_PHYS_BASE, 360 DOVE_PCIE0_MEM_SIZE); 361 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, 362 DOVE_MBUS_PCIE1_MEM_ATTR, 363 DOVE_PCIE1_MEM_PHYS_BASE, 364 DOVE_PCIE1_MEM_SIZE); 365 mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, 366 DOVE_MBUS_CESA_ATTR, 367 DOVE_CESA_PHYS_BASE, 368 DOVE_CESA_SIZE); 369 mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, 370 DOVE_MBUS_BOOTROM_ATTR, 371 DOVE_BOOTROM_PHYS_BASE, 372 DOVE_BOOTROM_SIZE); 373 mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, 374 DOVE_MBUS_SCRATCHPAD_ATTR, 375 DOVE_SCRATCHPAD_PHYS_BASE, 376 DOVE_SCRATCHPAD_SIZE); 377 } 378 379 static struct resource orion_wdt_resource[] = { 380 DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), 381 DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), 382 }; 383 384 static struct platform_device orion_wdt_device = { 385 .name = "orion_wdt", 386 .id = -1, 387 .num_resources = ARRAY_SIZE(orion_wdt_resource), 388 .resource = orion_wdt_resource, 389 }; 390 391 static void __init __maybe_unused orion_wdt_init(void) 392 { 393 platform_device_register(&orion_wdt_device); 394 } 395 396 static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = { 397 { 398 .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK, 399 .rst_mask = PMU_SW_RST_VIDEO_MASK, 400 .iso_mask = PMU_ISO_VIDEO_MASK, 401 .name = "vpu-domain", 402 }, { 403 .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, 404 .rst_mask = PMU_SW_RST_GPU_MASK, 405 .iso_mask = PMU_ISO_GPU_MASK, 406 .name = "gpu-domain", 407 }, { 408 /* sentinel */ 409 }, 410 }; 411 412 static const struct dove_pmu_initdata pmu_data __initconst = { 413 .pmc_base = DOVE_PMU_VIRT_BASE, 414 .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000, 415 .irq = IRQ_DOVE_PMU, 416 .irq_domain_start = IRQ_DOVE_PMU_START, 417 .domains = pmu_domains, 418 }; 419 420 void __init dove_init(void) 421 { 422 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 423 (dove_tclk + 499999) / 1000000); 424 425 #ifdef CONFIG_CACHE_TAUROS2 426 tauros2_init(0); 427 #endif 428 dove_setup_cpu_wins(); 429 430 /* Setup root of clk tree */ 431 dove_clk_init(); 432 433 /* internal devices that every board has */ 434 dove_init_pmu_legacy(&pmu_data); 435 dove_rtc_init(); 436 dove_xor0_init(); 437 dove_xor1_init(); 438 } 439 440 void dove_restart(enum reboot_mode mode, const char *cmd) 441 { 442 /* 443 * Enable soft reset to assert RSTOUTn. 444 */ 445 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 446 447 /* 448 * Assert soft reset. 449 */ 450 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 451 452 while (1) 453 ; 454 } 455