1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/serial_8250.h> 17 #include <linux/ahci_platform.h> 18 #include <linux/clk.h> 19 20 #include <mach/cputype.h> 21 #include <mach/common.h> 22 #include <mach/time.h> 23 #include <mach/da8xx.h> 24 #include <mach/cpuidle.h> 25 26 #include "clock.h" 27 28 #define DA8XX_TPCC_BASE 0x01c00000 29 #define DA8XX_TPTC0_BASE 0x01c08000 30 #define DA8XX_TPTC1_BASE 0x01c08400 31 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 32 #define DA8XX_I2C0_BASE 0x01c22000 33 #define DA8XX_RTC_BASE 0x01c23000 34 #define DA8XX_MMCSD0_BASE 0x01c40000 35 #define DA8XX_SPI0_BASE 0x01c41000 36 #define DA830_SPI1_BASE 0x01e12000 37 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 38 #define DA850_SATA_BASE 0x01e18000 39 #define DA850_MMCSD1_BASE 0x01e1b000 40 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 41 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 42 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 43 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 44 #define DA8XX_I2C1_BASE 0x01e28000 45 #define DA850_TPCC1_BASE 0x01e30000 46 #define DA850_TPTC2_BASE 0x01e38000 47 #define DA850_SPI1_BASE 0x01f0e000 48 #define DA8XX_DDR2_CTL_BASE 0xb0000000 49 50 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 51 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 52 #define DA8XX_EMAC_RAM_OFFSET 0x0000 53 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 54 55 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14) 56 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15) 57 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16) 58 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17) 59 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18) 60 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19) 61 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28) 62 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29) 63 64 void __iomem *da8xx_syscfg0_base; 65 void __iomem *da8xx_syscfg1_base; 66 67 static struct plat_serial8250_port da8xx_serial_pdata[] = { 68 { 69 .mapbase = DA8XX_UART0_BASE, 70 .irq = IRQ_DA8XX_UARTINT0, 71 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 72 UPF_IOREMAP, 73 .iotype = UPIO_MEM, 74 .regshift = 2, 75 }, 76 { 77 .mapbase = DA8XX_UART1_BASE, 78 .irq = IRQ_DA8XX_UARTINT1, 79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 80 UPF_IOREMAP, 81 .iotype = UPIO_MEM, 82 .regshift = 2, 83 }, 84 { 85 .mapbase = DA8XX_UART2_BASE, 86 .irq = IRQ_DA8XX_UARTINT2, 87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 88 UPF_IOREMAP, 89 .iotype = UPIO_MEM, 90 .regshift = 2, 91 }, 92 { 93 .flags = 0, 94 }, 95 }; 96 97 struct platform_device da8xx_serial_device = { 98 .name = "serial8250", 99 .id = PLAT8250_DEV_PLATFORM, 100 .dev = { 101 .platform_data = da8xx_serial_pdata, 102 }, 103 }; 104 105 static const s8 da8xx_queue_tc_mapping[][2] = { 106 /* {event queue no, TC no} */ 107 {0, 0}, 108 {1, 1}, 109 {-1, -1} 110 }; 111 112 static const s8 da8xx_queue_priority_mapping[][2] = { 113 /* {event queue no, Priority} */ 114 {0, 3}, 115 {1, 7}, 116 {-1, -1} 117 }; 118 119 static const s8 da850_queue_tc_mapping[][2] = { 120 /* {event queue no, TC no} */ 121 {0, 0}, 122 {-1, -1} 123 }; 124 125 static const s8 da850_queue_priority_mapping[][2] = { 126 /* {event queue no, Priority} */ 127 {0, 3}, 128 {-1, -1} 129 }; 130 131 static struct edma_soc_info da830_edma_cc0_info = { 132 .n_channel = 32, 133 .n_region = 4, 134 .n_slot = 128, 135 .n_tc = 2, 136 .n_cc = 1, 137 .queue_tc_mapping = da8xx_queue_tc_mapping, 138 .queue_priority_mapping = da8xx_queue_priority_mapping, 139 .default_queue = EVENTQ_1, 140 }; 141 142 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { 143 &da830_edma_cc0_info, 144 }; 145 146 static struct edma_soc_info da850_edma_cc_info[] = { 147 { 148 .n_channel = 32, 149 .n_region = 4, 150 .n_slot = 128, 151 .n_tc = 2, 152 .n_cc = 1, 153 .queue_tc_mapping = da8xx_queue_tc_mapping, 154 .queue_priority_mapping = da8xx_queue_priority_mapping, 155 .default_queue = EVENTQ_1, 156 }, 157 { 158 .n_channel = 32, 159 .n_region = 4, 160 .n_slot = 128, 161 .n_tc = 1, 162 .n_cc = 1, 163 .queue_tc_mapping = da850_queue_tc_mapping, 164 .queue_priority_mapping = da850_queue_priority_mapping, 165 .default_queue = EVENTQ_0, 166 }, 167 }; 168 169 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { 170 &da850_edma_cc_info[0], 171 &da850_edma_cc_info[1], 172 }; 173 174 static struct resource da830_edma_resources[] = { 175 { 176 .name = "edma_cc0", 177 .start = DA8XX_TPCC_BASE, 178 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 179 .flags = IORESOURCE_MEM, 180 }, 181 { 182 .name = "edma_tc0", 183 .start = DA8XX_TPTC0_BASE, 184 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 185 .flags = IORESOURCE_MEM, 186 }, 187 { 188 .name = "edma_tc1", 189 .start = DA8XX_TPTC1_BASE, 190 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 191 .flags = IORESOURCE_MEM, 192 }, 193 { 194 .name = "edma0", 195 .start = IRQ_DA8XX_CCINT0, 196 .flags = IORESOURCE_IRQ, 197 }, 198 { 199 .name = "edma0_err", 200 .start = IRQ_DA8XX_CCERRINT, 201 .flags = IORESOURCE_IRQ, 202 }, 203 }; 204 205 static struct resource da850_edma_resources[] = { 206 { 207 .name = "edma_cc0", 208 .start = DA8XX_TPCC_BASE, 209 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 210 .flags = IORESOURCE_MEM, 211 }, 212 { 213 .name = "edma_tc0", 214 .start = DA8XX_TPTC0_BASE, 215 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 216 .flags = IORESOURCE_MEM, 217 }, 218 { 219 .name = "edma_tc1", 220 .start = DA8XX_TPTC1_BASE, 221 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 222 .flags = IORESOURCE_MEM, 223 }, 224 { 225 .name = "edma_cc1", 226 .start = DA850_TPCC1_BASE, 227 .end = DA850_TPCC1_BASE + SZ_32K - 1, 228 .flags = IORESOURCE_MEM, 229 }, 230 { 231 .name = "edma_tc2", 232 .start = DA850_TPTC2_BASE, 233 .end = DA850_TPTC2_BASE + SZ_1K - 1, 234 .flags = IORESOURCE_MEM, 235 }, 236 { 237 .name = "edma0", 238 .start = IRQ_DA8XX_CCINT0, 239 .flags = IORESOURCE_IRQ, 240 }, 241 { 242 .name = "edma0_err", 243 .start = IRQ_DA8XX_CCERRINT, 244 .flags = IORESOURCE_IRQ, 245 }, 246 { 247 .name = "edma1", 248 .start = IRQ_DA850_CCINT1, 249 .flags = IORESOURCE_IRQ, 250 }, 251 { 252 .name = "edma1_err", 253 .start = IRQ_DA850_CCERRINT1, 254 .flags = IORESOURCE_IRQ, 255 }, 256 }; 257 258 static struct platform_device da830_edma_device = { 259 .name = "edma", 260 .id = -1, 261 .dev = { 262 .platform_data = da830_edma_info, 263 }, 264 .num_resources = ARRAY_SIZE(da830_edma_resources), 265 .resource = da830_edma_resources, 266 }; 267 268 static struct platform_device da850_edma_device = { 269 .name = "edma", 270 .id = -1, 271 .dev = { 272 .platform_data = da850_edma_info, 273 }, 274 .num_resources = ARRAY_SIZE(da850_edma_resources), 275 .resource = da850_edma_resources, 276 }; 277 278 int __init da830_register_edma(struct edma_rsv_info *rsv) 279 { 280 da830_edma_cc0_info.rsv = rsv; 281 282 return platform_device_register(&da830_edma_device); 283 } 284 285 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 286 { 287 if (rsv) { 288 da850_edma_cc_info[0].rsv = rsv[0]; 289 da850_edma_cc_info[1].rsv = rsv[1]; 290 } 291 292 return platform_device_register(&da850_edma_device); 293 } 294 295 static struct resource da8xx_i2c_resources0[] = { 296 { 297 .start = DA8XX_I2C0_BASE, 298 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 299 .flags = IORESOURCE_MEM, 300 }, 301 { 302 .start = IRQ_DA8XX_I2CINT0, 303 .end = IRQ_DA8XX_I2CINT0, 304 .flags = IORESOURCE_IRQ, 305 }, 306 }; 307 308 static struct platform_device da8xx_i2c_device0 = { 309 .name = "i2c_davinci", 310 .id = 1, 311 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 312 .resource = da8xx_i2c_resources0, 313 }; 314 315 static struct resource da8xx_i2c_resources1[] = { 316 { 317 .start = DA8XX_I2C1_BASE, 318 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 319 .flags = IORESOURCE_MEM, 320 }, 321 { 322 .start = IRQ_DA8XX_I2CINT1, 323 .end = IRQ_DA8XX_I2CINT1, 324 .flags = IORESOURCE_IRQ, 325 }, 326 }; 327 328 static struct platform_device da8xx_i2c_device1 = { 329 .name = "i2c_davinci", 330 .id = 2, 331 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 332 .resource = da8xx_i2c_resources1, 333 }; 334 335 int __init da8xx_register_i2c(int instance, 336 struct davinci_i2c_platform_data *pdata) 337 { 338 struct platform_device *pdev; 339 340 if (instance == 0) 341 pdev = &da8xx_i2c_device0; 342 else if (instance == 1) 343 pdev = &da8xx_i2c_device1; 344 else 345 return -EINVAL; 346 347 pdev->dev.platform_data = pdata; 348 return platform_device_register(pdev); 349 } 350 351 static struct resource da8xx_watchdog_resources[] = { 352 { 353 .start = DA8XX_WDOG_BASE, 354 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 355 .flags = IORESOURCE_MEM, 356 }, 357 }; 358 359 struct platform_device da8xx_wdt_device = { 360 .name = "watchdog", 361 .id = -1, 362 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 363 .resource = da8xx_watchdog_resources, 364 }; 365 366 void da8xx_restart(char mode, const char *cmd) 367 { 368 davinci_watchdog_reset(&da8xx_wdt_device); 369 } 370 371 int __init da8xx_register_watchdog(void) 372 { 373 return platform_device_register(&da8xx_wdt_device); 374 } 375 376 static struct resource da8xx_emac_resources[] = { 377 { 378 .start = DA8XX_EMAC_CPPI_PORT_BASE, 379 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 380 .flags = IORESOURCE_MEM, 381 }, 382 { 383 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, 384 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, 385 .flags = IORESOURCE_IRQ, 386 }, 387 { 388 .start = IRQ_DA8XX_C0_RX_PULSE, 389 .end = IRQ_DA8XX_C0_RX_PULSE, 390 .flags = IORESOURCE_IRQ, 391 }, 392 { 393 .start = IRQ_DA8XX_C0_TX_PULSE, 394 .end = IRQ_DA8XX_C0_TX_PULSE, 395 .flags = IORESOURCE_IRQ, 396 }, 397 { 398 .start = IRQ_DA8XX_C0_MISC_PULSE, 399 .end = IRQ_DA8XX_C0_MISC_PULSE, 400 .flags = IORESOURCE_IRQ, 401 }, 402 }; 403 404 struct emac_platform_data da8xx_emac_pdata = { 405 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 406 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 407 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 408 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 409 .version = EMAC_VERSION_2, 410 }; 411 412 static struct platform_device da8xx_emac_device = { 413 .name = "davinci_emac", 414 .id = 1, 415 .dev = { 416 .platform_data = &da8xx_emac_pdata, 417 }, 418 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 419 .resource = da8xx_emac_resources, 420 }; 421 422 static struct resource da8xx_mdio_resources[] = { 423 { 424 .start = DA8XX_EMAC_MDIO_BASE, 425 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 426 .flags = IORESOURCE_MEM, 427 }, 428 }; 429 430 static struct platform_device da8xx_mdio_device = { 431 .name = "davinci_mdio", 432 .id = 0, 433 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 434 .resource = da8xx_mdio_resources, 435 }; 436 437 int __init da8xx_register_emac(void) 438 { 439 int ret; 440 441 ret = platform_device_register(&da8xx_mdio_device); 442 if (ret < 0) 443 return ret; 444 ret = platform_device_register(&da8xx_emac_device); 445 if (ret < 0) 446 return ret; 447 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), 448 NULL, &da8xx_emac_device.dev); 449 return ret; 450 } 451 452 static struct resource da830_mcasp1_resources[] = { 453 { 454 .name = "mcasp1", 455 .start = DAVINCI_DA830_MCASP1_REG_BASE, 456 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 457 .flags = IORESOURCE_MEM, 458 }, 459 /* TX event */ 460 { 461 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 462 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 463 .flags = IORESOURCE_DMA, 464 }, 465 /* RX event */ 466 { 467 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 468 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 469 .flags = IORESOURCE_DMA, 470 }, 471 }; 472 473 static struct platform_device da830_mcasp1_device = { 474 .name = "davinci-mcasp", 475 .id = 1, 476 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 477 .resource = da830_mcasp1_resources, 478 }; 479 480 static struct resource da850_mcasp_resources[] = { 481 { 482 .name = "mcasp", 483 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 484 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 485 .flags = IORESOURCE_MEM, 486 }, 487 /* TX event */ 488 { 489 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 490 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 491 .flags = IORESOURCE_DMA, 492 }, 493 /* RX event */ 494 { 495 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 496 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 497 .flags = IORESOURCE_DMA, 498 }, 499 }; 500 501 static struct platform_device da850_mcasp_device = { 502 .name = "davinci-mcasp", 503 .id = 0, 504 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 505 .resource = da850_mcasp_resources, 506 }; 507 508 static struct platform_device davinci_pcm_device = { 509 .name = "davinci-pcm-audio", 510 .id = -1, 511 }; 512 513 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 514 { 515 platform_device_register(&davinci_pcm_device); 516 517 /* DA830/OMAP-L137 has 3 instances of McASP */ 518 if (cpu_is_davinci_da830() && id == 1) { 519 da830_mcasp1_device.dev.platform_data = pdata; 520 platform_device_register(&da830_mcasp1_device); 521 } else if (cpu_is_davinci_da850()) { 522 da850_mcasp_device.dev.platform_data = pdata; 523 platform_device_register(&da850_mcasp_device); 524 } 525 } 526 527 static const struct display_panel disp_panel = { 528 QVGA, 529 16, 530 16, 531 COLOR_ACTIVE, 532 }; 533 534 static struct lcd_ctrl_config lcd_cfg = { 535 &disp_panel, 536 .ac_bias = 255, 537 .ac_bias_intrpt = 0, 538 .dma_burst_sz = 16, 539 .bpp = 16, 540 .fdd = 255, 541 .tft_alt_mode = 0, 542 .stn_565_mode = 0, 543 .mono_8bit_mode = 0, 544 .invert_line_clock = 1, 545 .invert_frm_clock = 1, 546 .sync_edge = 0, 547 .sync_ctrl = 1, 548 .raster_order = 0, 549 }; 550 551 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 552 .manu_name = "sharp", 553 .controller_data = &lcd_cfg, 554 .type = "Sharp_LCD035Q3DG01", 555 }; 556 557 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 558 .manu_name = "sharp", 559 .controller_data = &lcd_cfg, 560 .type = "Sharp_LK043T1DG01", 561 }; 562 563 static struct resource da8xx_lcdc_resources[] = { 564 [0] = { /* registers */ 565 .start = DA8XX_LCD_CNTRL_BASE, 566 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 567 .flags = IORESOURCE_MEM, 568 }, 569 [1] = { /* interrupt */ 570 .start = IRQ_DA8XX_LCDINT, 571 .end = IRQ_DA8XX_LCDINT, 572 .flags = IORESOURCE_IRQ, 573 }, 574 }; 575 576 static struct platform_device da8xx_lcdc_device = { 577 .name = "da8xx_lcdc", 578 .id = 0, 579 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 580 .resource = da8xx_lcdc_resources, 581 }; 582 583 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 584 { 585 da8xx_lcdc_device.dev.platform_data = pdata; 586 return platform_device_register(&da8xx_lcdc_device); 587 } 588 589 static struct resource da8xx_mmcsd0_resources[] = { 590 { /* registers */ 591 .start = DA8XX_MMCSD0_BASE, 592 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 593 .flags = IORESOURCE_MEM, 594 }, 595 { /* interrupt */ 596 .start = IRQ_DA8XX_MMCSDINT0, 597 .end = IRQ_DA8XX_MMCSDINT0, 598 .flags = IORESOURCE_IRQ, 599 }, 600 { /* DMA RX */ 601 .start = DA8XX_DMA_MMCSD0_RX, 602 .end = DA8XX_DMA_MMCSD0_RX, 603 .flags = IORESOURCE_DMA, 604 }, 605 { /* DMA TX */ 606 .start = DA8XX_DMA_MMCSD0_TX, 607 .end = DA8XX_DMA_MMCSD0_TX, 608 .flags = IORESOURCE_DMA, 609 }, 610 }; 611 612 static struct platform_device da8xx_mmcsd0_device = { 613 .name = "davinci_mmc", 614 .id = 0, 615 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 616 .resource = da8xx_mmcsd0_resources, 617 }; 618 619 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 620 { 621 da8xx_mmcsd0_device.dev.platform_data = config; 622 return platform_device_register(&da8xx_mmcsd0_device); 623 } 624 625 #ifdef CONFIG_ARCH_DAVINCI_DA850 626 static struct resource da850_mmcsd1_resources[] = { 627 { /* registers */ 628 .start = DA850_MMCSD1_BASE, 629 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 630 .flags = IORESOURCE_MEM, 631 }, 632 { /* interrupt */ 633 .start = IRQ_DA850_MMCSDINT0_1, 634 .end = IRQ_DA850_MMCSDINT0_1, 635 .flags = IORESOURCE_IRQ, 636 }, 637 { /* DMA RX */ 638 .start = DA850_DMA_MMCSD1_RX, 639 .end = DA850_DMA_MMCSD1_RX, 640 .flags = IORESOURCE_DMA, 641 }, 642 { /* DMA TX */ 643 .start = DA850_DMA_MMCSD1_TX, 644 .end = DA850_DMA_MMCSD1_TX, 645 .flags = IORESOURCE_DMA, 646 }, 647 }; 648 649 static struct platform_device da850_mmcsd1_device = { 650 .name = "davinci_mmc", 651 .id = 1, 652 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 653 .resource = da850_mmcsd1_resources, 654 }; 655 656 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 657 { 658 da850_mmcsd1_device.dev.platform_data = config; 659 return platform_device_register(&da850_mmcsd1_device); 660 } 661 #endif 662 663 static struct resource da8xx_rtc_resources[] = { 664 { 665 .start = DA8XX_RTC_BASE, 666 .end = DA8XX_RTC_BASE + SZ_4K - 1, 667 .flags = IORESOURCE_MEM, 668 }, 669 { /* timer irq */ 670 .start = IRQ_DA8XX_RTC, 671 .end = IRQ_DA8XX_RTC, 672 .flags = IORESOURCE_IRQ, 673 }, 674 { /* alarm irq */ 675 .start = IRQ_DA8XX_RTC, 676 .end = IRQ_DA8XX_RTC, 677 .flags = IORESOURCE_IRQ, 678 }, 679 }; 680 681 static struct platform_device da8xx_rtc_device = { 682 .name = "omap_rtc", 683 .id = -1, 684 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 685 .resource = da8xx_rtc_resources, 686 }; 687 688 int da8xx_register_rtc(void) 689 { 690 int ret; 691 void __iomem *base; 692 693 base = ioremap(DA8XX_RTC_BASE, SZ_4K); 694 if (WARN_ON(!base)) 695 return -ENOMEM; 696 697 /* Unlock the rtc's registers */ 698 __raw_writel(0x83e70b13, base + 0x6c); 699 __raw_writel(0x95a4f1e0, base + 0x70); 700 701 iounmap(base); 702 703 ret = platform_device_register(&da8xx_rtc_device); 704 if (!ret) 705 /* Atleast on DA850, RTC is a wakeup source */ 706 device_init_wakeup(&da8xx_rtc_device.dev, true); 707 708 return ret; 709 } 710 711 static void __iomem *da8xx_ddr2_ctlr_base; 712 void __iomem * __init da8xx_get_mem_ctlr(void) 713 { 714 if (da8xx_ddr2_ctlr_base) 715 return da8xx_ddr2_ctlr_base; 716 717 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 718 if (!da8xx_ddr2_ctlr_base) 719 pr_warning("%s: Unable to map DDR2 controller", __func__); 720 721 return da8xx_ddr2_ctlr_base; 722 } 723 724 static struct resource da8xx_cpuidle_resources[] = { 725 { 726 .start = DA8XX_DDR2_CTL_BASE, 727 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 728 .flags = IORESOURCE_MEM, 729 }, 730 }; 731 732 /* DA8XX devices support DDR2 power down */ 733 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 734 .ddr2_pdown = 1, 735 }; 736 737 738 static struct platform_device da8xx_cpuidle_device = { 739 .name = "cpuidle-davinci", 740 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 741 .resource = da8xx_cpuidle_resources, 742 .dev = { 743 .platform_data = &da8xx_cpuidle_pdata, 744 }, 745 }; 746 747 int __init da8xx_register_cpuidle(void) 748 { 749 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 750 751 return platform_device_register(&da8xx_cpuidle_device); 752 } 753 754 static struct resource da8xx_spi0_resources[] = { 755 [0] = { 756 .start = DA8XX_SPI0_BASE, 757 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 758 .flags = IORESOURCE_MEM, 759 }, 760 [1] = { 761 .start = IRQ_DA8XX_SPINT0, 762 .end = IRQ_DA8XX_SPINT0, 763 .flags = IORESOURCE_IRQ, 764 }, 765 [2] = { 766 .start = DA8XX_DMA_SPI0_RX, 767 .end = DA8XX_DMA_SPI0_RX, 768 .flags = IORESOURCE_DMA, 769 }, 770 [3] = { 771 .start = DA8XX_DMA_SPI0_TX, 772 .end = DA8XX_DMA_SPI0_TX, 773 .flags = IORESOURCE_DMA, 774 }, 775 }; 776 777 static struct resource da8xx_spi1_resources[] = { 778 [0] = { 779 .start = DA830_SPI1_BASE, 780 .end = DA830_SPI1_BASE + SZ_4K - 1, 781 .flags = IORESOURCE_MEM, 782 }, 783 [1] = { 784 .start = IRQ_DA8XX_SPINT1, 785 .end = IRQ_DA8XX_SPINT1, 786 .flags = IORESOURCE_IRQ, 787 }, 788 [2] = { 789 .start = DA8XX_DMA_SPI1_RX, 790 .end = DA8XX_DMA_SPI1_RX, 791 .flags = IORESOURCE_DMA, 792 }, 793 [3] = { 794 .start = DA8XX_DMA_SPI1_TX, 795 .end = DA8XX_DMA_SPI1_TX, 796 .flags = IORESOURCE_DMA, 797 }, 798 }; 799 800 struct davinci_spi_platform_data da8xx_spi_pdata[] = { 801 [0] = { 802 .version = SPI_VERSION_2, 803 .intr_line = 1, 804 .dma_event_q = EVENTQ_0, 805 }, 806 [1] = { 807 .version = SPI_VERSION_2, 808 .intr_line = 1, 809 .dma_event_q = EVENTQ_0, 810 }, 811 }; 812 813 static struct platform_device da8xx_spi_device[] = { 814 [0] = { 815 .name = "spi_davinci", 816 .id = 0, 817 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 818 .resource = da8xx_spi0_resources, 819 .dev = { 820 .platform_data = &da8xx_spi_pdata[0], 821 }, 822 }, 823 [1] = { 824 .name = "spi_davinci", 825 .id = 1, 826 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 827 .resource = da8xx_spi1_resources, 828 .dev = { 829 .platform_data = &da8xx_spi_pdata[1], 830 }, 831 }, 832 }; 833 834 int __init da8xx_register_spi(int instance, struct spi_board_info *info, 835 unsigned len) 836 { 837 int ret; 838 839 if (instance < 0 || instance > 1) 840 return -EINVAL; 841 842 ret = spi_register_board_info(info, len); 843 if (ret) 844 pr_warning("%s: failed to register board info for spi %d :" 845 " %d\n", __func__, instance, ret); 846 847 da8xx_spi_pdata[instance].num_chipselect = len; 848 849 if (instance == 1 && cpu_is_davinci_da850()) { 850 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 851 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 852 } 853 854 return platform_device_register(&da8xx_spi_device[instance]); 855 } 856 857 #ifdef CONFIG_ARCH_DAVINCI_DA850 858 859 static struct resource da850_sata_resources[] = { 860 { 861 .start = DA850_SATA_BASE, 862 .end = DA850_SATA_BASE + 0x1fff, 863 .flags = IORESOURCE_MEM, 864 }, 865 { 866 .start = IRQ_DA850_SATAINT, 867 .flags = IORESOURCE_IRQ, 868 }, 869 }; 870 871 /* SATA PHY Control Register offset from AHCI base */ 872 #define SATA_P0PHYCR_REG 0x178 873 874 #define SATA_PHY_MPY(x) ((x) << 0) 875 #define SATA_PHY_LOS(x) ((x) << 6) 876 #define SATA_PHY_RXCDR(x) ((x) << 10) 877 #define SATA_PHY_RXEQ(x) ((x) << 13) 878 #define SATA_PHY_TXSWING(x) ((x) << 19) 879 #define SATA_PHY_ENPLL(x) ((x) << 31) 880 881 static struct clk *da850_sata_clk; 882 static unsigned long da850_sata_refclkpn; 883 884 /* Supported DA850 SATA crystal frequencies */ 885 #define KHZ_TO_HZ(freq) ((freq) * 1000) 886 static unsigned long da850_sata_xtal[] = { 887 KHZ_TO_HZ(300000), 888 KHZ_TO_HZ(250000), 889 0, /* Reserved */ 890 KHZ_TO_HZ(187500), 891 KHZ_TO_HZ(150000), 892 KHZ_TO_HZ(125000), 893 KHZ_TO_HZ(120000), 894 KHZ_TO_HZ(100000), 895 KHZ_TO_HZ(75000), 896 KHZ_TO_HZ(60000), 897 }; 898 899 static int da850_sata_init(struct device *dev, void __iomem *addr) 900 { 901 int i, ret; 902 unsigned int val; 903 904 da850_sata_clk = clk_get(dev, NULL); 905 if (IS_ERR(da850_sata_clk)) 906 return PTR_ERR(da850_sata_clk); 907 908 ret = clk_enable(da850_sata_clk); 909 if (ret) 910 goto err0; 911 912 /* Enable SATA clock receiver */ 913 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); 914 val &= ~BIT(0); 915 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); 916 917 /* Get the multiplier needed for 1.5GHz PLL output */ 918 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++) 919 if (da850_sata_xtal[i] == da850_sata_refclkpn) 920 break; 921 922 if (i == ARRAY_SIZE(da850_sata_xtal)) { 923 ret = -EINVAL; 924 goto err1; 925 } 926 927 val = SATA_PHY_MPY(i + 1) | 928 SATA_PHY_LOS(1) | 929 SATA_PHY_RXCDR(4) | 930 SATA_PHY_RXEQ(1) | 931 SATA_PHY_TXSWING(3) | 932 SATA_PHY_ENPLL(1); 933 934 __raw_writel(val, addr + SATA_P0PHYCR_REG); 935 936 return 0; 937 938 err1: 939 clk_disable(da850_sata_clk); 940 err0: 941 clk_put(da850_sata_clk); 942 return ret; 943 } 944 945 static void da850_sata_exit(struct device *dev) 946 { 947 clk_disable(da850_sata_clk); 948 clk_put(da850_sata_clk); 949 } 950 951 static struct ahci_platform_data da850_sata_pdata = { 952 .init = da850_sata_init, 953 .exit = da850_sata_exit, 954 }; 955 956 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 957 958 static struct platform_device da850_sata_device = { 959 .name = "ahci", 960 .id = -1, 961 .dev = { 962 .platform_data = &da850_sata_pdata, 963 .dma_mask = &da850_sata_dmamask, 964 .coherent_dma_mask = DMA_BIT_MASK(32), 965 }, 966 .num_resources = ARRAY_SIZE(da850_sata_resources), 967 .resource = da850_sata_resources, 968 }; 969 970 int __init da850_register_sata(unsigned long refclkpn) 971 { 972 da850_sata_refclkpn = refclkpn; 973 if (!da850_sata_refclkpn) 974 return -EINVAL; 975 976 return platform_device_register(&da850_sata_device); 977 } 978 #endif 979