1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/ahci_platform.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/dma-contiguous.h> 18 #include <linux/dmaengine.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/reboot.h> 22 #include <linux/serial_8250.h> 23 24 #include <mach/common.h> 25 #include <mach/cputype.h> 26 #include <mach/da8xx.h> 27 #include <mach/time.h> 28 29 #include "asp.h" 30 #include "cpuidle.h" 31 #include "sram.h" 32 33 #ifndef CONFIG_COMMON_CLK 34 #include <mach/clock.h> 35 #include "clock.h" 36 #endif 37 38 #define DA8XX_TPCC_BASE 0x01c00000 39 #define DA8XX_TPTC0_BASE 0x01c08000 40 #define DA8XX_TPTC1_BASE 0x01c08400 41 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 42 #define DA8XX_I2C0_BASE 0x01c22000 43 #define DA8XX_RTC_BASE 0x01c23000 44 #define DA8XX_PRUSS_MEM_BASE 0x01c30000 45 #define DA8XX_MMCSD0_BASE 0x01c40000 46 #define DA8XX_SPI0_BASE 0x01c41000 47 #define DA830_SPI1_BASE 0x01e12000 48 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 49 #define DA850_SATA_BASE 0x01e18000 50 #define DA850_MMCSD1_BASE 0x01e1b000 51 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 52 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 53 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 54 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 55 #define DA8XX_I2C1_BASE 0x01e28000 56 #define DA850_TPCC1_BASE 0x01e30000 57 #define DA850_TPTC2_BASE 0x01e38000 58 #define DA850_SPI1_BASE 0x01f0e000 59 #define DA8XX_DDR2_CTL_BASE 0xb0000000 60 61 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 62 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 63 #define DA8XX_EMAC_RAM_OFFSET 0x0000 64 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 65 66 void __iomem *da8xx_syscfg0_base; 67 void __iomem *da8xx_syscfg1_base; 68 69 static struct plat_serial8250_port da8xx_serial0_pdata[] = { 70 { 71 .mapbase = DA8XX_UART0_BASE, 72 .irq = IRQ_DA8XX_UARTINT0, 73 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 74 UPF_IOREMAP, 75 .iotype = UPIO_MEM, 76 .regshift = 2, 77 }, 78 { 79 .flags = 0, 80 } 81 }; 82 static struct plat_serial8250_port da8xx_serial1_pdata[] = { 83 { 84 .mapbase = DA8XX_UART1_BASE, 85 .irq = IRQ_DA8XX_UARTINT1, 86 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 87 UPF_IOREMAP, 88 .iotype = UPIO_MEM, 89 .regshift = 2, 90 }, 91 { 92 .flags = 0, 93 } 94 }; 95 static struct plat_serial8250_port da8xx_serial2_pdata[] = { 96 { 97 .mapbase = DA8XX_UART2_BASE, 98 .irq = IRQ_DA8XX_UARTINT2, 99 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 100 UPF_IOREMAP, 101 .iotype = UPIO_MEM, 102 .regshift = 2, 103 }, 104 { 105 .flags = 0, 106 } 107 }; 108 109 struct platform_device da8xx_serial_device[] = { 110 { 111 .name = "serial8250", 112 .id = PLAT8250_DEV_PLATFORM, 113 .dev = { 114 .platform_data = da8xx_serial0_pdata, 115 } 116 }, 117 { 118 .name = "serial8250", 119 .id = PLAT8250_DEV_PLATFORM1, 120 .dev = { 121 .platform_data = da8xx_serial1_pdata, 122 } 123 }, 124 { 125 .name = "serial8250", 126 .id = PLAT8250_DEV_PLATFORM2, 127 .dev = { 128 .platform_data = da8xx_serial2_pdata, 129 } 130 }, 131 { 132 } 133 }; 134 135 static s8 da8xx_queue_priority_mapping[][2] = { 136 /* {event queue no, Priority} */ 137 {0, 3}, 138 {1, 7}, 139 {-1, -1} 140 }; 141 142 static s8 da850_queue_priority_mapping[][2] = { 143 /* {event queue no, Priority} */ 144 {0, 3}, 145 {-1, -1} 146 }; 147 148 static struct edma_soc_info da8xx_edma0_pdata = { 149 .queue_priority_mapping = da8xx_queue_priority_mapping, 150 .default_queue = EVENTQ_1, 151 }; 152 153 static struct edma_soc_info da850_edma1_pdata = { 154 .queue_priority_mapping = da850_queue_priority_mapping, 155 .default_queue = EVENTQ_0, 156 }; 157 158 static struct resource da8xx_edma0_resources[] = { 159 { 160 .name = "edma3_cc", 161 .start = DA8XX_TPCC_BASE, 162 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 163 .flags = IORESOURCE_MEM, 164 }, 165 { 166 .name = "edma3_tc0", 167 .start = DA8XX_TPTC0_BASE, 168 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 169 .flags = IORESOURCE_MEM, 170 }, 171 { 172 .name = "edma3_tc1", 173 .start = DA8XX_TPTC1_BASE, 174 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 175 .flags = IORESOURCE_MEM, 176 }, 177 { 178 .name = "edma3_ccint", 179 .start = IRQ_DA8XX_CCINT0, 180 .flags = IORESOURCE_IRQ, 181 }, 182 { 183 .name = "edma3_ccerrint", 184 .start = IRQ_DA8XX_CCERRINT, 185 .flags = IORESOURCE_IRQ, 186 }, 187 }; 188 189 static struct resource da850_edma1_resources[] = { 190 { 191 .name = "edma3_cc", 192 .start = DA850_TPCC1_BASE, 193 .end = DA850_TPCC1_BASE + SZ_32K - 1, 194 .flags = IORESOURCE_MEM, 195 }, 196 { 197 .name = "edma3_tc0", 198 .start = DA850_TPTC2_BASE, 199 .end = DA850_TPTC2_BASE + SZ_1K - 1, 200 .flags = IORESOURCE_MEM, 201 }, 202 { 203 .name = "edma3_ccint", 204 .start = IRQ_DA850_CCINT1, 205 .flags = IORESOURCE_IRQ, 206 }, 207 { 208 .name = "edma3_ccerrint", 209 .start = IRQ_DA850_CCERRINT1, 210 .flags = IORESOURCE_IRQ, 211 }, 212 }; 213 214 static const struct platform_device_info da8xx_edma0_device __initconst = { 215 .name = "edma", 216 .id = 0, 217 .dma_mask = DMA_BIT_MASK(32), 218 .res = da8xx_edma0_resources, 219 .num_res = ARRAY_SIZE(da8xx_edma0_resources), 220 .data = &da8xx_edma0_pdata, 221 .size_data = sizeof(da8xx_edma0_pdata), 222 }; 223 224 static const struct platform_device_info da850_edma1_device __initconst = { 225 .name = "edma", 226 .id = 1, 227 .dma_mask = DMA_BIT_MASK(32), 228 .res = da850_edma1_resources, 229 .num_res = ARRAY_SIZE(da850_edma1_resources), 230 .data = &da850_edma1_pdata, 231 .size_data = sizeof(da850_edma1_pdata), 232 }; 233 234 static const struct dma_slave_map da830_edma_map[] = { 235 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 236 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 237 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, 238 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, 239 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, 240 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, 241 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 242 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 243 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 244 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 245 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 246 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 247 }; 248 249 int __init da830_register_edma(struct edma_rsv_info *rsv) 250 { 251 struct platform_device *edma_pdev; 252 253 da8xx_edma0_pdata.rsv = rsv; 254 255 da8xx_edma0_pdata.slave_map = da830_edma_map; 256 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); 257 258 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 259 return PTR_ERR_OR_ZERO(edma_pdev); 260 } 261 262 static const struct dma_slave_map da850_edma0_map[] = { 263 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 264 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 265 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, 266 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, 267 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, 268 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, 269 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 270 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 271 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 272 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 273 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 274 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 275 }; 276 277 static const struct dma_slave_map da850_edma1_map[] = { 278 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) }, 279 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) }, 280 }; 281 282 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 283 { 284 struct platform_device *edma_pdev; 285 286 if (rsv) { 287 da8xx_edma0_pdata.rsv = rsv[0]; 288 da850_edma1_pdata.rsv = rsv[1]; 289 } 290 291 da8xx_edma0_pdata.slave_map = da850_edma0_map; 292 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); 293 294 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 295 if (IS_ERR(edma_pdev)) { 296 pr_warn("%s: Failed to register eDMA0\n", __func__); 297 return PTR_ERR(edma_pdev); 298 } 299 300 da850_edma1_pdata.slave_map = da850_edma1_map; 301 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); 302 303 edma_pdev = platform_device_register_full(&da850_edma1_device); 304 return PTR_ERR_OR_ZERO(edma_pdev); 305 } 306 307 static struct resource da8xx_i2c_resources0[] = { 308 { 309 .start = DA8XX_I2C0_BASE, 310 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 311 .flags = IORESOURCE_MEM, 312 }, 313 { 314 .start = IRQ_DA8XX_I2CINT0, 315 .end = IRQ_DA8XX_I2CINT0, 316 .flags = IORESOURCE_IRQ, 317 }, 318 }; 319 320 static struct platform_device da8xx_i2c_device0 = { 321 .name = "i2c_davinci", 322 .id = 1, 323 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 324 .resource = da8xx_i2c_resources0, 325 }; 326 327 static struct resource da8xx_i2c_resources1[] = { 328 { 329 .start = DA8XX_I2C1_BASE, 330 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 331 .flags = IORESOURCE_MEM, 332 }, 333 { 334 .start = IRQ_DA8XX_I2CINT1, 335 .end = IRQ_DA8XX_I2CINT1, 336 .flags = IORESOURCE_IRQ, 337 }, 338 }; 339 340 static struct platform_device da8xx_i2c_device1 = { 341 .name = "i2c_davinci", 342 .id = 2, 343 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 344 .resource = da8xx_i2c_resources1, 345 }; 346 347 int __init da8xx_register_i2c(int instance, 348 struct davinci_i2c_platform_data *pdata) 349 { 350 struct platform_device *pdev; 351 352 if (instance == 0) 353 pdev = &da8xx_i2c_device0; 354 else if (instance == 1) 355 pdev = &da8xx_i2c_device1; 356 else 357 return -EINVAL; 358 359 pdev->dev.platform_data = pdata; 360 return platform_device_register(pdev); 361 } 362 363 static struct resource da8xx_watchdog_resources[] = { 364 { 365 .start = DA8XX_WDOG_BASE, 366 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 367 .flags = IORESOURCE_MEM, 368 }, 369 }; 370 371 static struct platform_device da8xx_wdt_device = { 372 .name = "davinci-wdt", 373 .id = -1, 374 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 375 .resource = da8xx_watchdog_resources, 376 }; 377 378 int __init da8xx_register_watchdog(void) 379 { 380 return platform_device_register(&da8xx_wdt_device); 381 } 382 383 static struct resource da8xx_emac_resources[] = { 384 { 385 .start = DA8XX_EMAC_CPPI_PORT_BASE, 386 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 387 .flags = IORESOURCE_MEM, 388 }, 389 { 390 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, 391 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, 392 .flags = IORESOURCE_IRQ, 393 }, 394 { 395 .start = IRQ_DA8XX_C0_RX_PULSE, 396 .end = IRQ_DA8XX_C0_RX_PULSE, 397 .flags = IORESOURCE_IRQ, 398 }, 399 { 400 .start = IRQ_DA8XX_C0_TX_PULSE, 401 .end = IRQ_DA8XX_C0_TX_PULSE, 402 .flags = IORESOURCE_IRQ, 403 }, 404 { 405 .start = IRQ_DA8XX_C0_MISC_PULSE, 406 .end = IRQ_DA8XX_C0_MISC_PULSE, 407 .flags = IORESOURCE_IRQ, 408 }, 409 }; 410 411 struct emac_platform_data da8xx_emac_pdata = { 412 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 413 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 414 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 415 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 416 .version = EMAC_VERSION_2, 417 }; 418 419 static struct platform_device da8xx_emac_device = { 420 .name = "davinci_emac", 421 .id = 1, 422 .dev = { 423 .platform_data = &da8xx_emac_pdata, 424 }, 425 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 426 .resource = da8xx_emac_resources, 427 }; 428 429 static struct resource da8xx_mdio_resources[] = { 430 { 431 .start = DA8XX_EMAC_MDIO_BASE, 432 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 433 .flags = IORESOURCE_MEM, 434 }, 435 }; 436 437 static struct platform_device da8xx_mdio_device = { 438 .name = "davinci_mdio", 439 .id = 0, 440 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 441 .resource = da8xx_mdio_resources, 442 }; 443 444 int __init da8xx_register_emac(void) 445 { 446 int ret; 447 448 ret = platform_device_register(&da8xx_mdio_device); 449 if (ret < 0) 450 return ret; 451 452 return platform_device_register(&da8xx_emac_device); 453 } 454 455 static struct resource da830_mcasp1_resources[] = { 456 { 457 .name = "mpu", 458 .start = DAVINCI_DA830_MCASP1_REG_BASE, 459 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 460 .flags = IORESOURCE_MEM, 461 }, 462 /* TX event */ 463 { 464 .name = "tx", 465 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 466 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 467 .flags = IORESOURCE_DMA, 468 }, 469 /* RX event */ 470 { 471 .name = "rx", 472 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 473 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 474 .flags = IORESOURCE_DMA, 475 }, 476 { 477 .name = "common", 478 .start = IRQ_DA8XX_MCASPINT, 479 .flags = IORESOURCE_IRQ, 480 }, 481 }; 482 483 static struct platform_device da830_mcasp1_device = { 484 .name = "davinci-mcasp", 485 .id = 1, 486 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 487 .resource = da830_mcasp1_resources, 488 }; 489 490 static struct resource da830_mcasp2_resources[] = { 491 { 492 .name = "mpu", 493 .start = DAVINCI_DA830_MCASP2_REG_BASE, 494 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, 495 .flags = IORESOURCE_MEM, 496 }, 497 /* TX event */ 498 { 499 .name = "tx", 500 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, 501 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, 502 .flags = IORESOURCE_DMA, 503 }, 504 /* RX event */ 505 { 506 .name = "rx", 507 .start = DAVINCI_DA830_DMA_MCASP2_AREVT, 508 .end = DAVINCI_DA830_DMA_MCASP2_AREVT, 509 .flags = IORESOURCE_DMA, 510 }, 511 { 512 .name = "common", 513 .start = IRQ_DA8XX_MCASPINT, 514 .flags = IORESOURCE_IRQ, 515 }, 516 }; 517 518 static struct platform_device da830_mcasp2_device = { 519 .name = "davinci-mcasp", 520 .id = 2, 521 .num_resources = ARRAY_SIZE(da830_mcasp2_resources), 522 .resource = da830_mcasp2_resources, 523 }; 524 525 static struct resource da850_mcasp_resources[] = { 526 { 527 .name = "mpu", 528 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 529 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 530 .flags = IORESOURCE_MEM, 531 }, 532 /* TX event */ 533 { 534 .name = "tx", 535 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 536 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 537 .flags = IORESOURCE_DMA, 538 }, 539 /* RX event */ 540 { 541 .name = "rx", 542 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 543 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 544 .flags = IORESOURCE_DMA, 545 }, 546 { 547 .name = "common", 548 .start = IRQ_DA8XX_MCASPINT, 549 .flags = IORESOURCE_IRQ, 550 }, 551 }; 552 553 static struct platform_device da850_mcasp_device = { 554 .name = "davinci-mcasp", 555 .id = 0, 556 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 557 .resource = da850_mcasp_resources, 558 }; 559 560 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 561 { 562 struct platform_device *pdev; 563 564 switch (id) { 565 case 0: 566 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ 567 pdev = &da850_mcasp_device; 568 break; 569 case 1: 570 /* Valid for DA830/OMAP-L137 only */ 571 if (!cpu_is_davinci_da830()) 572 return; 573 pdev = &da830_mcasp1_device; 574 break; 575 case 2: 576 /* Valid for DA830/OMAP-L137 only */ 577 if (!cpu_is_davinci_da830()) 578 return; 579 pdev = &da830_mcasp2_device; 580 break; 581 default: 582 return; 583 } 584 585 pdev->dev.platform_data = pdata; 586 platform_device_register(pdev); 587 } 588 589 static struct resource da8xx_pruss_resources[] = { 590 { 591 .start = DA8XX_PRUSS_MEM_BASE, 592 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, 593 .flags = IORESOURCE_MEM, 594 }, 595 { 596 .start = IRQ_DA8XX_EVTOUT0, 597 .end = IRQ_DA8XX_EVTOUT0, 598 .flags = IORESOURCE_IRQ, 599 }, 600 { 601 .start = IRQ_DA8XX_EVTOUT1, 602 .end = IRQ_DA8XX_EVTOUT1, 603 .flags = IORESOURCE_IRQ, 604 }, 605 { 606 .start = IRQ_DA8XX_EVTOUT2, 607 .end = IRQ_DA8XX_EVTOUT2, 608 .flags = IORESOURCE_IRQ, 609 }, 610 { 611 .start = IRQ_DA8XX_EVTOUT3, 612 .end = IRQ_DA8XX_EVTOUT3, 613 .flags = IORESOURCE_IRQ, 614 }, 615 { 616 .start = IRQ_DA8XX_EVTOUT4, 617 .end = IRQ_DA8XX_EVTOUT4, 618 .flags = IORESOURCE_IRQ, 619 }, 620 { 621 .start = IRQ_DA8XX_EVTOUT5, 622 .end = IRQ_DA8XX_EVTOUT5, 623 .flags = IORESOURCE_IRQ, 624 }, 625 { 626 .start = IRQ_DA8XX_EVTOUT6, 627 .end = IRQ_DA8XX_EVTOUT6, 628 .flags = IORESOURCE_IRQ, 629 }, 630 { 631 .start = IRQ_DA8XX_EVTOUT7, 632 .end = IRQ_DA8XX_EVTOUT7, 633 .flags = IORESOURCE_IRQ, 634 }, 635 }; 636 637 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { 638 .pintc_base = 0x4000, 639 }; 640 641 static struct platform_device da8xx_uio_pruss_dev = { 642 .name = "pruss_uio", 643 .id = -1, 644 .num_resources = ARRAY_SIZE(da8xx_pruss_resources), 645 .resource = da8xx_pruss_resources, 646 .dev = { 647 .coherent_dma_mask = DMA_BIT_MASK(32), 648 .platform_data = &da8xx_uio_pruss_pdata, 649 } 650 }; 651 652 int __init da8xx_register_uio_pruss(void) 653 { 654 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); 655 return platform_device_register(&da8xx_uio_pruss_dev); 656 } 657 658 static struct lcd_ctrl_config lcd_cfg = { 659 .panel_shade = COLOR_ACTIVE, 660 .bpp = 16, 661 }; 662 663 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 664 .manu_name = "sharp", 665 .controller_data = &lcd_cfg, 666 .type = "Sharp_LCD035Q3DG01", 667 }; 668 669 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 670 .manu_name = "sharp", 671 .controller_data = &lcd_cfg, 672 .type = "Sharp_LK043T1DG01", 673 }; 674 675 static struct resource da8xx_lcdc_resources[] = { 676 [0] = { /* registers */ 677 .start = DA8XX_LCD_CNTRL_BASE, 678 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 679 .flags = IORESOURCE_MEM, 680 }, 681 [1] = { /* interrupt */ 682 .start = IRQ_DA8XX_LCDINT, 683 .end = IRQ_DA8XX_LCDINT, 684 .flags = IORESOURCE_IRQ, 685 }, 686 }; 687 688 static struct platform_device da8xx_lcdc_device = { 689 .name = "da8xx_lcdc", 690 .id = 0, 691 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 692 .resource = da8xx_lcdc_resources, 693 }; 694 695 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 696 { 697 da8xx_lcdc_device.dev.platform_data = pdata; 698 return platform_device_register(&da8xx_lcdc_device); 699 } 700 701 static struct resource da8xx_gpio_resources[] = { 702 { /* registers */ 703 .start = DA8XX_GPIO_BASE, 704 .end = DA8XX_GPIO_BASE + SZ_4K - 1, 705 .flags = IORESOURCE_MEM, 706 }, 707 { /* interrupt */ 708 .start = IRQ_DA8XX_GPIO0, 709 .end = IRQ_DA8XX_GPIO8, 710 .flags = IORESOURCE_IRQ, 711 }, 712 }; 713 714 static struct platform_device da8xx_gpio_device = { 715 .name = "davinci_gpio", 716 .id = -1, 717 .num_resources = ARRAY_SIZE(da8xx_gpio_resources), 718 .resource = da8xx_gpio_resources, 719 }; 720 721 int __init da8xx_register_gpio(void *pdata) 722 { 723 da8xx_gpio_device.dev.platform_data = pdata; 724 return platform_device_register(&da8xx_gpio_device); 725 } 726 727 static struct resource da8xx_mmcsd0_resources[] = { 728 { /* registers */ 729 .start = DA8XX_MMCSD0_BASE, 730 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 731 .flags = IORESOURCE_MEM, 732 }, 733 { /* interrupt */ 734 .start = IRQ_DA8XX_MMCSDINT0, 735 .end = IRQ_DA8XX_MMCSDINT0, 736 .flags = IORESOURCE_IRQ, 737 }, 738 }; 739 740 static struct platform_device da8xx_mmcsd0_device = { 741 .name = "da830-mmc", 742 .id = 0, 743 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 744 .resource = da8xx_mmcsd0_resources, 745 }; 746 747 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 748 { 749 da8xx_mmcsd0_device.dev.platform_data = config; 750 return platform_device_register(&da8xx_mmcsd0_device); 751 } 752 753 #ifdef CONFIG_ARCH_DAVINCI_DA850 754 static struct resource da850_mmcsd1_resources[] = { 755 { /* registers */ 756 .start = DA850_MMCSD1_BASE, 757 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 758 .flags = IORESOURCE_MEM, 759 }, 760 { /* interrupt */ 761 .start = IRQ_DA850_MMCSDINT0_1, 762 .end = IRQ_DA850_MMCSDINT0_1, 763 .flags = IORESOURCE_IRQ, 764 }, 765 }; 766 767 static struct platform_device da850_mmcsd1_device = { 768 .name = "da830-mmc", 769 .id = 1, 770 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 771 .resource = da850_mmcsd1_resources, 772 }; 773 774 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 775 { 776 da850_mmcsd1_device.dev.platform_data = config; 777 return platform_device_register(&da850_mmcsd1_device); 778 } 779 #endif 780 781 static struct resource da8xx_rproc_resources[] = { 782 { /* DSP boot address */ 783 .name = "host1cfg", 784 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, 785 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, 786 .flags = IORESOURCE_MEM, 787 }, 788 { /* DSP interrupt registers */ 789 .name = "chipsig", 790 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, 791 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, 792 .flags = IORESOURCE_MEM, 793 }, 794 { /* DSP L2 RAM */ 795 .name = "l2sram", 796 .start = DA8XX_DSP_L2_RAM_BASE, 797 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, 798 .flags = IORESOURCE_MEM, 799 }, 800 { /* DSP L1P RAM */ 801 .name = "l1pram", 802 .start = DA8XX_DSP_L1P_RAM_BASE, 803 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, 804 .flags = IORESOURCE_MEM, 805 }, 806 { /* DSP L1D RAM */ 807 .name = "l1dram", 808 .start = DA8XX_DSP_L1D_RAM_BASE, 809 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, 810 .flags = IORESOURCE_MEM, 811 }, 812 { /* dsp irq */ 813 .start = IRQ_DA8XX_CHIPINT0, 814 .end = IRQ_DA8XX_CHIPINT0, 815 .flags = IORESOURCE_IRQ, 816 }, 817 }; 818 819 static struct platform_device da8xx_dsp = { 820 .name = "davinci-rproc", 821 .dev = { 822 .coherent_dma_mask = DMA_BIT_MASK(32), 823 }, 824 .num_resources = ARRAY_SIZE(da8xx_rproc_resources), 825 .resource = da8xx_rproc_resources, 826 }; 827 828 static bool rproc_mem_inited __initdata; 829 830 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) 831 832 static phys_addr_t rproc_base __initdata; 833 static unsigned long rproc_size __initdata; 834 835 static int __init early_rproc_mem(char *p) 836 { 837 char *endp; 838 839 if (p == NULL) 840 return 0; 841 842 rproc_size = memparse(p, &endp); 843 if (*endp == '@') 844 rproc_base = memparse(endp + 1, NULL); 845 846 return 0; 847 } 848 early_param("rproc_mem", early_rproc_mem); 849 850 void __init da8xx_rproc_reserve_cma(void) 851 { 852 int ret; 853 854 if (!rproc_base || !rproc_size) { 855 pr_err("%s: 'rproc_mem=nn@address' badly specified\n" 856 " 'nn' and 'address' must both be non-zero\n", 857 __func__); 858 859 return; 860 } 861 862 pr_info("%s: reserving 0x%lx @ 0x%lx...\n", 863 __func__, rproc_size, (unsigned long)rproc_base); 864 865 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); 866 if (ret) 867 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); 868 else 869 rproc_mem_inited = true; 870 } 871 872 #else 873 874 void __init da8xx_rproc_reserve_cma(void) 875 { 876 } 877 878 #endif 879 880 int __init da8xx_register_rproc(void) 881 { 882 int ret; 883 884 if (!rproc_mem_inited) { 885 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", 886 __func__); 887 return -ENOMEM; 888 } 889 890 ret = platform_device_register(&da8xx_dsp); 891 if (ret) 892 pr_err("%s: can't register DSP device: %d\n", __func__, ret); 893 894 return ret; 895 }; 896 897 static struct resource da8xx_rtc_resources[] = { 898 { 899 .start = DA8XX_RTC_BASE, 900 .end = DA8XX_RTC_BASE + SZ_4K - 1, 901 .flags = IORESOURCE_MEM, 902 }, 903 { /* timer irq */ 904 .start = IRQ_DA8XX_RTC, 905 .end = IRQ_DA8XX_RTC, 906 .flags = IORESOURCE_IRQ, 907 }, 908 { /* alarm irq */ 909 .start = IRQ_DA8XX_RTC, 910 .end = IRQ_DA8XX_RTC, 911 .flags = IORESOURCE_IRQ, 912 }, 913 }; 914 915 static struct platform_device da8xx_rtc_device = { 916 .name = "da830-rtc", 917 .id = -1, 918 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 919 .resource = da8xx_rtc_resources, 920 }; 921 922 int da8xx_register_rtc(void) 923 { 924 return platform_device_register(&da8xx_rtc_device); 925 } 926 927 static void __iomem *da8xx_ddr2_ctlr_base; 928 void __iomem * __init da8xx_get_mem_ctlr(void) 929 { 930 if (da8xx_ddr2_ctlr_base) 931 return da8xx_ddr2_ctlr_base; 932 933 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 934 if (!da8xx_ddr2_ctlr_base) 935 pr_warn("%s: Unable to map DDR2 controller", __func__); 936 937 return da8xx_ddr2_ctlr_base; 938 } 939 940 static struct resource da8xx_cpuidle_resources[] = { 941 { 942 .start = DA8XX_DDR2_CTL_BASE, 943 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 944 .flags = IORESOURCE_MEM, 945 }, 946 }; 947 948 /* DA8XX devices support DDR2 power down */ 949 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 950 .ddr2_pdown = 1, 951 }; 952 953 954 static struct platform_device da8xx_cpuidle_device = { 955 .name = "cpuidle-davinci", 956 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 957 .resource = da8xx_cpuidle_resources, 958 .dev = { 959 .platform_data = &da8xx_cpuidle_pdata, 960 }, 961 }; 962 963 int __init da8xx_register_cpuidle(void) 964 { 965 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 966 967 return platform_device_register(&da8xx_cpuidle_device); 968 } 969 970 static struct resource da8xx_spi0_resources[] = { 971 [0] = { 972 .start = DA8XX_SPI0_BASE, 973 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 974 .flags = IORESOURCE_MEM, 975 }, 976 [1] = { 977 .start = IRQ_DA8XX_SPINT0, 978 .end = IRQ_DA8XX_SPINT0, 979 .flags = IORESOURCE_IRQ, 980 }, 981 }; 982 983 static struct resource da8xx_spi1_resources[] = { 984 [0] = { 985 .start = DA830_SPI1_BASE, 986 .end = DA830_SPI1_BASE + SZ_4K - 1, 987 .flags = IORESOURCE_MEM, 988 }, 989 [1] = { 990 .start = IRQ_DA8XX_SPINT1, 991 .end = IRQ_DA8XX_SPINT1, 992 .flags = IORESOURCE_IRQ, 993 }, 994 }; 995 996 static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 997 [0] = { 998 .version = SPI_VERSION_2, 999 .intr_line = 1, 1000 .dma_event_q = EVENTQ_0, 1001 .prescaler_limit = 2, 1002 }, 1003 [1] = { 1004 .version = SPI_VERSION_2, 1005 .intr_line = 1, 1006 .dma_event_q = EVENTQ_0, 1007 .prescaler_limit = 2, 1008 }, 1009 }; 1010 1011 static struct platform_device da8xx_spi_device[] = { 1012 [0] = { 1013 .name = "spi_davinci", 1014 .id = 0, 1015 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 1016 .resource = da8xx_spi0_resources, 1017 .dev = { 1018 .platform_data = &da8xx_spi_pdata[0], 1019 }, 1020 }, 1021 [1] = { 1022 .name = "spi_davinci", 1023 .id = 1, 1024 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 1025 .resource = da8xx_spi1_resources, 1026 .dev = { 1027 .platform_data = &da8xx_spi_pdata[1], 1028 }, 1029 }, 1030 }; 1031 1032 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) 1033 { 1034 if (instance < 0 || instance > 1) 1035 return -EINVAL; 1036 1037 da8xx_spi_pdata[instance].num_chipselect = num_chipselect; 1038 1039 if (instance == 1 && cpu_is_davinci_da850()) { 1040 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 1041 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 1042 } 1043 1044 return platform_device_register(&da8xx_spi_device[instance]); 1045 } 1046 1047 #ifdef CONFIG_ARCH_DAVINCI_DA850 1048 #ifndef CONFIG_COMMON_CLK 1049 static struct clk sata_refclk = { 1050 .name = "sata_refclk", 1051 .set_rate = davinci_simple_set_rate, 1052 }; 1053 1054 static struct clk_lookup sata_refclk_lookup = 1055 CLK("ahci_da850", "refclk", &sata_refclk); 1056 1057 int __init da850_register_sata_refclk(int rate) 1058 { 1059 int ret; 1060 1061 sata_refclk.rate = rate; 1062 ret = clk_register(&sata_refclk); 1063 if (ret) 1064 return ret; 1065 1066 clkdev_add(&sata_refclk_lookup); 1067 1068 return 0; 1069 } 1070 #else 1071 int __init da850_register_sata_refclk(int rate) 1072 { 1073 struct clk *clk; 1074 1075 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); 1076 if (IS_ERR(clk)) 1077 return PTR_ERR(clk); 1078 1079 return clk_register_clkdev(clk, "refclk", "ahci_da850"); 1080 } 1081 #endif 1082 1083 static struct resource da850_sata_resources[] = { 1084 { 1085 .start = DA850_SATA_BASE, 1086 .end = DA850_SATA_BASE + 0x1fff, 1087 .flags = IORESOURCE_MEM, 1088 }, 1089 { 1090 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, 1091 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, 1092 .flags = IORESOURCE_MEM, 1093 }, 1094 { 1095 .start = IRQ_DA850_SATAINT, 1096 .flags = IORESOURCE_IRQ, 1097 }, 1098 }; 1099 1100 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 1101 1102 static struct platform_device da850_sata_device = { 1103 .name = "ahci_da850", 1104 .id = -1, 1105 .dev = { 1106 .dma_mask = &da850_sata_dmamask, 1107 .coherent_dma_mask = DMA_BIT_MASK(32), 1108 }, 1109 .num_resources = ARRAY_SIZE(da850_sata_resources), 1110 .resource = da850_sata_resources, 1111 }; 1112 1113 int __init da850_register_sata(unsigned long refclkpn) 1114 { 1115 int ret; 1116 1117 ret = da850_register_sata_refclk(refclkpn); 1118 if (ret) 1119 return ret; 1120 1121 return platform_device_register(&da850_sata_device); 1122 } 1123 #endif 1124 1125 static struct regmap *da8xx_cfgchip; 1126 1127 static const struct regmap_config da8xx_cfgchip_config __initconst = { 1128 .name = "cfgchip", 1129 .reg_bits = 32, 1130 .val_bits = 32, 1131 .reg_stride = 4, 1132 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, 1133 }; 1134 1135 /** 1136 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap 1137 * 1138 * This is for use on non-DT boards only. For DT boards, use 1139 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") 1140 * 1141 * Returns: Pointer to the CFGCHIP regmap or negative error code. 1142 */ 1143 struct regmap * __init da8xx_get_cfgchip(void) 1144 { 1145 if (IS_ERR_OR_NULL(da8xx_cfgchip)) 1146 da8xx_cfgchip = regmap_init_mmio(NULL, 1147 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), 1148 &da8xx_cfgchip_config); 1149 1150 return da8xx_cfgchip; 1151 } 1152