1 /* 2 * DA8XX/OMAP L1XX platform device data 3 * 4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> 5 * Derived from code that was: 6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 #include <linux/ahci_platform.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/dma-contiguous.h> 18 #include <linux/dmaengine.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 #include <linux/reboot.h> 22 #include <linux/serial_8250.h> 23 24 #include <mach/common.h> 25 #include <mach/cputype.h> 26 #include <mach/da8xx.h> 27 #include <mach/time.h> 28 29 #include "asp.h" 30 #include "cpuidle.h" 31 #include "sram.h" 32 33 #define DA8XX_TPCC_BASE 0x01c00000 34 #define DA8XX_TPTC0_BASE 0x01c08000 35 #define DA8XX_TPTC1_BASE 0x01c08400 36 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 37 #define DA8XX_I2C0_BASE 0x01c22000 38 #define DA8XX_RTC_BASE 0x01c23000 39 #define DA8XX_PRUSS_MEM_BASE 0x01c30000 40 #define DA8XX_MMCSD0_BASE 0x01c40000 41 #define DA8XX_SPI0_BASE 0x01c41000 42 #define DA830_SPI1_BASE 0x01e12000 43 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 44 #define DA850_SATA_BASE 0x01e18000 45 #define DA850_MMCSD1_BASE 0x01e1b000 46 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 47 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 48 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 49 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 50 #define DA8XX_I2C1_BASE 0x01e28000 51 #define DA850_TPCC1_BASE 0x01e30000 52 #define DA850_TPTC2_BASE 0x01e38000 53 #define DA850_SPI1_BASE 0x01f0e000 54 #define DA8XX_DDR2_CTL_BASE 0xb0000000 55 56 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 57 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 58 #define DA8XX_EMAC_RAM_OFFSET 0x0000 59 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 60 61 void __iomem *da8xx_syscfg0_base; 62 void __iomem *da8xx_syscfg1_base; 63 64 static struct plat_serial8250_port da8xx_serial0_pdata[] = { 65 { 66 .mapbase = DA8XX_UART0_BASE, 67 .irq = IRQ_DA8XX_UARTINT0, 68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 69 UPF_IOREMAP, 70 .iotype = UPIO_MEM, 71 .regshift = 2, 72 }, 73 { 74 .flags = 0, 75 } 76 }; 77 static struct plat_serial8250_port da8xx_serial1_pdata[] = { 78 { 79 .mapbase = DA8XX_UART1_BASE, 80 .irq = IRQ_DA8XX_UARTINT1, 81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 82 UPF_IOREMAP, 83 .iotype = UPIO_MEM, 84 .regshift = 2, 85 }, 86 { 87 .flags = 0, 88 } 89 }; 90 static struct plat_serial8250_port da8xx_serial2_pdata[] = { 91 { 92 .mapbase = DA8XX_UART2_BASE, 93 .irq = IRQ_DA8XX_UARTINT2, 94 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 95 UPF_IOREMAP, 96 .iotype = UPIO_MEM, 97 .regshift = 2, 98 }, 99 { 100 .flags = 0, 101 } 102 }; 103 104 struct platform_device da8xx_serial_device[] = { 105 { 106 .name = "serial8250", 107 .id = PLAT8250_DEV_PLATFORM, 108 .dev = { 109 .platform_data = da8xx_serial0_pdata, 110 } 111 }, 112 { 113 .name = "serial8250", 114 .id = PLAT8250_DEV_PLATFORM1, 115 .dev = { 116 .platform_data = da8xx_serial1_pdata, 117 } 118 }, 119 { 120 .name = "serial8250", 121 .id = PLAT8250_DEV_PLATFORM2, 122 .dev = { 123 .platform_data = da8xx_serial2_pdata, 124 } 125 }, 126 { 127 } 128 }; 129 130 static s8 da8xx_queue_priority_mapping[][2] = { 131 /* {event queue no, Priority} */ 132 {0, 3}, 133 {1, 7}, 134 {-1, -1} 135 }; 136 137 static s8 da850_queue_priority_mapping[][2] = { 138 /* {event queue no, Priority} */ 139 {0, 3}, 140 {-1, -1} 141 }; 142 143 static struct edma_soc_info da8xx_edma0_pdata = { 144 .queue_priority_mapping = da8xx_queue_priority_mapping, 145 .default_queue = EVENTQ_1, 146 }; 147 148 static struct edma_soc_info da850_edma1_pdata = { 149 .queue_priority_mapping = da850_queue_priority_mapping, 150 .default_queue = EVENTQ_0, 151 }; 152 153 static struct resource da8xx_edma0_resources[] = { 154 { 155 .name = "edma3_cc", 156 .start = DA8XX_TPCC_BASE, 157 .end = DA8XX_TPCC_BASE + SZ_32K - 1, 158 .flags = IORESOURCE_MEM, 159 }, 160 { 161 .name = "edma3_tc0", 162 .start = DA8XX_TPTC0_BASE, 163 .end = DA8XX_TPTC0_BASE + SZ_1K - 1, 164 .flags = IORESOURCE_MEM, 165 }, 166 { 167 .name = "edma3_tc1", 168 .start = DA8XX_TPTC1_BASE, 169 .end = DA8XX_TPTC1_BASE + SZ_1K - 1, 170 .flags = IORESOURCE_MEM, 171 }, 172 { 173 .name = "edma3_ccint", 174 .start = IRQ_DA8XX_CCINT0, 175 .flags = IORESOURCE_IRQ, 176 }, 177 { 178 .name = "edma3_ccerrint", 179 .start = IRQ_DA8XX_CCERRINT, 180 .flags = IORESOURCE_IRQ, 181 }, 182 }; 183 184 static struct resource da850_edma1_resources[] = { 185 { 186 .name = "edma3_cc", 187 .start = DA850_TPCC1_BASE, 188 .end = DA850_TPCC1_BASE + SZ_32K - 1, 189 .flags = IORESOURCE_MEM, 190 }, 191 { 192 .name = "edma3_tc0", 193 .start = DA850_TPTC2_BASE, 194 .end = DA850_TPTC2_BASE + SZ_1K - 1, 195 .flags = IORESOURCE_MEM, 196 }, 197 { 198 .name = "edma3_ccint", 199 .start = IRQ_DA850_CCINT1, 200 .flags = IORESOURCE_IRQ, 201 }, 202 { 203 .name = "edma3_ccerrint", 204 .start = IRQ_DA850_CCERRINT1, 205 .flags = IORESOURCE_IRQ, 206 }, 207 }; 208 209 static const struct platform_device_info da8xx_edma0_device __initconst = { 210 .name = "edma", 211 .id = 0, 212 .dma_mask = DMA_BIT_MASK(32), 213 .res = da8xx_edma0_resources, 214 .num_res = ARRAY_SIZE(da8xx_edma0_resources), 215 .data = &da8xx_edma0_pdata, 216 .size_data = sizeof(da8xx_edma0_pdata), 217 }; 218 219 static const struct platform_device_info da850_edma1_device __initconst = { 220 .name = "edma", 221 .id = 1, 222 .dma_mask = DMA_BIT_MASK(32), 223 .res = da850_edma1_resources, 224 .num_res = ARRAY_SIZE(da850_edma1_resources), 225 .data = &da850_edma1_pdata, 226 .size_data = sizeof(da850_edma1_pdata), 227 }; 228 229 static const struct dma_slave_map da830_edma_map[] = { 230 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 231 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 232 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, 233 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, 234 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, 235 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, 236 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 237 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 238 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 239 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 240 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 241 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 242 }; 243 244 int __init da830_register_edma(struct edma_rsv_info *rsv) 245 { 246 struct platform_device *edma_pdev; 247 248 da8xx_edma0_pdata.rsv = rsv; 249 250 da8xx_edma0_pdata.slave_map = da830_edma_map; 251 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); 252 253 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 254 return PTR_ERR_OR_ZERO(edma_pdev); 255 } 256 257 static const struct dma_slave_map da850_edma0_map[] = { 258 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, 259 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, 260 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, 261 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, 262 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, 263 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, 264 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, 265 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, 266 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, 267 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, 268 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, 269 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, 270 }; 271 272 static const struct dma_slave_map da850_edma1_map[] = { 273 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) }, 274 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) }, 275 }; 276 277 int __init da850_register_edma(struct edma_rsv_info *rsv[2]) 278 { 279 struct platform_device *edma_pdev; 280 281 if (rsv) { 282 da8xx_edma0_pdata.rsv = rsv[0]; 283 da850_edma1_pdata.rsv = rsv[1]; 284 } 285 286 da8xx_edma0_pdata.slave_map = da850_edma0_map; 287 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); 288 289 edma_pdev = platform_device_register_full(&da8xx_edma0_device); 290 if (IS_ERR(edma_pdev)) { 291 pr_warn("%s: Failed to register eDMA0\n", __func__); 292 return PTR_ERR(edma_pdev); 293 } 294 295 da850_edma1_pdata.slave_map = da850_edma1_map; 296 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); 297 298 edma_pdev = platform_device_register_full(&da850_edma1_device); 299 return PTR_ERR_OR_ZERO(edma_pdev); 300 } 301 302 static struct resource da8xx_i2c_resources0[] = { 303 { 304 .start = DA8XX_I2C0_BASE, 305 .end = DA8XX_I2C0_BASE + SZ_4K - 1, 306 .flags = IORESOURCE_MEM, 307 }, 308 { 309 .start = IRQ_DA8XX_I2CINT0, 310 .end = IRQ_DA8XX_I2CINT0, 311 .flags = IORESOURCE_IRQ, 312 }, 313 }; 314 315 static struct platform_device da8xx_i2c_device0 = { 316 .name = "i2c_davinci", 317 .id = 1, 318 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), 319 .resource = da8xx_i2c_resources0, 320 }; 321 322 static struct resource da8xx_i2c_resources1[] = { 323 { 324 .start = DA8XX_I2C1_BASE, 325 .end = DA8XX_I2C1_BASE + SZ_4K - 1, 326 .flags = IORESOURCE_MEM, 327 }, 328 { 329 .start = IRQ_DA8XX_I2CINT1, 330 .end = IRQ_DA8XX_I2CINT1, 331 .flags = IORESOURCE_IRQ, 332 }, 333 }; 334 335 static struct platform_device da8xx_i2c_device1 = { 336 .name = "i2c_davinci", 337 .id = 2, 338 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), 339 .resource = da8xx_i2c_resources1, 340 }; 341 342 int __init da8xx_register_i2c(int instance, 343 struct davinci_i2c_platform_data *pdata) 344 { 345 struct platform_device *pdev; 346 347 if (instance == 0) 348 pdev = &da8xx_i2c_device0; 349 else if (instance == 1) 350 pdev = &da8xx_i2c_device1; 351 else 352 return -EINVAL; 353 354 pdev->dev.platform_data = pdata; 355 return platform_device_register(pdev); 356 } 357 358 static struct resource da8xx_watchdog_resources[] = { 359 { 360 .start = DA8XX_WDOG_BASE, 361 .end = DA8XX_WDOG_BASE + SZ_4K - 1, 362 .flags = IORESOURCE_MEM, 363 }, 364 }; 365 366 static struct platform_device da8xx_wdt_device = { 367 .name = "davinci-wdt", 368 .id = -1, 369 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), 370 .resource = da8xx_watchdog_resources, 371 }; 372 373 int __init da8xx_register_watchdog(void) 374 { 375 return platform_device_register(&da8xx_wdt_device); 376 } 377 378 static struct resource da8xx_emac_resources[] = { 379 { 380 .start = DA8XX_EMAC_CPPI_PORT_BASE, 381 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, 382 .flags = IORESOURCE_MEM, 383 }, 384 { 385 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, 386 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, 387 .flags = IORESOURCE_IRQ, 388 }, 389 { 390 .start = IRQ_DA8XX_C0_RX_PULSE, 391 .end = IRQ_DA8XX_C0_RX_PULSE, 392 .flags = IORESOURCE_IRQ, 393 }, 394 { 395 .start = IRQ_DA8XX_C0_TX_PULSE, 396 .end = IRQ_DA8XX_C0_TX_PULSE, 397 .flags = IORESOURCE_IRQ, 398 }, 399 { 400 .start = IRQ_DA8XX_C0_MISC_PULSE, 401 .end = IRQ_DA8XX_C0_MISC_PULSE, 402 .flags = IORESOURCE_IRQ, 403 }, 404 }; 405 406 struct emac_platform_data da8xx_emac_pdata = { 407 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, 408 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, 409 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, 410 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, 411 .version = EMAC_VERSION_2, 412 }; 413 414 static struct platform_device da8xx_emac_device = { 415 .name = "davinci_emac", 416 .id = 1, 417 .dev = { 418 .platform_data = &da8xx_emac_pdata, 419 }, 420 .num_resources = ARRAY_SIZE(da8xx_emac_resources), 421 .resource = da8xx_emac_resources, 422 }; 423 424 static struct resource da8xx_mdio_resources[] = { 425 { 426 .start = DA8XX_EMAC_MDIO_BASE, 427 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, 428 .flags = IORESOURCE_MEM, 429 }, 430 }; 431 432 static struct platform_device da8xx_mdio_device = { 433 .name = "davinci_mdio", 434 .id = 0, 435 .num_resources = ARRAY_SIZE(da8xx_mdio_resources), 436 .resource = da8xx_mdio_resources, 437 }; 438 439 int __init da8xx_register_emac(void) 440 { 441 int ret; 442 443 ret = platform_device_register(&da8xx_mdio_device); 444 if (ret < 0) 445 return ret; 446 447 return platform_device_register(&da8xx_emac_device); 448 } 449 450 static struct resource da830_mcasp1_resources[] = { 451 { 452 .name = "mpu", 453 .start = DAVINCI_DA830_MCASP1_REG_BASE, 454 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, 455 .flags = IORESOURCE_MEM, 456 }, 457 /* TX event */ 458 { 459 .name = "tx", 460 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, 461 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, 462 .flags = IORESOURCE_DMA, 463 }, 464 /* RX event */ 465 { 466 .name = "rx", 467 .start = DAVINCI_DA830_DMA_MCASP1_AREVT, 468 .end = DAVINCI_DA830_DMA_MCASP1_AREVT, 469 .flags = IORESOURCE_DMA, 470 }, 471 { 472 .name = "common", 473 .start = IRQ_DA8XX_MCASPINT, 474 .flags = IORESOURCE_IRQ, 475 }, 476 }; 477 478 static struct platform_device da830_mcasp1_device = { 479 .name = "davinci-mcasp", 480 .id = 1, 481 .num_resources = ARRAY_SIZE(da830_mcasp1_resources), 482 .resource = da830_mcasp1_resources, 483 }; 484 485 static struct resource da830_mcasp2_resources[] = { 486 { 487 .name = "mpu", 488 .start = DAVINCI_DA830_MCASP2_REG_BASE, 489 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1, 490 .flags = IORESOURCE_MEM, 491 }, 492 /* TX event */ 493 { 494 .name = "tx", 495 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT, 496 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT, 497 .flags = IORESOURCE_DMA, 498 }, 499 /* RX event */ 500 { 501 .name = "rx", 502 .start = DAVINCI_DA830_DMA_MCASP2_AREVT, 503 .end = DAVINCI_DA830_DMA_MCASP2_AREVT, 504 .flags = IORESOURCE_DMA, 505 }, 506 { 507 .name = "common", 508 .start = IRQ_DA8XX_MCASPINT, 509 .flags = IORESOURCE_IRQ, 510 }, 511 }; 512 513 static struct platform_device da830_mcasp2_device = { 514 .name = "davinci-mcasp", 515 .id = 2, 516 .num_resources = ARRAY_SIZE(da830_mcasp2_resources), 517 .resource = da830_mcasp2_resources, 518 }; 519 520 static struct resource da850_mcasp_resources[] = { 521 { 522 .name = "mpu", 523 .start = DAVINCI_DA8XX_MCASP0_REG_BASE, 524 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, 525 .flags = IORESOURCE_MEM, 526 }, 527 /* TX event */ 528 { 529 .name = "tx", 530 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 531 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, 532 .flags = IORESOURCE_DMA, 533 }, 534 /* RX event */ 535 { 536 .name = "rx", 537 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 538 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, 539 .flags = IORESOURCE_DMA, 540 }, 541 { 542 .name = "common", 543 .start = IRQ_DA8XX_MCASPINT, 544 .flags = IORESOURCE_IRQ, 545 }, 546 }; 547 548 static struct platform_device da850_mcasp_device = { 549 .name = "davinci-mcasp", 550 .id = 0, 551 .num_resources = ARRAY_SIZE(da850_mcasp_resources), 552 .resource = da850_mcasp_resources, 553 }; 554 555 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) 556 { 557 struct platform_device *pdev; 558 559 switch (id) { 560 case 0: 561 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */ 562 pdev = &da850_mcasp_device; 563 break; 564 case 1: 565 /* Valid for DA830/OMAP-L137 only */ 566 if (!cpu_is_davinci_da830()) 567 return; 568 pdev = &da830_mcasp1_device; 569 break; 570 case 2: 571 /* Valid for DA830/OMAP-L137 only */ 572 if (!cpu_is_davinci_da830()) 573 return; 574 pdev = &da830_mcasp2_device; 575 break; 576 default: 577 return; 578 } 579 580 pdev->dev.platform_data = pdata; 581 platform_device_register(pdev); 582 } 583 584 static struct resource da8xx_pruss_resources[] = { 585 { 586 .start = DA8XX_PRUSS_MEM_BASE, 587 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, 588 .flags = IORESOURCE_MEM, 589 }, 590 { 591 .start = IRQ_DA8XX_EVTOUT0, 592 .end = IRQ_DA8XX_EVTOUT0, 593 .flags = IORESOURCE_IRQ, 594 }, 595 { 596 .start = IRQ_DA8XX_EVTOUT1, 597 .end = IRQ_DA8XX_EVTOUT1, 598 .flags = IORESOURCE_IRQ, 599 }, 600 { 601 .start = IRQ_DA8XX_EVTOUT2, 602 .end = IRQ_DA8XX_EVTOUT2, 603 .flags = IORESOURCE_IRQ, 604 }, 605 { 606 .start = IRQ_DA8XX_EVTOUT3, 607 .end = IRQ_DA8XX_EVTOUT3, 608 .flags = IORESOURCE_IRQ, 609 }, 610 { 611 .start = IRQ_DA8XX_EVTOUT4, 612 .end = IRQ_DA8XX_EVTOUT4, 613 .flags = IORESOURCE_IRQ, 614 }, 615 { 616 .start = IRQ_DA8XX_EVTOUT5, 617 .end = IRQ_DA8XX_EVTOUT5, 618 .flags = IORESOURCE_IRQ, 619 }, 620 { 621 .start = IRQ_DA8XX_EVTOUT6, 622 .end = IRQ_DA8XX_EVTOUT6, 623 .flags = IORESOURCE_IRQ, 624 }, 625 { 626 .start = IRQ_DA8XX_EVTOUT7, 627 .end = IRQ_DA8XX_EVTOUT7, 628 .flags = IORESOURCE_IRQ, 629 }, 630 }; 631 632 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { 633 .pintc_base = 0x4000, 634 }; 635 636 static struct platform_device da8xx_uio_pruss_dev = { 637 .name = "pruss_uio", 638 .id = -1, 639 .num_resources = ARRAY_SIZE(da8xx_pruss_resources), 640 .resource = da8xx_pruss_resources, 641 .dev = { 642 .coherent_dma_mask = DMA_BIT_MASK(32), 643 .platform_data = &da8xx_uio_pruss_pdata, 644 } 645 }; 646 647 int __init da8xx_register_uio_pruss(void) 648 { 649 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); 650 return platform_device_register(&da8xx_uio_pruss_dev); 651 } 652 653 static struct lcd_ctrl_config lcd_cfg = { 654 .panel_shade = COLOR_ACTIVE, 655 .bpp = 16, 656 }; 657 658 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { 659 .manu_name = "sharp", 660 .controller_data = &lcd_cfg, 661 .type = "Sharp_LCD035Q3DG01", 662 }; 663 664 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { 665 .manu_name = "sharp", 666 .controller_data = &lcd_cfg, 667 .type = "Sharp_LK043T1DG01", 668 }; 669 670 static struct resource da8xx_lcdc_resources[] = { 671 [0] = { /* registers */ 672 .start = DA8XX_LCD_CNTRL_BASE, 673 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, 674 .flags = IORESOURCE_MEM, 675 }, 676 [1] = { /* interrupt */ 677 .start = IRQ_DA8XX_LCDINT, 678 .end = IRQ_DA8XX_LCDINT, 679 .flags = IORESOURCE_IRQ, 680 }, 681 }; 682 683 static struct platform_device da8xx_lcdc_device = { 684 .name = "da8xx_lcdc", 685 .id = 0, 686 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 687 .resource = da8xx_lcdc_resources, 688 }; 689 690 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) 691 { 692 da8xx_lcdc_device.dev.platform_data = pdata; 693 return platform_device_register(&da8xx_lcdc_device); 694 } 695 696 static struct resource da8xx_gpio_resources[] = { 697 { /* registers */ 698 .start = DA8XX_GPIO_BASE, 699 .end = DA8XX_GPIO_BASE + SZ_4K - 1, 700 .flags = IORESOURCE_MEM, 701 }, 702 { /* interrupt */ 703 .start = IRQ_DA8XX_GPIO0, 704 .end = IRQ_DA8XX_GPIO8, 705 .flags = IORESOURCE_IRQ, 706 }, 707 }; 708 709 static struct platform_device da8xx_gpio_device = { 710 .name = "davinci_gpio", 711 .id = -1, 712 .num_resources = ARRAY_SIZE(da8xx_gpio_resources), 713 .resource = da8xx_gpio_resources, 714 }; 715 716 int __init da8xx_register_gpio(void *pdata) 717 { 718 da8xx_gpio_device.dev.platform_data = pdata; 719 return platform_device_register(&da8xx_gpio_device); 720 } 721 722 static struct resource da8xx_mmcsd0_resources[] = { 723 { /* registers */ 724 .start = DA8XX_MMCSD0_BASE, 725 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, 726 .flags = IORESOURCE_MEM, 727 }, 728 { /* interrupt */ 729 .start = IRQ_DA8XX_MMCSDINT0, 730 .end = IRQ_DA8XX_MMCSDINT0, 731 .flags = IORESOURCE_IRQ, 732 }, 733 }; 734 735 static struct platform_device da8xx_mmcsd0_device = { 736 .name = "da830-mmc", 737 .id = 0, 738 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), 739 .resource = da8xx_mmcsd0_resources, 740 }; 741 742 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) 743 { 744 da8xx_mmcsd0_device.dev.platform_data = config; 745 return platform_device_register(&da8xx_mmcsd0_device); 746 } 747 748 #ifdef CONFIG_ARCH_DAVINCI_DA850 749 static struct resource da850_mmcsd1_resources[] = { 750 { /* registers */ 751 .start = DA850_MMCSD1_BASE, 752 .end = DA850_MMCSD1_BASE + SZ_4K - 1, 753 .flags = IORESOURCE_MEM, 754 }, 755 { /* interrupt */ 756 .start = IRQ_DA850_MMCSDINT0_1, 757 .end = IRQ_DA850_MMCSDINT0_1, 758 .flags = IORESOURCE_IRQ, 759 }, 760 }; 761 762 static struct platform_device da850_mmcsd1_device = { 763 .name = "da830-mmc", 764 .id = 1, 765 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), 766 .resource = da850_mmcsd1_resources, 767 }; 768 769 int __init da850_register_mmcsd1(struct davinci_mmc_config *config) 770 { 771 da850_mmcsd1_device.dev.platform_data = config; 772 return platform_device_register(&da850_mmcsd1_device); 773 } 774 #endif 775 776 static struct resource da8xx_rproc_resources[] = { 777 { /* DSP boot address */ 778 .name = "host1cfg", 779 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, 780 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, 781 .flags = IORESOURCE_MEM, 782 }, 783 { /* DSP interrupt registers */ 784 .name = "chipsig", 785 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, 786 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, 787 .flags = IORESOURCE_MEM, 788 }, 789 { /* DSP L2 RAM */ 790 .name = "l2sram", 791 .start = DA8XX_DSP_L2_RAM_BASE, 792 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1, 793 .flags = IORESOURCE_MEM, 794 }, 795 { /* DSP L1P RAM */ 796 .name = "l1pram", 797 .start = DA8XX_DSP_L1P_RAM_BASE, 798 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1, 799 .flags = IORESOURCE_MEM, 800 }, 801 { /* DSP L1D RAM */ 802 .name = "l1dram", 803 .start = DA8XX_DSP_L1D_RAM_BASE, 804 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1, 805 .flags = IORESOURCE_MEM, 806 }, 807 { /* dsp irq */ 808 .start = IRQ_DA8XX_CHIPINT0, 809 .end = IRQ_DA8XX_CHIPINT0, 810 .flags = IORESOURCE_IRQ, 811 }, 812 }; 813 814 static struct platform_device da8xx_dsp = { 815 .name = "davinci-rproc", 816 .dev = { 817 .coherent_dma_mask = DMA_BIT_MASK(32), 818 }, 819 .num_resources = ARRAY_SIZE(da8xx_rproc_resources), 820 .resource = da8xx_rproc_resources, 821 }; 822 823 static bool rproc_mem_inited __initdata; 824 825 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) 826 827 static phys_addr_t rproc_base __initdata; 828 static unsigned long rproc_size __initdata; 829 830 static int __init early_rproc_mem(char *p) 831 { 832 char *endp; 833 834 if (p == NULL) 835 return 0; 836 837 rproc_size = memparse(p, &endp); 838 if (*endp == '@') 839 rproc_base = memparse(endp + 1, NULL); 840 841 return 0; 842 } 843 early_param("rproc_mem", early_rproc_mem); 844 845 void __init da8xx_rproc_reserve_cma(void) 846 { 847 int ret; 848 849 if (!rproc_base || !rproc_size) { 850 pr_err("%s: 'rproc_mem=nn@address' badly specified\n" 851 " 'nn' and 'address' must both be non-zero\n", 852 __func__); 853 854 return; 855 } 856 857 pr_info("%s: reserving 0x%lx @ 0x%lx...\n", 858 __func__, rproc_size, (unsigned long)rproc_base); 859 860 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); 861 if (ret) 862 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); 863 else 864 rproc_mem_inited = true; 865 } 866 867 #else 868 869 void __init da8xx_rproc_reserve_cma(void) 870 { 871 } 872 873 #endif 874 875 int __init da8xx_register_rproc(void) 876 { 877 int ret; 878 879 if (!rproc_mem_inited) { 880 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n", 881 __func__); 882 return -ENOMEM; 883 } 884 885 ret = platform_device_register(&da8xx_dsp); 886 if (ret) 887 pr_err("%s: can't register DSP device: %d\n", __func__, ret); 888 889 return ret; 890 }; 891 892 static struct resource da8xx_rtc_resources[] = { 893 { 894 .start = DA8XX_RTC_BASE, 895 .end = DA8XX_RTC_BASE + SZ_4K - 1, 896 .flags = IORESOURCE_MEM, 897 }, 898 { /* timer irq */ 899 .start = IRQ_DA8XX_RTC, 900 .end = IRQ_DA8XX_RTC, 901 .flags = IORESOURCE_IRQ, 902 }, 903 { /* alarm irq */ 904 .start = IRQ_DA8XX_RTC, 905 .end = IRQ_DA8XX_RTC, 906 .flags = IORESOURCE_IRQ, 907 }, 908 }; 909 910 static struct platform_device da8xx_rtc_device = { 911 .name = "da830-rtc", 912 .id = -1, 913 .num_resources = ARRAY_SIZE(da8xx_rtc_resources), 914 .resource = da8xx_rtc_resources, 915 }; 916 917 int da8xx_register_rtc(void) 918 { 919 return platform_device_register(&da8xx_rtc_device); 920 } 921 922 static void __iomem *da8xx_ddr2_ctlr_base; 923 void __iomem * __init da8xx_get_mem_ctlr(void) 924 { 925 if (da8xx_ddr2_ctlr_base) 926 return da8xx_ddr2_ctlr_base; 927 928 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); 929 if (!da8xx_ddr2_ctlr_base) 930 pr_warn("%s: Unable to map DDR2 controller", __func__); 931 932 return da8xx_ddr2_ctlr_base; 933 } 934 935 static struct resource da8xx_cpuidle_resources[] = { 936 { 937 .start = DA8XX_DDR2_CTL_BASE, 938 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, 939 .flags = IORESOURCE_MEM, 940 }, 941 }; 942 943 /* DA8XX devices support DDR2 power down */ 944 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { 945 .ddr2_pdown = 1, 946 }; 947 948 949 static struct platform_device da8xx_cpuidle_device = { 950 .name = "cpuidle-davinci", 951 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), 952 .resource = da8xx_cpuidle_resources, 953 .dev = { 954 .platform_data = &da8xx_cpuidle_pdata, 955 }, 956 }; 957 958 int __init da8xx_register_cpuidle(void) 959 { 960 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); 961 962 return platform_device_register(&da8xx_cpuidle_device); 963 } 964 965 static struct resource da8xx_spi0_resources[] = { 966 [0] = { 967 .start = DA8XX_SPI0_BASE, 968 .end = DA8XX_SPI0_BASE + SZ_4K - 1, 969 .flags = IORESOURCE_MEM, 970 }, 971 [1] = { 972 .start = IRQ_DA8XX_SPINT0, 973 .end = IRQ_DA8XX_SPINT0, 974 .flags = IORESOURCE_IRQ, 975 }, 976 }; 977 978 static struct resource da8xx_spi1_resources[] = { 979 [0] = { 980 .start = DA830_SPI1_BASE, 981 .end = DA830_SPI1_BASE + SZ_4K - 1, 982 .flags = IORESOURCE_MEM, 983 }, 984 [1] = { 985 .start = IRQ_DA8XX_SPINT1, 986 .end = IRQ_DA8XX_SPINT1, 987 .flags = IORESOURCE_IRQ, 988 }, 989 }; 990 991 static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 992 [0] = { 993 .version = SPI_VERSION_2, 994 .intr_line = 1, 995 .dma_event_q = EVENTQ_0, 996 .prescaler_limit = 2, 997 }, 998 [1] = { 999 .version = SPI_VERSION_2, 1000 .intr_line = 1, 1001 .dma_event_q = EVENTQ_0, 1002 .prescaler_limit = 2, 1003 }, 1004 }; 1005 1006 static struct platform_device da8xx_spi_device[] = { 1007 [0] = { 1008 .name = "spi_davinci", 1009 .id = 0, 1010 .num_resources = ARRAY_SIZE(da8xx_spi0_resources), 1011 .resource = da8xx_spi0_resources, 1012 .dev = { 1013 .platform_data = &da8xx_spi_pdata[0], 1014 }, 1015 }, 1016 [1] = { 1017 .name = "spi_davinci", 1018 .id = 1, 1019 .num_resources = ARRAY_SIZE(da8xx_spi1_resources), 1020 .resource = da8xx_spi1_resources, 1021 .dev = { 1022 .platform_data = &da8xx_spi_pdata[1], 1023 }, 1024 }, 1025 }; 1026 1027 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) 1028 { 1029 if (instance < 0 || instance > 1) 1030 return -EINVAL; 1031 1032 da8xx_spi_pdata[instance].num_chipselect = num_chipselect; 1033 1034 if (instance == 1 && cpu_is_davinci_da850()) { 1035 da8xx_spi1_resources[0].start = DA850_SPI1_BASE; 1036 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; 1037 } 1038 1039 return platform_device_register(&da8xx_spi_device[instance]); 1040 } 1041 1042 #ifdef CONFIG_ARCH_DAVINCI_DA850 1043 int __init da850_register_sata_refclk(int rate) 1044 { 1045 struct clk *clk; 1046 1047 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate); 1048 if (IS_ERR(clk)) 1049 return PTR_ERR(clk); 1050 1051 return clk_register_clkdev(clk, "refclk", "ahci_da850"); 1052 } 1053 1054 static struct resource da850_sata_resources[] = { 1055 { 1056 .start = DA850_SATA_BASE, 1057 .end = DA850_SATA_BASE + 0x1fff, 1058 .flags = IORESOURCE_MEM, 1059 }, 1060 { 1061 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG, 1062 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3, 1063 .flags = IORESOURCE_MEM, 1064 }, 1065 { 1066 .start = IRQ_DA850_SATAINT, 1067 .flags = IORESOURCE_IRQ, 1068 }, 1069 }; 1070 1071 static u64 da850_sata_dmamask = DMA_BIT_MASK(32); 1072 1073 static struct platform_device da850_sata_device = { 1074 .name = "ahci_da850", 1075 .id = -1, 1076 .dev = { 1077 .dma_mask = &da850_sata_dmamask, 1078 .coherent_dma_mask = DMA_BIT_MASK(32), 1079 }, 1080 .num_resources = ARRAY_SIZE(da850_sata_resources), 1081 .resource = da850_sata_resources, 1082 }; 1083 1084 int __init da850_register_sata(unsigned long refclkpn) 1085 { 1086 int ret; 1087 1088 ret = da850_register_sata_refclk(refclkpn); 1089 if (ret) 1090 return ret; 1091 1092 return platform_device_register(&da850_sata_device); 1093 } 1094 #endif 1095 1096 static struct regmap *da8xx_cfgchip; 1097 1098 static const struct regmap_config da8xx_cfgchip_config __initconst = { 1099 .name = "cfgchip", 1100 .reg_bits = 32, 1101 .val_bits = 32, 1102 .reg_stride = 4, 1103 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG, 1104 }; 1105 1106 /** 1107 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap 1108 * 1109 * This is for use on non-DT boards only. For DT boards, use 1110 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip") 1111 * 1112 * Returns: Pointer to the CFGCHIP regmap or negative error code. 1113 */ 1114 struct regmap * __init da8xx_get_cfgchip(void) 1115 { 1116 if (IS_ERR_OR_NULL(da8xx_cfgchip)) 1117 da8xx_cfgchip = regmap_init_mmio(NULL, 1118 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG), 1119 &da8xx_cfgchip_config); 1120 1121 return da8xx_cfgchip; 1122 } 1123