1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/arm/mach-at91/pm.c 4 * AT91 Power Management 5 * 6 * Copyright (C) 2005 David Brownell 7 */ 8 9 #include <linux/genalloc.h> 10 #include <linux/io.h> 11 #include <linux/of_address.h> 12 #include <linux/of.h> 13 #include <linux/of_fdt.h> 14 #include <linux/of_platform.h> 15 #include <linux/parser.h> 16 #include <linux/suspend.h> 17 18 #include <linux/clk.h> 19 #include <linux/clk/at91_pmc.h> 20 #include <linux/platform_data/atmel.h> 21 22 #include <soc/at91/pm.h> 23 24 #include <asm/cacheflush.h> 25 #include <asm/fncpy.h> 26 #include <asm/system_misc.h> 27 #include <asm/suspend.h> 28 29 #include "generic.h" 30 #include "pm.h" 31 #include "sam_secure.h" 32 33 #define BACKUP_DDR_PHY_CALIBRATION (9) 34 35 /** 36 * struct at91_pm_bu - AT91 power management backup unit data structure 37 * @suspended: true if suspended to backup mode 38 * @reserved: reserved 39 * @canary: canary data for memory checking after exit from backup mode 40 * @resume: resume API 41 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words 42 * of the memory 43 */ 44 struct at91_pm_bu { 45 int suspended; 46 unsigned long reserved; 47 phys_addr_t canary; 48 phys_addr_t resume; 49 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; 50 }; 51 52 /** 53 * struct at91_pm_sfrbu_regs - registers mapping for SFRBU 54 * @pswbu: power switch BU control registers 55 */ 56 struct at91_pm_sfrbu_regs { 57 struct { 58 u32 key; 59 u32 ctrl; 60 u32 state; 61 u32 softsw; 62 } pswbu; 63 }; 64 65 /** 66 * enum at91_pm_eth_clk - Ethernet clock indexes 67 * @AT91_PM_ETH_PCLK: pclk index 68 * @AT91_PM_ETH_HCLK: hclk index 69 * @AT91_PM_ETH_MAX_CLK: max index 70 */ 71 enum at91_pm_eth_clk { 72 AT91_PM_ETH_PCLK, 73 AT91_PM_ETH_HCLK, 74 AT91_PM_ETH_MAX_CLK, 75 }; 76 77 /** 78 * enum at91_pm_eth - Ethernet controller indexes 79 * @AT91_PM_G_ETH: gigabit Ethernet controller index 80 * @AT91_PM_E_ETH: megabit Ethernet controller index 81 * @AT91_PM_MAX_ETH: max index 82 */ 83 enum at91_pm_eth { 84 AT91_PM_G_ETH, 85 AT91_PM_E_ETH, 86 AT91_PM_MAX_ETH, 87 }; 88 89 /** 90 * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks 91 * @dev: Ethernet device 92 * @np: Ethernet device node 93 * @clks: Ethernet clocks 94 * @modes: power management mode that this quirk applies to 95 * @dns_modes: do not suspend modes: stop suspending if Ethernet is configured 96 * as wakeup source but buggy and no other wakeup source is 97 * available 98 */ 99 struct at91_pm_quirk_eth { 100 struct device *dev; 101 struct device_node *np; 102 struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK]; 103 u32 modes; 104 u32 dns_modes; 105 }; 106 107 /** 108 * struct at91_pm_quirks - AT91 PM quirks 109 * @eth: Ethernet quirks 110 */ 111 struct at91_pm_quirks { 112 struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH]; 113 }; 114 115 /** 116 * struct at91_soc_pm - AT91 SoC power management data structure 117 * @config_shdwc_ws: wakeup sources configuration function for SHDWC 118 * @config_pmc_ws: wakeup srouces configuration function for PMC 119 * @ws_ids: wakup sources of_device_id array 120 * @bu: backup unit mapped data (for backup mode) 121 * @quirks: PM quirks 122 * @data: PM data to be used on last phase of suspend 123 * @sfrbu_regs: SFRBU registers mapping 124 * @memcs: memory chip select 125 */ 126 struct at91_soc_pm { 127 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); 128 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); 129 const struct of_device_id *ws_ids; 130 struct at91_pm_bu *bu; 131 struct at91_pm_quirks quirks; 132 struct at91_pm_data data; 133 struct at91_pm_sfrbu_regs sfrbu_regs; 134 void *memcs; 135 }; 136 137 /** 138 * enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes 139 * @AT91_PM_IOMAP_SHDWC: SHDWC controller 140 * @AT91_PM_IOMAP_SFRBU: SFRBU controller 141 * @AT91_PM_IOMAP_ETHC: Ethernet controller 142 */ 143 enum at91_pm_iomaps { 144 AT91_PM_IOMAP_SHDWC, 145 AT91_PM_IOMAP_SFRBU, 146 AT91_PM_IOMAP_ETHC, 147 }; 148 149 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) 150 151 static struct at91_soc_pm soc_pm = { 152 .data = { 153 .standby_mode = AT91_PM_STANDBY, 154 .suspend_mode = AT91_PM_ULP0, 155 }, 156 }; 157 158 static const match_table_t pm_modes __initconst = { 159 { AT91_PM_STANDBY, "standby" }, 160 { AT91_PM_ULP0, "ulp0" }, 161 { AT91_PM_ULP0_FAST, "ulp0-fast" }, 162 { AT91_PM_ULP1, "ulp1" }, 163 { AT91_PM_BACKUP, "backup" }, 164 { -1, NULL }, 165 }; 166 167 #define at91_ramc_read(id, field) \ 168 __raw_readl(soc_pm.data.ramc[id] + field) 169 170 #define at91_ramc_write(id, field, value) \ 171 __raw_writel(value, soc_pm.data.ramc[id] + field) 172 173 static int at91_pm_valid_state(suspend_state_t state) 174 { 175 switch (state) { 176 case PM_SUSPEND_ON: 177 case PM_SUSPEND_STANDBY: 178 case PM_SUSPEND_MEM: 179 return 1; 180 181 default: 182 return 0; 183 } 184 } 185 186 static int canary = 0xA5A5A5A5; 187 188 struct wakeup_source_info { 189 unsigned int pmc_fsmr_bit; 190 unsigned int shdwc_mr_bit; 191 bool set_polarity; 192 }; 193 194 static const struct wakeup_source_info ws_info[] = { 195 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, 196 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, 197 { .pmc_fsmr_bit = AT91_PMC_USBAL }, 198 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, 199 { .pmc_fsmr_bit = AT91_PMC_RTTAL }, 200 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, 201 }; 202 203 static const struct of_device_id sama5d2_ws_ids[] = { 204 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, 205 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, 206 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, 207 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 208 { .compatible = "usb-ohci", .data = &ws_info[2] }, 209 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 210 { .compatible = "usb-ehci", .data = &ws_info[2] }, 211 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, 212 { /* sentinel */ } 213 }; 214 215 static const struct of_device_id sam9x60_ws_ids[] = { 216 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 217 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, 218 { .compatible = "usb-ohci", .data = &ws_info[2] }, 219 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 220 { .compatible = "usb-ehci", .data = &ws_info[2] }, 221 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 222 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, 223 { /* sentinel */ } 224 }; 225 226 static const struct of_device_id sama7g5_ws_ids[] = { 227 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, 228 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, 229 { .compatible = "usb-ohci", .data = &ws_info[2] }, 230 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, 231 { .compatible = "usb-ehci", .data = &ws_info[2] }, 232 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, 233 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, 234 { /* sentinel */ } 235 }; 236 237 static int at91_pm_config_ws(unsigned int pm_mode, bool set) 238 { 239 const struct wakeup_source_info *wsi; 240 const struct of_device_id *match; 241 struct platform_device *pdev; 242 struct device_node *np; 243 unsigned int mode = 0, polarity = 0, val = 0; 244 245 if (pm_mode != AT91_PM_ULP1) 246 return 0; 247 248 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) 249 return -EPERM; 250 251 if (!set) { 252 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); 253 return 0; 254 } 255 256 if (soc_pm.config_shdwc_ws) 257 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); 258 259 /* SHDWC.MR */ 260 val = readl(soc_pm.data.shdwc + 0x04); 261 262 /* Loop through defined wakeup sources. */ 263 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { 264 pdev = of_find_device_by_node(np); 265 if (!pdev) 266 continue; 267 268 if (device_may_wakeup(&pdev->dev)) { 269 wsi = match->data; 270 271 /* Check if enabled on SHDWC. */ 272 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) 273 goto put_device; 274 275 mode |= wsi->pmc_fsmr_bit; 276 if (wsi->set_polarity) 277 polarity |= wsi->pmc_fsmr_bit; 278 } 279 280 put_device: 281 put_device(&pdev->dev); 282 } 283 284 if (mode) { 285 if (soc_pm.config_pmc_ws) 286 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); 287 } else { 288 pr_err("AT91: PM: no ULP1 wakeup sources found!"); 289 } 290 291 return mode ? 0 : -EPERM; 292 } 293 294 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, 295 u32 *polarity) 296 { 297 u32 val; 298 299 /* SHDWC.WUIR */ 300 val = readl(shdwc + 0x0c); 301 *mode |= (val & 0x3ff); 302 *polarity |= ((val >> 16) & 0x3ff); 303 304 return 0; 305 } 306 307 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 308 { 309 writel(mode, pmc + AT91_PMC_FSMR); 310 writel(polarity, pmc + AT91_PMC_FSPR); 311 312 return 0; 313 } 314 315 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) 316 { 317 writel(mode, pmc + AT91_PMC_FSMR); 318 319 return 0; 320 } 321 322 static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth) 323 { 324 struct platform_device *pdev; 325 326 /* Interface NA in DT. */ 327 if (!eth->np) 328 return false; 329 330 /* No quirks for this interface and current suspend mode. */ 331 if (!(eth->modes & BIT(soc_pm.data.mode))) 332 return false; 333 334 if (!eth->dev) { 335 /* Driver not probed. */ 336 pdev = of_find_device_by_node(eth->np); 337 if (!pdev) 338 return false; 339 eth->dev = &pdev->dev; 340 } 341 342 /* No quirks if device isn't a wakeup source. */ 343 if (!device_may_wakeup(eth->dev)) { 344 put_device(eth->dev); 345 return false; 346 } 347 348 /* put_device(eth->dev) is called at the end of suspend. */ 349 return true; 350 } 351 352 static int at91_pm_config_quirks(bool suspend) 353 { 354 struct at91_pm_quirk_eth *eth; 355 int i, j, ret, tmp; 356 357 /* 358 * Ethernet IPs who's device_node pointers are stored into 359 * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1 360 * or both due to a hardware bug. If they receive WoL packets while in 361 * ULP0 or ULP1 IPs could stop working or the whole system could stop 362 * working. We cannot handle this scenario in the ethernet driver itself 363 * as the driver is common to multiple vendors and also we only know 364 * here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle 365 * these scenarios here, as quirks. 366 */ 367 for (i = 0; i < AT91_PM_MAX_ETH; i++) { 368 eth = &soc_pm.quirks.eth[i]; 369 370 if (!at91_pm_eth_quirk_is_valid(eth)) 371 continue; 372 373 /* 374 * For modes in dns_modes mask the system blocks if quirk is not 375 * applied but if applied the interface doesn't act at WoL 376 * events. Thus take care to avoid suspending if this interface 377 * is the only configured wakeup source. 378 */ 379 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) { 380 int ws_count = 0; 381 #ifdef CONFIG_PM_SLEEP 382 struct wakeup_source *ws; 383 384 for_each_wakeup_source(ws) { 385 if (ws->dev == eth->dev) 386 continue; 387 388 ws_count++; 389 break; 390 } 391 #endif 392 393 /* 394 * Checking !ws is good for all platforms with issues 395 * even when both G_ETH and E_ETH are available as dns_modes 396 * is populated only on G_ETH interface. 397 */ 398 if (!ws_count) { 399 pr_err("AT91: PM: Ethernet cannot resume from WoL!"); 400 ret = -EPERM; 401 put_device(eth->dev); 402 eth->dev = NULL; 403 /* No need to revert clock settings for this eth. */ 404 i--; 405 goto clk_unconfigure; 406 } 407 } 408 409 if (suspend) { 410 clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks); 411 } else { 412 ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, 413 eth->clks); 414 if (ret) 415 goto clk_unconfigure; 416 /* 417 * Release the reference to eth->dev taken in 418 * at91_pm_eth_quirk_is_valid(). 419 */ 420 put_device(eth->dev); 421 eth->dev = NULL; 422 } 423 } 424 425 return 0; 426 427 clk_unconfigure: 428 /* 429 * In case of resume we reach this point if clk_prepare_enable() failed. 430 * we don't want to revert the previous clk_prepare_enable() for the 431 * other IP. 432 */ 433 for (j = i; j >= 0; j--) { 434 eth = &soc_pm.quirks.eth[j]; 435 if (suspend) { 436 if (!at91_pm_eth_quirk_is_valid(eth)) 437 continue; 438 439 tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks); 440 if (tmp) { 441 pr_err("AT91: PM: failed to enable %s clocks\n", 442 j == AT91_PM_G_ETH ? "geth" : "eth"); 443 } 444 } else { 445 /* 446 * Release the reference to eth->dev taken in 447 * at91_pm_eth_quirk_is_valid(). 448 */ 449 put_device(eth->dev); 450 eth->dev = NULL; 451 } 452 } 453 454 return ret; 455 } 456 457 /* 458 * Called after processes are frozen, but before we shutdown devices. 459 */ 460 static int at91_pm_begin(suspend_state_t state) 461 { 462 int ret; 463 464 switch (state) { 465 case PM_SUSPEND_MEM: 466 soc_pm.data.mode = soc_pm.data.suspend_mode; 467 break; 468 469 case PM_SUSPEND_STANDBY: 470 soc_pm.data.mode = soc_pm.data.standby_mode; 471 break; 472 473 default: 474 soc_pm.data.mode = -1; 475 } 476 477 ret = at91_pm_config_ws(soc_pm.data.mode, true); 478 if (ret) 479 return ret; 480 481 if (soc_pm.data.mode == AT91_PM_BACKUP) 482 soc_pm.bu->suspended = 1; 483 else if (soc_pm.bu) 484 soc_pm.bu->suspended = 0; 485 486 return 0; 487 } 488 489 /* 490 * Verify that all the clocks are correct before entering 491 * slow-clock mode. 492 */ 493 static int at91_pm_verify_clocks(void) 494 { 495 unsigned long scsr; 496 int i; 497 498 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); 499 500 /* USB must not be using PLLB */ 501 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { 502 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 503 return 0; 504 } 505 506 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 507 for (i = 0; i < 4; i++) { 508 u32 css; 509 510 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 511 continue; 512 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 513 if (css != AT91_PMC_CSS_SLOW) { 514 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 515 return 0; 516 } 517 } 518 519 return 1; 520 } 521 522 /* 523 * Call this from platform driver suspend() to see how deeply to suspend. 524 * For example, some controllers (like OHCI) need one of the PLL clocks 525 * in order to act as a wakeup source, and those are not available when 526 * going into slow clock mode. 527 * 528 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 529 * the very same problem (but not using at91 main_clk), and it'd be better 530 * to add one generic API rather than lots of platform-specific ones. 531 */ 532 int at91_suspend_entering_slow_clock(void) 533 { 534 return (soc_pm.data.mode >= AT91_PM_ULP0); 535 } 536 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 537 538 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 539 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 540 extern u32 at91_pm_suspend_in_sram_sz; 541 542 static int at91_suspend_finish(unsigned long val) 543 { 544 int i; 545 546 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { 547 /* 548 * The 1st 8 words of memory might get corrupted in the process 549 * of DDR PHY recalibration; it is saved here in securam and it 550 * will be restored later, after recalibration, by bootloader 551 */ 552 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) 553 soc_pm.bu->ddr_phy_calibration[i] = 554 *((unsigned int *)soc_pm.memcs + (i - 1)); 555 } 556 557 flush_cache_all(); 558 outer_disable(); 559 560 at91_suspend_sram_fn(&soc_pm.data); 561 562 return 0; 563 } 564 565 static void at91_pm_switch_ba_to_vbat(void) 566 { 567 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); 568 unsigned int val; 569 570 /* Just for safety. */ 571 if (!soc_pm.data.sfrbu) 572 return; 573 574 val = readl(soc_pm.data.sfrbu + offset); 575 576 /* Already on VBAT. */ 577 if (!(val & soc_pm.sfrbu_regs.pswbu.state)) 578 return; 579 580 val &= ~soc_pm.sfrbu_regs.pswbu.softsw; 581 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; 582 writel(val, soc_pm.data.sfrbu + offset); 583 584 /* Wait for update. */ 585 val = readl(soc_pm.data.sfrbu + offset); 586 while (val & soc_pm.sfrbu_regs.pswbu.state) 587 val = readl(soc_pm.data.sfrbu + offset); 588 } 589 590 static void at91_pm_suspend(suspend_state_t state) 591 { 592 if (soc_pm.data.mode == AT91_PM_BACKUP) { 593 at91_pm_switch_ba_to_vbat(); 594 595 cpu_suspend(0, at91_suspend_finish); 596 597 /* The SRAM is lost between suspend cycles */ 598 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 599 &at91_pm_suspend_in_sram, 600 at91_pm_suspend_in_sram_sz); 601 } else { 602 at91_suspend_finish(0); 603 } 604 605 outer_resume(); 606 } 607 608 /* 609 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' 610 * event sources; and reduces DRAM power. But otherwise it's identical to 611 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. 612 * 613 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must 614 * suspend more deeply, the master clock switches to the clk32k and turns off 615 * the main oscillator 616 * 617 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh 618 */ 619 static int at91_pm_enter(suspend_state_t state) 620 { 621 int ret; 622 623 ret = at91_pm_config_quirks(true); 624 if (ret) 625 return ret; 626 627 #ifdef CONFIG_PINCTRL_AT91 628 /* 629 * FIXME: this is needed to communicate between the pinctrl driver and 630 * the PM implementation in the machine. Possibly part of the PM 631 * implementation should be moved down into the pinctrl driver and get 632 * called as part of the generic suspend/resume path. 633 */ 634 at91_pinctrl_gpio_suspend(); 635 #endif 636 637 switch (state) { 638 case PM_SUSPEND_MEM: 639 case PM_SUSPEND_STANDBY: 640 /* 641 * Ensure that clocks are in a valid state. 642 */ 643 if (soc_pm.data.mode >= AT91_PM_ULP0 && 644 !at91_pm_verify_clocks()) 645 goto error; 646 647 at91_pm_suspend(state); 648 649 break; 650 651 case PM_SUSPEND_ON: 652 cpu_do_idle(); 653 break; 654 655 default: 656 pr_debug("AT91: PM - bogus suspend state %d\n", state); 657 goto error; 658 } 659 660 error: 661 #ifdef CONFIG_PINCTRL_AT91 662 at91_pinctrl_gpio_resume(); 663 #endif 664 at91_pm_config_quirks(false); 665 return 0; 666 } 667 668 /* 669 * Called right prior to thawing processes. 670 */ 671 static void at91_pm_end(void) 672 { 673 at91_pm_config_ws(soc_pm.data.mode, false); 674 } 675 676 677 static const struct platform_suspend_ops at91_pm_ops = { 678 .valid = at91_pm_valid_state, 679 .begin = at91_pm_begin, 680 .enter = at91_pm_enter, 681 .end = at91_pm_end, 682 }; 683 684 static struct platform_device at91_cpuidle_device = { 685 .name = "cpuidle-at91", 686 }; 687 688 /* 689 * The AT91RM9200 goes into self-refresh mode with this command, and will 690 * terminate self-refresh automatically on the next SDRAM access. 691 * 692 * Self-refresh mode is exited as soon as a memory access is made, but we don't 693 * know for sure when that happens. However, we need to restore the low-power 694 * mode if it was enabled before going idle. Restoring low-power mode while 695 * still in self-refresh is "not recommended", but seems to work. 696 */ 697 static void at91rm9200_standby(void) 698 { 699 asm volatile( 700 "b 1f\n\t" 701 ".align 5\n\t" 702 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 703 " str %2, [%1, %3]\n\t" 704 " mcr p15, 0, %0, c7, c0, 4\n\t" 705 : 706 : "r" (0), "r" (soc_pm.data.ramc[0]), 707 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 708 } 709 710 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 711 * remember. 712 */ 713 static void at91_ddr_standby(void) 714 { 715 /* Those two values allow us to delay self-refresh activation 716 * to the maximum. */ 717 u32 lpr0, lpr1 = 0; 718 u32 mdr, saved_mdr0, saved_mdr1 = 0; 719 u32 saved_lpr0, saved_lpr1 = 0; 720 721 /* LPDDR1 --> force DDR2 mode during self-refresh */ 722 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 723 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 724 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 725 mdr |= AT91_DDRSDRC_MD_DDR2; 726 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 727 } 728 729 if (soc_pm.data.ramc[1]) { 730 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 731 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 732 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 733 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 734 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 735 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 736 mdr |= AT91_DDRSDRC_MD_DDR2; 737 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 738 } 739 } 740 741 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 742 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 743 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 744 745 /* self-refresh mode now */ 746 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 747 if (soc_pm.data.ramc[1]) 748 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 749 750 cpu_do_idle(); 751 752 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 753 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 754 if (soc_pm.data.ramc[1]) { 755 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 756 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 757 } 758 } 759 760 static void sama5d3_ddr_standby(void) 761 { 762 u32 lpr0; 763 u32 saved_lpr0; 764 765 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 766 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 767 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 768 769 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 770 771 cpu_do_idle(); 772 773 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 774 } 775 776 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 777 * remember. 778 */ 779 static void at91sam9_sdram_standby(void) 780 { 781 u32 lpr0, lpr1 = 0; 782 u32 saved_lpr0, saved_lpr1 = 0; 783 784 if (soc_pm.data.ramc[1]) { 785 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 786 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 787 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 788 } 789 790 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 791 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 792 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 793 794 /* self-refresh mode now */ 795 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 796 if (soc_pm.data.ramc[1]) 797 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 798 799 cpu_do_idle(); 800 801 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 802 if (soc_pm.data.ramc[1]) 803 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 804 } 805 806 static void sama7g5_standby(void) 807 { 808 int pwrtmg, ratio; 809 810 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); 811 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); 812 813 /* 814 * Place RAM into self-refresh after a maximum idle clocks. The maximum 815 * idle clocks is configured by bootloader in 816 * UDDRC_PWRMGT.SELFREF_TO_X32. 817 */ 818 writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, 819 soc_pm.data.ramc[0] + UDDRC_PWRCTL); 820 /* Divide CPU clock by 16. */ 821 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); 822 823 cpu_do_idle(); 824 825 /* Restore previous configuration. */ 826 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); 827 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); 828 } 829 830 struct ramc_info { 831 void (*idle)(void); 832 unsigned int memctrl; 833 }; 834 835 static const struct ramc_info ramc_infos[] __initconst = { 836 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 837 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 838 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 839 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 840 { .idle = sama7g5_standby, }, 841 }; 842 843 static const struct of_device_id ramc_ids[] __initconst = { 844 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 845 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 846 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 847 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 848 { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, 849 { /*sentinel*/ } 850 }; 851 852 static const struct of_device_id ramc_phy_ids[] __initconst = { 853 { .compatible = "microchip,sama7g5-ddr3phy", }, 854 { /* Sentinel. */ }, 855 }; 856 857 static __init int at91_dt_ramc(bool phy_mandatory) 858 { 859 struct device_node *np; 860 const struct of_device_id *of_id; 861 int idx = 0; 862 void *standby = NULL; 863 const struct ramc_info *ramc; 864 int ret; 865 866 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 867 soc_pm.data.ramc[idx] = of_iomap(np, 0); 868 if (!soc_pm.data.ramc[idx]) { 869 pr_err("unable to map ramc[%d] cpu registers\n", idx); 870 ret = -ENOMEM; 871 of_node_put(np); 872 goto unmap_ramc; 873 } 874 875 ramc = of_id->data; 876 if (ramc) { 877 if (!standby) 878 standby = ramc->idle; 879 soc_pm.data.memctrl = ramc->memctrl; 880 } 881 882 idx++; 883 } 884 885 if (!idx) { 886 pr_err("unable to find compatible ram controller node in dtb\n"); 887 ret = -ENODEV; 888 goto unmap_ramc; 889 } 890 891 /* Lookup for DDR PHY node, if any. */ 892 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { 893 soc_pm.data.ramc_phy = of_iomap(np, 0); 894 if (!soc_pm.data.ramc_phy) { 895 pr_err("unable to map ramc phy cpu registers\n"); 896 ret = -ENOMEM; 897 of_node_put(np); 898 goto unmap_ramc; 899 } 900 } 901 902 if (phy_mandatory && !soc_pm.data.ramc_phy) { 903 pr_err("DDR PHY is mandatory!\n"); 904 ret = -ENODEV; 905 goto unmap_ramc; 906 } 907 908 if (!standby) { 909 pr_warn("ramc no standby function available\n"); 910 return 0; 911 } 912 913 at91_cpuidle_device.dev.platform_data = standby; 914 915 return 0; 916 917 unmap_ramc: 918 while (idx) 919 iounmap(soc_pm.data.ramc[--idx]); 920 921 return ret; 922 } 923 924 static void at91rm9200_idle(void) 925 { 926 /* 927 * Disable the processor clock. The processor will be automatically 928 * re-enabled by an interrupt or by a reset. 929 */ 930 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 931 } 932 933 static void at91sam9_idle(void) 934 { 935 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); 936 cpu_do_idle(); 937 } 938 939 static void __init at91_pm_sram_init(void) 940 { 941 struct gen_pool *sram_pool; 942 phys_addr_t sram_pbase; 943 unsigned long sram_base; 944 struct device_node *node; 945 struct platform_device *pdev = NULL; 946 947 for_each_compatible_node(node, NULL, "mmio-sram") { 948 pdev = of_find_device_by_node(node); 949 if (pdev) { 950 of_node_put(node); 951 break; 952 } 953 } 954 955 if (!pdev) { 956 pr_warn("%s: failed to find sram device!\n", __func__); 957 return; 958 } 959 960 sram_pool = gen_pool_get(&pdev->dev, NULL); 961 if (!sram_pool) { 962 pr_warn("%s: sram pool unavailable!\n", __func__); 963 goto out_put_device; 964 } 965 966 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 967 if (!sram_base) { 968 pr_warn("%s: unable to alloc sram!\n", __func__); 969 goto out_put_device; 970 } 971 972 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 973 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 974 at91_pm_suspend_in_sram_sz, false); 975 if (!at91_suspend_sram_fn) { 976 pr_warn("SRAM: Could not map\n"); 977 goto out_put_device; 978 } 979 980 /* Copy the pm suspend handler to SRAM */ 981 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 982 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 983 return; 984 985 out_put_device: 986 put_device(&pdev->dev); 987 return; 988 } 989 990 static bool __init at91_is_pm_mode_active(int pm_mode) 991 { 992 return (soc_pm.data.standby_mode == pm_mode || 993 soc_pm.data.suspend_mode == pm_mode); 994 } 995 996 static int __init at91_pm_backup_scan_memcs(unsigned long node, 997 const char *uname, int depth, 998 void *data) 999 { 1000 const char *type; 1001 const __be32 *reg; 1002 int *located = data; 1003 int size; 1004 1005 /* Memory node already located. */ 1006 if (*located) 1007 return 0; 1008 1009 type = of_get_flat_dt_prop(node, "device_type", NULL); 1010 1011 /* We are scanning "memory" nodes only. */ 1012 if (!type || strcmp(type, "memory")) 1013 return 0; 1014 1015 reg = of_get_flat_dt_prop(node, "reg", &size); 1016 if (reg) { 1017 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); 1018 *located = 1; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int __init at91_pm_backup_init(void) 1025 { 1026 struct gen_pool *sram_pool; 1027 struct device_node *np; 1028 struct platform_device *pdev; 1029 int ret = -ENODEV, located = 0; 1030 1031 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && 1032 !IS_ENABLED(CONFIG_SOC_SAMA7G5)) 1033 return -EPERM; 1034 1035 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) 1036 return 0; 1037 1038 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); 1039 if (!np) 1040 return ret; 1041 1042 pdev = of_find_device_by_node(np); 1043 of_node_put(np); 1044 if (!pdev) { 1045 pr_warn("%s: failed to find securam device!\n", __func__); 1046 return ret; 1047 } 1048 1049 sram_pool = gen_pool_get(&pdev->dev, NULL); 1050 if (!sram_pool) { 1051 pr_warn("%s: securam pool unavailable!\n", __func__); 1052 goto securam_fail; 1053 } 1054 1055 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); 1056 if (!soc_pm.bu) { 1057 pr_warn("%s: unable to alloc securam!\n", __func__); 1058 ret = -ENOMEM; 1059 goto securam_fail; 1060 } 1061 1062 soc_pm.bu->suspended = 0; 1063 soc_pm.bu->canary = __pa_symbol(&canary); 1064 soc_pm.bu->resume = __pa_symbol(cpu_resume); 1065 if (soc_pm.data.ramc_phy) { 1066 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); 1067 if (!located) 1068 goto securam_fail; 1069 1070 /* DDR3PHY_ZQ0SR0 */ 1071 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy + 1072 0x188); 1073 } 1074 1075 return 0; 1076 1077 securam_fail: 1078 put_device(&pdev->dev); 1079 return ret; 1080 } 1081 1082 static void at91_pm_secure_init(void) 1083 { 1084 int suspend_mode; 1085 struct arm_smccc_res res; 1086 1087 suspend_mode = soc_pm.data.suspend_mode; 1088 1089 res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE, 1090 suspend_mode, 0); 1091 if (res.a0 == 0) { 1092 pr_info("AT91: Secure PM: suspend mode set to %s\n", 1093 pm_modes[suspend_mode].pattern); 1094 return; 1095 } 1096 1097 pr_warn("AT91: Secure PM: %s mode not supported !\n", 1098 pm_modes[suspend_mode].pattern); 1099 1100 res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0); 1101 if (res.a0 == 0) { 1102 pr_warn("AT91: Secure PM: failed to get default mode\n"); 1103 return; 1104 } 1105 1106 pr_info("AT91: Secure PM: using default suspend mode %s\n", 1107 pm_modes[suspend_mode].pattern); 1108 1109 soc_pm.data.suspend_mode = res.a1; 1110 } 1111 static const struct of_device_id atmel_shdwc_ids[] = { 1112 { .compatible = "atmel,sama5d2-shdwc" }, 1113 { .compatible = "microchip,sam9x60-shdwc" }, 1114 { .compatible = "microchip,sama7g5-shdwc" }, 1115 { /* sentinel. */ } 1116 }; 1117 1118 static const struct of_device_id gmac_ids[] __initconst = { 1119 { .compatible = "atmel,sama5d3-gem" }, 1120 { .compatible = "atmel,sama5d2-gem" }, 1121 { .compatible = "atmel,sama5d29-gem" }, 1122 { .compatible = "microchip,sama7g5-gem" }, 1123 { }, 1124 }; 1125 1126 static const struct of_device_id emac_ids[] __initconst = { 1127 { .compatible = "atmel,sama5d3-macb" }, 1128 { .compatible = "microchip,sama7g5-emac" }, 1129 { }, 1130 }; 1131 1132 /* 1133 * Replaces _mode_to_replace with a supported mode that doesn't depend 1134 * on controller pointed by _map_bitmask 1135 * @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91 1136 * PM mode 1137 * @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on 1138 * controller represented by _map_bitmask, _mode_to_replace needs to be 1139 * updated 1140 * @_mode_to_replace: standby_mode or suspend_mode that need to be 1141 * updated 1142 * @_mode_to_check: standby_mode or suspend_mode; this is needed here 1143 * to avoid having standby_mode and suspend_mode set with the same AT91 1144 * PM mode 1145 */ 1146 #define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \ 1147 _mode_to_check) \ 1148 do { \ 1149 if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \ 1150 int _mode_to_use, _mode_complementary; \ 1151 /* Use ULP0 if it doesn't need _map_bitmask. */ \ 1152 if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\ 1153 _mode_to_use = AT91_PM_ULP0; \ 1154 _mode_complementary = AT91_PM_STANDBY; \ 1155 } else { \ 1156 _mode_to_use = AT91_PM_STANDBY; \ 1157 _mode_complementary = AT91_PM_STANDBY; \ 1158 } \ 1159 \ 1160 if ((_mode_to_check) != _mode_to_use) \ 1161 (_mode_to_replace) = _mode_to_use; \ 1162 else \ 1163 (_mode_to_replace) = _mode_complementary;\ 1164 } \ 1165 } while (0) 1166 1167 /* 1168 * Replaces standby and suspend modes with default supported modes: 1169 * ULP0 and STANDBY. 1170 * @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP() 1171 * flags 1172 * @_map: controller specific name; standby and suspend mode need to be 1173 * replaced in order to not depend on this controller 1174 */ 1175 #define AT91_PM_REPLACE_MODES(_maps, _map) \ 1176 do { \ 1177 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ 1178 (soc_pm.data.standby_mode), \ 1179 (soc_pm.data.suspend_mode)); \ 1180 AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ 1181 (soc_pm.data.suspend_mode), \ 1182 (soc_pm.data.standby_mode)); \ 1183 } while (0) 1184 1185 static int __init at91_pm_get_eth_clks(struct device_node *np, 1186 struct clk_bulk_data *clks) 1187 { 1188 clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk"); 1189 if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk)) 1190 return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk); 1191 1192 clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk"); 1193 if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk)) 1194 return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk); 1195 1196 return 0; 1197 } 1198 1199 static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks) 1200 { 1201 return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) || 1202 IS_ERR(clks[AT91_PM_ETH_HCLK].clk); 1203 } 1204 1205 static void __init at91_pm_modes_init(const u32 *maps, int len) 1206 { 1207 struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH]; 1208 struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH]; 1209 struct device_node *np; 1210 int ret; 1211 1212 ret = at91_pm_backup_init(); 1213 if (ret) { 1214 if (soc_pm.data.standby_mode == AT91_PM_BACKUP) 1215 soc_pm.data.standby_mode = AT91_PM_ULP0; 1216 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) 1217 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1218 } 1219 1220 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 1221 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { 1222 np = of_find_matching_node(NULL, atmel_shdwc_ids); 1223 if (!np) { 1224 pr_warn("%s: failed to find shdwc!\n", __func__); 1225 AT91_PM_REPLACE_MODES(maps, SHDWC); 1226 } else { 1227 soc_pm.data.shdwc = of_iomap(np, 0); 1228 of_node_put(np); 1229 } 1230 } 1231 1232 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 1233 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { 1234 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); 1235 if (!np) { 1236 pr_warn("%s: failed to find sfrbu!\n", __func__); 1237 AT91_PM_REPLACE_MODES(maps, SFRBU); 1238 } else { 1239 soc_pm.data.sfrbu = of_iomap(np, 0); 1240 of_node_put(np); 1241 } 1242 } 1243 1244 if ((at91_is_pm_mode_active(AT91_PM_ULP1) || 1245 at91_is_pm_mode_active(AT91_PM_ULP0) || 1246 at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) && 1247 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) || 1248 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) { 1249 np = of_find_matching_node(NULL, gmac_ids); 1250 if (!np) { 1251 np = of_find_matching_node(NULL, emac_ids); 1252 if (np) 1253 goto get_emac_clks; 1254 AT91_PM_REPLACE_MODES(maps, ETHC); 1255 goto unmap_unused_nodes; 1256 } else { 1257 gmac->np = np; 1258 at91_pm_get_eth_clks(np, gmac->clks); 1259 } 1260 1261 np = of_find_matching_node(NULL, emac_ids); 1262 if (!np) { 1263 if (at91_pm_eth_clks_empty(gmac->clks)) 1264 AT91_PM_REPLACE_MODES(maps, ETHC); 1265 } else { 1266 get_emac_clks: 1267 emac->np = np; 1268 ret = at91_pm_get_eth_clks(np, emac->clks); 1269 if (ret && at91_pm_eth_clks_empty(gmac->clks)) { 1270 of_node_put(gmac->np); 1271 of_node_put(emac->np); 1272 gmac->np = NULL; 1273 emac->np = NULL; 1274 } 1275 } 1276 } 1277 1278 unmap_unused_nodes: 1279 /* Unmap all unnecessary. */ 1280 if (soc_pm.data.shdwc && 1281 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || 1282 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { 1283 iounmap(soc_pm.data.shdwc); 1284 soc_pm.data.shdwc = NULL; 1285 } 1286 1287 if (soc_pm.data.sfrbu && 1288 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || 1289 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { 1290 iounmap(soc_pm.data.sfrbu); 1291 soc_pm.data.sfrbu = NULL; 1292 } 1293 1294 return; 1295 } 1296 1297 struct pmc_info { 1298 unsigned long uhp_udp_mask; 1299 unsigned long mckr; 1300 unsigned long version; 1301 }; 1302 1303 static const struct pmc_info pmc_infos[] __initconst = { 1304 { 1305 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, 1306 .mckr = 0x30, 1307 .version = AT91_PMC_V1, 1308 }, 1309 1310 { 1311 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 1312 .mckr = 0x30, 1313 .version = AT91_PMC_V1, 1314 }, 1315 { 1316 .uhp_udp_mask = AT91SAM926x_PMC_UHP, 1317 .mckr = 0x30, 1318 .version = AT91_PMC_V1, 1319 }, 1320 { .uhp_udp_mask = 0, 1321 .mckr = 0x30, 1322 .version = AT91_PMC_V1, 1323 }, 1324 { 1325 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, 1326 .mckr = 0x28, 1327 .version = AT91_PMC_V2, 1328 }, 1329 { 1330 .mckr = 0x28, 1331 .version = AT91_PMC_V2, 1332 }, 1333 1334 }; 1335 1336 static const struct of_device_id atmel_pmc_ids[] __initconst = { 1337 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 1338 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 1339 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, 1340 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, 1341 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 1342 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 1343 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, 1344 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 1345 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 1346 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, 1347 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 1348 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, 1349 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, 1350 { /* sentinel */ }, 1351 }; 1352 1353 static void __init at91_pm_modes_validate(const int *modes, int len) 1354 { 1355 u8 i, standby = 0, suspend = 0; 1356 int mode; 1357 1358 for (i = 0; i < len; i++) { 1359 if (standby && suspend) 1360 break; 1361 1362 if (modes[i] == soc_pm.data.standby_mode && !standby) { 1363 standby = 1; 1364 continue; 1365 } 1366 1367 if (modes[i] == soc_pm.data.suspend_mode && !suspend) { 1368 suspend = 1; 1369 continue; 1370 } 1371 } 1372 1373 if (!standby) { 1374 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) 1375 mode = AT91_PM_ULP0; 1376 else 1377 mode = AT91_PM_STANDBY; 1378 1379 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1380 pm_modes[soc_pm.data.standby_mode].pattern, 1381 pm_modes[mode].pattern); 1382 soc_pm.data.standby_mode = mode; 1383 } 1384 1385 if (!suspend) { 1386 if (soc_pm.data.standby_mode == AT91_PM_ULP0) 1387 mode = AT91_PM_STANDBY; 1388 else 1389 mode = AT91_PM_ULP0; 1390 1391 pr_warn("AT91: PM: %s mode not supported! Using %s.\n", 1392 pm_modes[soc_pm.data.suspend_mode].pattern, 1393 pm_modes[mode].pattern); 1394 soc_pm.data.suspend_mode = mode; 1395 } 1396 } 1397 1398 static void __init at91_pm_init(void (*pm_idle)(void)) 1399 { 1400 struct device_node *pmc_np; 1401 const struct of_device_id *of_id; 1402 const struct pmc_info *pmc; 1403 1404 if (at91_cpuidle_device.dev.platform_data) 1405 platform_device_register(&at91_cpuidle_device); 1406 1407 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 1408 soc_pm.data.pmc = of_iomap(pmc_np, 0); 1409 of_node_put(pmc_np); 1410 if (!soc_pm.data.pmc) { 1411 pr_err("AT91: PM not supported, PMC not found\n"); 1412 return; 1413 } 1414 1415 pmc = of_id->data; 1416 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; 1417 soc_pm.data.pmc_mckr_offset = pmc->mckr; 1418 soc_pm.data.pmc_version = pmc->version; 1419 1420 if (pm_idle) 1421 arm_pm_idle = pm_idle; 1422 1423 at91_pm_sram_init(); 1424 1425 if (at91_suspend_sram_fn) { 1426 suspend_set_ops(&at91_pm_ops); 1427 pr_info("AT91: PM: standby: %s, suspend: %s\n", 1428 pm_modes[soc_pm.data.standby_mode].pattern, 1429 pm_modes[soc_pm.data.suspend_mode].pattern); 1430 } else { 1431 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 1432 } 1433 } 1434 1435 void __init at91rm9200_pm_init(void) 1436 { 1437 int ret; 1438 1439 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) 1440 return; 1441 1442 /* 1443 * Force STANDBY and ULP0 mode to avoid calling 1444 * at91_pm_modes_validate() which may increase booting time. 1445 * Platform supports anyway only STANDBY and ULP0 modes. 1446 */ 1447 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1448 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1449 1450 ret = at91_dt_ramc(false); 1451 if (ret) 1452 return; 1453 1454 /* 1455 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 1456 */ 1457 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 1458 1459 at91_pm_init(at91rm9200_idle); 1460 } 1461 1462 void __init sam9x60_pm_init(void) 1463 { 1464 static const int modes[] __initconst = { 1465 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1466 }; 1467 static const int iomaps[] __initconst = { 1468 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), 1469 }; 1470 int ret; 1471 1472 if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) 1473 return; 1474 1475 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1476 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1477 ret = at91_dt_ramc(false); 1478 if (ret) 1479 return; 1480 1481 at91_pm_init(NULL); 1482 1483 soc_pm.ws_ids = sam9x60_ws_ids; 1484 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1485 } 1486 1487 void __init at91sam9_pm_init(void) 1488 { 1489 int ret; 1490 1491 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) 1492 return; 1493 1494 /* 1495 * Force STANDBY and ULP0 mode to avoid calling 1496 * at91_pm_modes_validate() which may increase booting time. 1497 * Platform supports anyway only STANDBY and ULP0 modes. 1498 */ 1499 soc_pm.data.standby_mode = AT91_PM_STANDBY; 1500 soc_pm.data.suspend_mode = AT91_PM_ULP0; 1501 1502 ret = at91_dt_ramc(false); 1503 if (ret) 1504 return; 1505 1506 at91_pm_init(at91sam9_idle); 1507 } 1508 1509 void __init sama5_pm_init(void) 1510 { 1511 static const int modes[] __initconst = { 1512 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, 1513 }; 1514 static const u32 iomaps[] __initconst = { 1515 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), 1516 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), 1517 }; 1518 int ret; 1519 1520 if (!IS_ENABLED(CONFIG_SOC_SAMA5)) 1521 return; 1522 1523 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1524 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1525 ret = at91_dt_ramc(false); 1526 if (ret) 1527 return; 1528 1529 at91_pm_init(NULL); 1530 1531 /* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */ 1532 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | 1533 BIT(AT91_PM_ULP0_FAST) | 1534 BIT(AT91_PM_ULP1); 1535 /* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */ 1536 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | 1537 BIT(AT91_PM_ULP0_FAST); 1538 } 1539 1540 void __init sama5d2_pm_init(void) 1541 { 1542 static const int modes[] __initconst = { 1543 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, 1544 AT91_PM_BACKUP, 1545 }; 1546 static const u32 iomaps[] __initconst = { 1547 [AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), 1548 [AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), 1549 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) | 1550 AT91_PM_IOMAP(ETHC), 1551 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | 1552 AT91_PM_IOMAP(SFRBU), 1553 }; 1554 int ret; 1555 1556 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) 1557 return; 1558 1559 if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) { 1560 pr_warn("AT91: Secure PM: ignoring standby mode\n"); 1561 at91_pm_secure_init(); 1562 return; 1563 } 1564 1565 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1566 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1567 ret = at91_dt_ramc(false); 1568 if (ret) 1569 return; 1570 1571 at91_pm_init(NULL); 1572 1573 soc_pm.ws_ids = sama5d2_ws_ids; 1574 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; 1575 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; 1576 1577 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1578 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1579 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1580 soc_pm.sfrbu_regs.pswbu.state = BIT(3); 1581 1582 /* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */ 1583 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | 1584 BIT(AT91_PM_ULP0_FAST) | 1585 BIT(AT91_PM_ULP1); 1586 /* 1587 * Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup 1588 * source. 1589 */ 1590 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | 1591 BIT(AT91_PM_ULP0_FAST); 1592 } 1593 1594 void __init sama7_pm_init(void) 1595 { 1596 static const int modes[] __initconst = { 1597 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, 1598 }; 1599 static const u32 iomaps[] __initconst = { 1600 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), 1601 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | 1602 AT91_PM_IOMAP(SHDWC) | 1603 AT91_PM_IOMAP(ETHC), 1604 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | 1605 AT91_PM_IOMAP(SHDWC), 1606 }; 1607 int ret; 1608 1609 if (!IS_ENABLED(CONFIG_SOC_SAMA7)) 1610 return; 1611 1612 at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); 1613 1614 ret = at91_dt_ramc(true); 1615 if (ret) 1616 return; 1617 1618 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); 1619 at91_pm_init(NULL); 1620 1621 soc_pm.ws_ids = sama7g5_ws_ids; 1622 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; 1623 1624 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); 1625 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); 1626 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); 1627 soc_pm.sfrbu_regs.pswbu.state = BIT(2); 1628 1629 /* Quirks applies to ULP1 for both Ethernet interfaces. */ 1630 soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1); 1631 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1); 1632 } 1633 1634 static int __init at91_pm_modes_select(char *str) 1635 { 1636 char *s; 1637 substring_t args[MAX_OPT_ARGS]; 1638 int standby, suspend; 1639 1640 if (!str) 1641 return 0; 1642 1643 s = strsep(&str, ","); 1644 standby = match_token(s, pm_modes, args); 1645 if (standby < 0) 1646 return 0; 1647 1648 suspend = match_token(str, pm_modes, args); 1649 if (suspend < 0) 1650 return 0; 1651 1652 soc_pm.data.standby_mode = standby; 1653 soc_pm.data.suspend_mode = suspend; 1654 1655 return 0; 1656 } 1657 early_param("atmel.pm_modes", at91_pm_modes_select); 1658