1 /* 2 * arch/arm/mach-at91/pm.c 3 * AT91 Power Management 4 * 5 * Copyright (C) 2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #include <linux/genalloc.h> 14 #include <linux/io.h> 15 #include <linux/of_address.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/suspend.h> 19 20 #include <linux/clk/at91_pmc.h> 21 22 #include <asm/cacheflush.h> 23 #include <asm/fncpy.h> 24 #include <asm/system_misc.h> 25 26 #include "generic.h" 27 #include "pm.h" 28 29 /* 30 * FIXME: this is needed to communicate between the pinctrl driver and 31 * the PM implementation in the machine. Possibly part of the PM 32 * implementation should be moved down into the pinctrl driver and get 33 * called as part of the generic suspend/resume path. 34 */ 35 #ifdef CONFIG_PINCTRL_AT91 36 extern void at91_pinctrl_gpio_suspend(void); 37 extern void at91_pinctrl_gpio_resume(void); 38 #endif 39 40 static struct at91_pm_data pm_data; 41 42 #define at91_ramc_read(id, field) \ 43 __raw_readl(pm_data.ramc[id] + field) 44 45 #define at91_ramc_write(id, field, value) \ 46 __raw_writel(value, pm_data.ramc[id] + field) 47 48 static int at91_pm_valid_state(suspend_state_t state) 49 { 50 switch (state) { 51 case PM_SUSPEND_ON: 52 case PM_SUSPEND_STANDBY: 53 case PM_SUSPEND_MEM: 54 return 1; 55 56 default: 57 return 0; 58 } 59 } 60 61 62 static suspend_state_t target_state; 63 64 /* 65 * Called after processes are frozen, but before we shutdown devices. 66 */ 67 static int at91_pm_begin(suspend_state_t state) 68 { 69 target_state = state; 70 return 0; 71 } 72 73 /* 74 * Verify that all the clocks are correct before entering 75 * slow-clock mode. 76 */ 77 static int at91_pm_verify_clocks(void) 78 { 79 unsigned long scsr; 80 int i; 81 82 scsr = readl(pm_data.pmc + AT91_PMC_SCSR); 83 84 /* USB must not be using PLLB */ 85 if ((scsr & pm_data.uhp_udp_mask) != 0) { 86 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 87 return 0; 88 } 89 90 /* PCK0..PCK3 must be disabled, or configured to use clk32k */ 91 for (i = 0; i < 4; i++) { 92 u32 css; 93 94 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 95 continue; 96 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 97 if (css != AT91_PMC_CSS_SLOW) { 98 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 99 return 0; 100 } 101 } 102 103 return 1; 104 } 105 106 /* 107 * Call this from platform driver suspend() to see how deeply to suspend. 108 * For example, some controllers (like OHCI) need one of the PLL clocks 109 * in order to act as a wakeup source, and those are not available when 110 * going into slow clock mode. 111 * 112 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have 113 * the very same problem (but not using at91 main_clk), and it'd be better 114 * to add one generic API rather than lots of platform-specific ones. 115 */ 116 int at91_suspend_entering_slow_clock(void) 117 { 118 return (target_state == PM_SUSPEND_MEM); 119 } 120 EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 121 122 static void (*at91_suspend_sram_fn)(struct at91_pm_data *); 123 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); 124 extern u32 at91_pm_suspend_in_sram_sz; 125 126 static void at91_pm_suspend(suspend_state_t state) 127 { 128 pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0; 129 130 flush_cache_all(); 131 outer_disable(); 132 133 at91_suspend_sram_fn(&pm_data); 134 135 outer_resume(); 136 } 137 138 static int at91_pm_enter(suspend_state_t state) 139 { 140 #ifdef CONFIG_PINCTRL_AT91 141 at91_pinctrl_gpio_suspend(); 142 #endif 143 switch (state) { 144 /* 145 * Suspend-to-RAM is like STANDBY plus slow clock mode, so 146 * drivers must suspend more deeply, the master clock switches 147 * to the clk32k and turns off the main oscillator 148 */ 149 case PM_SUSPEND_MEM: 150 /* 151 * Ensure that clocks are in a valid state. 152 */ 153 if (!at91_pm_verify_clocks()) 154 goto error; 155 156 at91_pm_suspend(state); 157 158 break; 159 160 /* 161 * STANDBY mode has *all* drivers suspended; ignores irqs not 162 * marked as 'wakeup' event sources; and reduces DRAM power. 163 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and 164 * nothing fancy done with main or cpu clocks. 165 */ 166 case PM_SUSPEND_STANDBY: 167 at91_pm_suspend(state); 168 break; 169 170 case PM_SUSPEND_ON: 171 cpu_do_idle(); 172 break; 173 174 default: 175 pr_debug("AT91: PM - bogus suspend state %d\n", state); 176 goto error; 177 } 178 179 error: 180 target_state = PM_SUSPEND_ON; 181 182 #ifdef CONFIG_PINCTRL_AT91 183 at91_pinctrl_gpio_resume(); 184 #endif 185 return 0; 186 } 187 188 /* 189 * Called right prior to thawing processes. 190 */ 191 static void at91_pm_end(void) 192 { 193 target_state = PM_SUSPEND_ON; 194 } 195 196 197 static const struct platform_suspend_ops at91_pm_ops = { 198 .valid = at91_pm_valid_state, 199 .begin = at91_pm_begin, 200 .enter = at91_pm_enter, 201 .end = at91_pm_end, 202 }; 203 204 static struct platform_device at91_cpuidle_device = { 205 .name = "cpuidle-at91", 206 }; 207 208 /* 209 * The AT91RM9200 goes into self-refresh mode with this command, and will 210 * terminate self-refresh automatically on the next SDRAM access. 211 * 212 * Self-refresh mode is exited as soon as a memory access is made, but we don't 213 * know for sure when that happens. However, we need to restore the low-power 214 * mode if it was enabled before going idle. Restoring low-power mode while 215 * still in self-refresh is "not recommended", but seems to work. 216 */ 217 static void at91rm9200_standby(void) 218 { 219 asm volatile( 220 "b 1f\n\t" 221 ".align 5\n\t" 222 "1: mcr p15, 0, %0, c7, c10, 4\n\t" 223 " str %2, [%1, %3]\n\t" 224 " mcr p15, 0, %0, c7, c0, 4\n\t" 225 : 226 : "r" (0), "r" (pm_data.ramc[0]), 227 "r" (1), "r" (AT91_MC_SDRAMC_SRR)); 228 } 229 230 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 231 * remember. 232 */ 233 static void at91_ddr_standby(void) 234 { 235 /* Those two values allow us to delay self-refresh activation 236 * to the maximum. */ 237 u32 lpr0, lpr1 = 0; 238 u32 mdr, saved_mdr0, saved_mdr1 = 0; 239 u32 saved_lpr0, saved_lpr1 = 0; 240 241 /* LPDDR1 --> force DDR2 mode during self-refresh */ 242 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); 243 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 244 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; 245 mdr |= AT91_DDRSDRC_MD_DDR2; 246 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); 247 } 248 249 if (pm_data.ramc[1]) { 250 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 251 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 252 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 253 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); 254 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { 255 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; 256 mdr |= AT91_DDRSDRC_MD_DDR2; 257 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); 258 } 259 } 260 261 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 262 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 263 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 264 265 /* self-refresh mode now */ 266 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 267 if (pm_data.ramc[1]) 268 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 269 270 cpu_do_idle(); 271 272 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); 273 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 274 if (pm_data.ramc[1]) { 275 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); 276 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 277 } 278 } 279 280 static void sama5d3_ddr_standby(void) 281 { 282 u32 lpr0; 283 u32 saved_lpr0; 284 285 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); 286 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; 287 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; 288 289 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 290 291 cpu_do_idle(); 292 293 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 294 } 295 296 /* We manage both DDRAM/SDRAM controllers, we need more than one value to 297 * remember. 298 */ 299 static void at91sam9_sdram_standby(void) 300 { 301 u32 lpr0, lpr1 = 0; 302 u32 saved_lpr0, saved_lpr1 = 0; 303 304 if (pm_data.ramc[1]) { 305 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 306 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 307 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 308 } 309 310 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); 311 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; 312 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 313 314 /* self-refresh mode now */ 315 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 316 if (pm_data.ramc[1]) 317 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 318 319 cpu_do_idle(); 320 321 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 322 if (pm_data.ramc[1]) 323 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 324 } 325 326 struct ramc_info { 327 void (*idle)(void); 328 unsigned int memctrl; 329 }; 330 331 static const struct ramc_info ramc_infos[] __initconst = { 332 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, 333 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, 334 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 335 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, 336 }; 337 338 static const struct of_device_id const ramc_ids[] __initconst = { 339 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, 340 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, 341 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, 342 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, 343 { /*sentinel*/ } 344 }; 345 346 static __init void at91_dt_ramc(void) 347 { 348 struct device_node *np; 349 const struct of_device_id *of_id; 350 int idx = 0; 351 void *standby = NULL; 352 const struct ramc_info *ramc; 353 354 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 355 pm_data.ramc[idx] = of_iomap(np, 0); 356 if (!pm_data.ramc[idx]) 357 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 358 359 ramc = of_id->data; 360 if (!standby) 361 standby = ramc->idle; 362 pm_data.memctrl = ramc->memctrl; 363 364 idx++; 365 } 366 367 if (!idx) 368 panic(pr_fmt("unable to find compatible ram controller node in dtb\n")); 369 370 if (!standby) { 371 pr_warn("ramc no standby function available\n"); 372 return; 373 } 374 375 at91_cpuidle_device.dev.platform_data = standby; 376 } 377 378 static void at91rm9200_idle(void) 379 { 380 /* 381 * Disable the processor clock. The processor will be automatically 382 * re-enabled by an interrupt or by a reset. 383 */ 384 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); 385 } 386 387 static void at91sam9_idle(void) 388 { 389 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR); 390 cpu_do_idle(); 391 } 392 393 static void __init at91_pm_sram_init(void) 394 { 395 struct gen_pool *sram_pool; 396 phys_addr_t sram_pbase; 397 unsigned long sram_base; 398 struct device_node *node; 399 struct platform_device *pdev = NULL; 400 401 for_each_compatible_node(node, NULL, "mmio-sram") { 402 pdev = of_find_device_by_node(node); 403 if (pdev) { 404 of_node_put(node); 405 break; 406 } 407 } 408 409 if (!pdev) { 410 pr_warn("%s: failed to find sram device!\n", __func__); 411 return; 412 } 413 414 sram_pool = gen_pool_get(&pdev->dev, NULL); 415 if (!sram_pool) { 416 pr_warn("%s: sram pool unavailable!\n", __func__); 417 return; 418 } 419 420 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); 421 if (!sram_base) { 422 pr_warn("%s: unable to alloc sram!\n", __func__); 423 return; 424 } 425 426 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 427 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, 428 at91_pm_suspend_in_sram_sz, false); 429 if (!at91_suspend_sram_fn) { 430 pr_warn("SRAM: Could not map\n"); 431 return; 432 } 433 434 /* Copy the pm suspend handler to SRAM */ 435 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, 436 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); 437 } 438 439 struct pmc_info { 440 unsigned long uhp_udp_mask; 441 }; 442 443 static const struct pmc_info pmc_infos[] __initconst = { 444 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP }, 445 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP }, 446 { .uhp_udp_mask = AT91SAM926x_PMC_UHP }, 447 }; 448 449 static const struct of_device_id atmel_pmc_ids[] __initconst = { 450 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, 451 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, 452 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, 453 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, 454 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, 455 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, 456 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, 457 { /* sentinel */ }, 458 }; 459 460 static void __init at91_pm_init(void (*pm_idle)(void)) 461 { 462 struct device_node *pmc_np; 463 const struct of_device_id *of_id; 464 const struct pmc_info *pmc; 465 466 if (at91_cpuidle_device.dev.platform_data) 467 platform_device_register(&at91_cpuidle_device); 468 469 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); 470 pm_data.pmc = of_iomap(pmc_np, 0); 471 if (!pm_data.pmc) { 472 pr_err("AT91: PM not supported, PMC not found\n"); 473 return; 474 } 475 476 pmc = of_id->data; 477 pm_data.uhp_udp_mask = pmc->uhp_udp_mask; 478 479 if (pm_idle) 480 arm_pm_idle = pm_idle; 481 482 at91_pm_sram_init(); 483 484 if (at91_suspend_sram_fn) 485 suspend_set_ops(&at91_pm_ops); 486 else 487 pr_info("AT91: PM not supported, due to no SRAM allocated\n"); 488 } 489 490 void __init at91rm9200_pm_init(void) 491 { 492 at91_dt_ramc(); 493 494 /* 495 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 496 */ 497 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 498 499 at91_pm_init(at91rm9200_idle); 500 } 501 502 void __init at91sam9_pm_init(void) 503 { 504 at91_dt_ramc(); 505 at91_pm_init(at91sam9_idle); 506 } 507 508 void __init sama5_pm_init(void) 509 { 510 at91_dt_ramc(); 511 at91_pm_init(NULL); 512 } 513