1 /* 2 * arch/arm/mach-at91/at91rm9200.c 3 * 4 * Copyright (C) 2005 SAN People 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 */ 12 13 #include <linux/module.h> 14 15 #include <asm/mach/arch.h> 16 #include <asm/mach/map.h> 17 #include <asm/arch/at91rm9200.h> 18 #include <asm/arch/at91_pmc.h> 19 #include <asm/arch/at91_st.h> 20 21 #include "generic.h" 22 #include "clock.h" 23 24 static struct map_desc at91rm9200_io_desc[] __initdata = { 25 { 26 .virtual = AT91_VA_BASE_SYS, 27 .pfn = __phys_to_pfn(AT91_BASE_SYS), 28 .length = SZ_4K, 29 .type = MT_DEVICE, 30 }, { 31 .virtual = AT91_VA_BASE_EMAC, 32 .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), 33 .length = SZ_16K, 34 .type = MT_DEVICE, 35 }, { 36 .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE, 37 .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), 38 .length = AT91RM9200_SRAM_SIZE, 39 .type = MT_DEVICE, 40 }, 41 }; 42 43 /* -------------------------------------------------------------------- 44 * Clocks 45 * -------------------------------------------------------------------- */ 46 47 /* 48 * The peripheral clocks. 49 */ 50 static struct clk udc_clk = { 51 .name = "udc_clk", 52 .pmc_mask = 1 << AT91RM9200_ID_UDP, 53 .type = CLK_TYPE_PERIPHERAL, 54 }; 55 static struct clk ohci_clk = { 56 .name = "ohci_clk", 57 .pmc_mask = 1 << AT91RM9200_ID_UHP, 58 .type = CLK_TYPE_PERIPHERAL, 59 }; 60 static struct clk ether_clk = { 61 .name = "ether_clk", 62 .pmc_mask = 1 << AT91RM9200_ID_EMAC, 63 .type = CLK_TYPE_PERIPHERAL, 64 }; 65 static struct clk mmc_clk = { 66 .name = "mci_clk", 67 .pmc_mask = 1 << AT91RM9200_ID_MCI, 68 .type = CLK_TYPE_PERIPHERAL, 69 }; 70 static struct clk twi_clk = { 71 .name = "twi_clk", 72 .pmc_mask = 1 << AT91RM9200_ID_TWI, 73 .type = CLK_TYPE_PERIPHERAL, 74 }; 75 static struct clk usart0_clk = { 76 .name = "usart0_clk", 77 .pmc_mask = 1 << AT91RM9200_ID_US0, 78 .type = CLK_TYPE_PERIPHERAL, 79 }; 80 static struct clk usart1_clk = { 81 .name = "usart1_clk", 82 .pmc_mask = 1 << AT91RM9200_ID_US1, 83 .type = CLK_TYPE_PERIPHERAL, 84 }; 85 static struct clk usart2_clk = { 86 .name = "usart2_clk", 87 .pmc_mask = 1 << AT91RM9200_ID_US2, 88 .type = CLK_TYPE_PERIPHERAL, 89 }; 90 static struct clk usart3_clk = { 91 .name = "usart3_clk", 92 .pmc_mask = 1 << AT91RM9200_ID_US3, 93 .type = CLK_TYPE_PERIPHERAL, 94 }; 95 static struct clk spi_clk = { 96 .name = "spi_clk", 97 .pmc_mask = 1 << AT91RM9200_ID_SPI, 98 .type = CLK_TYPE_PERIPHERAL, 99 }; 100 static struct clk pioA_clk = { 101 .name = "pioA_clk", 102 .pmc_mask = 1 << AT91RM9200_ID_PIOA, 103 .type = CLK_TYPE_PERIPHERAL, 104 }; 105 static struct clk pioB_clk = { 106 .name = "pioB_clk", 107 .pmc_mask = 1 << AT91RM9200_ID_PIOB, 108 .type = CLK_TYPE_PERIPHERAL, 109 }; 110 static struct clk pioC_clk = { 111 .name = "pioC_clk", 112 .pmc_mask = 1 << AT91RM9200_ID_PIOC, 113 .type = CLK_TYPE_PERIPHERAL, 114 }; 115 static struct clk pioD_clk = { 116 .name = "pioD_clk", 117 .pmc_mask = 1 << AT91RM9200_ID_PIOD, 118 .type = CLK_TYPE_PERIPHERAL, 119 }; 120 static struct clk tc0_clk = { 121 .name = "tc0_clk", 122 .pmc_mask = 1 << AT91RM9200_ID_TC0, 123 .type = CLK_TYPE_PERIPHERAL, 124 }; 125 static struct clk tc1_clk = { 126 .name = "tc1_clk", 127 .pmc_mask = 1 << AT91RM9200_ID_TC1, 128 .type = CLK_TYPE_PERIPHERAL, 129 }; 130 static struct clk tc2_clk = { 131 .name = "tc2_clk", 132 .pmc_mask = 1 << AT91RM9200_ID_TC2, 133 .type = CLK_TYPE_PERIPHERAL, 134 }; 135 static struct clk tc3_clk = { 136 .name = "tc3_clk", 137 .pmc_mask = 1 << AT91RM9200_ID_TC3, 138 .type = CLK_TYPE_PERIPHERAL, 139 }; 140 static struct clk tc4_clk = { 141 .name = "tc4_clk", 142 .pmc_mask = 1 << AT91RM9200_ID_TC4, 143 .type = CLK_TYPE_PERIPHERAL, 144 }; 145 static struct clk tc5_clk = { 146 .name = "tc5_clk", 147 .pmc_mask = 1 << AT91RM9200_ID_TC5, 148 .type = CLK_TYPE_PERIPHERAL, 149 }; 150 151 static struct clk *periph_clocks[] __initdata = { 152 &pioA_clk, 153 &pioB_clk, 154 &pioC_clk, 155 &pioD_clk, 156 &usart0_clk, 157 &usart1_clk, 158 &usart2_clk, 159 &usart3_clk, 160 &mmc_clk, 161 &udc_clk, 162 &twi_clk, 163 &spi_clk, 164 // ssc 0 .. ssc2 165 &tc0_clk, 166 &tc1_clk, 167 &tc2_clk, 168 &tc3_clk, 169 &tc4_clk, 170 &tc5_clk, 171 &ohci_clk, 172 ðer_clk, 173 // irq0 .. irq6 174 }; 175 176 /* 177 * The four programmable clocks. 178 * You must configure pin multiplexing to bring these signals out. 179 */ 180 static struct clk pck0 = { 181 .name = "pck0", 182 .pmc_mask = AT91_PMC_PCK0, 183 .type = CLK_TYPE_PROGRAMMABLE, 184 .id = 0, 185 }; 186 static struct clk pck1 = { 187 .name = "pck1", 188 .pmc_mask = AT91_PMC_PCK1, 189 .type = CLK_TYPE_PROGRAMMABLE, 190 .id = 1, 191 }; 192 static struct clk pck2 = { 193 .name = "pck2", 194 .pmc_mask = AT91_PMC_PCK2, 195 .type = CLK_TYPE_PROGRAMMABLE, 196 .id = 2, 197 }; 198 static struct clk pck3 = { 199 .name = "pck3", 200 .pmc_mask = AT91_PMC_PCK3, 201 .type = CLK_TYPE_PROGRAMMABLE, 202 .id = 3, 203 }; 204 205 static void __init at91rm9200_register_clocks(void) 206 { 207 int i; 208 209 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) 210 clk_register(periph_clocks[i]); 211 212 clk_register(&pck0); 213 clk_register(&pck1); 214 clk_register(&pck2); 215 clk_register(&pck3); 216 } 217 218 /* -------------------------------------------------------------------- 219 * GPIO 220 * -------------------------------------------------------------------- */ 221 222 static struct at91_gpio_bank at91rm9200_gpio[] = { 223 { 224 .id = AT91RM9200_ID_PIOA, 225 .offset = AT91_PIOA, 226 .clock = &pioA_clk, 227 }, { 228 .id = AT91RM9200_ID_PIOB, 229 .offset = AT91_PIOB, 230 .clock = &pioB_clk, 231 }, { 232 .id = AT91RM9200_ID_PIOC, 233 .offset = AT91_PIOC, 234 .clock = &pioC_clk, 235 }, { 236 .id = AT91RM9200_ID_PIOD, 237 .offset = AT91_PIOD, 238 .clock = &pioD_clk, 239 } 240 }; 241 242 static void at91rm9200_reset(void) 243 { 244 /* 245 * Perform a hardware reset with the use of the Watchdog timer. 246 */ 247 at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); 248 at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); 249 } 250 251 252 /* -------------------------------------------------------------------- 253 * AT91RM9200 processor initialization 254 * -------------------------------------------------------------------- */ 255 void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) 256 { 257 /* Map peripherals */ 258 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); 259 260 at91_arch_reset = at91rm9200_reset; 261 at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) 262 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) 263 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) 264 | (1 << AT91RM9200_ID_IRQ6); 265 266 /* Init clock subsystem */ 267 at91_clock_init(main_clock); 268 269 /* Register the processor-specific clocks */ 270 at91rm9200_register_clocks(); 271 272 /* Initialize GPIO subsystem */ 273 at91_gpio_init(at91rm9200_gpio, banks); 274 } 275 276 277 /* -------------------------------------------------------------------- 278 * Interrupt initialization 279 * -------------------------------------------------------------------- */ 280 281 /* 282 * The default interrupt priority levels (0 = lowest, 7 = highest). 283 */ 284 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 285 7, /* Advanced Interrupt Controller (FIQ) */ 286 7, /* System Peripherals */ 287 0, /* Parallel IO Controller A */ 288 0, /* Parallel IO Controller B */ 289 0, /* Parallel IO Controller C */ 290 0, /* Parallel IO Controller D */ 291 6, /* USART 0 */ 292 6, /* USART 1 */ 293 6, /* USART 2 */ 294 6, /* USART 3 */ 295 0, /* Multimedia Card Interface */ 296 4, /* USB Device Port */ 297 0, /* Two-Wire Interface */ 298 6, /* Serial Peripheral Interface */ 299 5, /* Serial Synchronous Controller 0 */ 300 5, /* Serial Synchronous Controller 1 */ 301 5, /* Serial Synchronous Controller 2 */ 302 0, /* Timer Counter 0 */ 303 0, /* Timer Counter 1 */ 304 0, /* Timer Counter 2 */ 305 0, /* Timer Counter 3 */ 306 0, /* Timer Counter 4 */ 307 0, /* Timer Counter 5 */ 308 3, /* USB Host port */ 309 3, /* Ethernet MAC */ 310 0, /* Advanced Interrupt Controller (IRQ0) */ 311 0, /* Advanced Interrupt Controller (IRQ1) */ 312 0, /* Advanced Interrupt Controller (IRQ2) */ 313 0, /* Advanced Interrupt Controller (IRQ3) */ 314 0, /* Advanced Interrupt Controller (IRQ4) */ 315 0, /* Advanced Interrupt Controller (IRQ5) */ 316 0 /* Advanced Interrupt Controller (IRQ6) */ 317 }; 318 319 void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS]) 320 { 321 if (!priority) 322 priority = at91rm9200_default_irq_priority; 323 324 /* Initialize the AIC interrupt controller */ 325 at91_aic_init(priority); 326 327 /* Enable GPIO interrupts */ 328 at91_gpio_irq_setup(); 329 } 330