1*d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2080fc66fSRussell King/* 3080fc66fSRussell King * linux/arch/arm/lib/io-writesw-armv3.S 4080fc66fSRussell King * 5080fc66fSRussell King * Copyright (C) 1995-2000 Russell King 6080fc66fSRussell King */ 7080fc66fSRussell King#include <linux/linkage.h> 8080fc66fSRussell King#include <asm/assembler.h> 9080fc66fSRussell King 10080fc66fSRussell King.Loutsw_bad_alignment: 11080fc66fSRussell King adr r0, .Loutsw_bad_align_msg 12080fc66fSRussell King mov r2, lr 13080fc66fSRussell King b panic 14080fc66fSRussell King.Loutsw_bad_align_msg: 15080fc66fSRussell King .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" 16080fc66fSRussell King .align 17080fc66fSRussell King 18080fc66fSRussell King.Loutsw_align: tst r1, #1 19080fc66fSRussell King bne .Loutsw_bad_alignment 20080fc66fSRussell King 21080fc66fSRussell King add r1, r1, #2 22080fc66fSRussell King 23080fc66fSRussell King ldr r3, [r1, #-4] 24080fc66fSRussell King mov r3, r3, lsr #16 25080fc66fSRussell King orr r3, r3, r3, lsl #16 26080fc66fSRussell King str r3, [r0] 27080fc66fSRussell King subs r2, r2, #1 286ebbf2ceSRussell King reteq lr 29080fc66fSRussell King 30080fc66fSRussell KingENTRY(__raw_writesw) 31080fc66fSRussell King teq r2, #0 @ do we have to check for the zero len? 326ebbf2ceSRussell King reteq lr 33080fc66fSRussell King tst r1, #3 34080fc66fSRussell King bne .Loutsw_align 35080fc66fSRussell King 36080fc66fSRussell King stmfd sp!, {r4, r5, r6, lr} 37080fc66fSRussell King 38080fc66fSRussell King subs r2, r2, #8 39080fc66fSRussell King bmi .Lno_outsw_8 40080fc66fSRussell King 41080fc66fSRussell King.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6} 42080fc66fSRussell King 43080fc66fSRussell King mov ip, r3, lsl #16 44080fc66fSRussell King orr ip, ip, ip, lsr #16 45080fc66fSRussell King str ip, [r0] 46080fc66fSRussell King 47080fc66fSRussell King mov ip, r3, lsr #16 48080fc66fSRussell King orr ip, ip, ip, lsl #16 49080fc66fSRussell King str ip, [r0] 50080fc66fSRussell King 51080fc66fSRussell King mov ip, r4, lsl #16 52080fc66fSRussell King orr ip, ip, ip, lsr #16 53080fc66fSRussell King str ip, [r0] 54080fc66fSRussell King 55080fc66fSRussell King mov ip, r4, lsr #16 56080fc66fSRussell King orr ip, ip, ip, lsl #16 57080fc66fSRussell King str ip, [r0] 58080fc66fSRussell King 59080fc66fSRussell King mov ip, r5, lsl #16 60080fc66fSRussell King orr ip, ip, ip, lsr #16 61080fc66fSRussell King str ip, [r0] 62080fc66fSRussell King 63080fc66fSRussell King mov ip, r5, lsr #16 64080fc66fSRussell King orr ip, ip, ip, lsl #16 65080fc66fSRussell King str ip, [r0] 66080fc66fSRussell King 67080fc66fSRussell King mov ip, r6, lsl #16 68080fc66fSRussell King orr ip, ip, ip, lsr #16 69080fc66fSRussell King str ip, [r0] 70080fc66fSRussell King 71080fc66fSRussell King mov ip, r6, lsr #16 72080fc66fSRussell King orr ip, ip, ip, lsl #16 73080fc66fSRussell King str ip, [r0] 74080fc66fSRussell King 75080fc66fSRussell King subs r2, r2, #8 76080fc66fSRussell King bpl .Loutsw_8_lp 77080fc66fSRussell King 78080fc66fSRussell King tst r2, #7 79e44fc388SStefan Agner ldmfdeq sp!, {r4, r5, r6, pc} 80080fc66fSRussell King 81080fc66fSRussell King.Lno_outsw_8: tst r2, #4 82080fc66fSRussell King beq .Lno_outsw_4 83080fc66fSRussell King 84080fc66fSRussell King ldmia r1!, {r3, r4} 85080fc66fSRussell King 86080fc66fSRussell King mov ip, r3, lsl #16 87080fc66fSRussell King orr ip, ip, ip, lsr #16 88080fc66fSRussell King str ip, [r0] 89080fc66fSRussell King 90080fc66fSRussell King mov ip, r3, lsr #16 91080fc66fSRussell King orr ip, ip, ip, lsl #16 92080fc66fSRussell King str ip, [r0] 93080fc66fSRussell King 94080fc66fSRussell King mov ip, r4, lsl #16 95080fc66fSRussell King orr ip, ip, ip, lsr #16 96080fc66fSRussell King str ip, [r0] 97080fc66fSRussell King 98080fc66fSRussell King mov ip, r4, lsr #16 99080fc66fSRussell King orr ip, ip, ip, lsl #16 100080fc66fSRussell King str ip, [r0] 101080fc66fSRussell King 102080fc66fSRussell King.Lno_outsw_4: tst r2, #2 103080fc66fSRussell King beq .Lno_outsw_2 104080fc66fSRussell King 105080fc66fSRussell King ldr r3, [r1], #4 106080fc66fSRussell King 107080fc66fSRussell King mov ip, r3, lsl #16 108080fc66fSRussell King orr ip, ip, ip, lsr #16 109080fc66fSRussell King str ip, [r0] 110080fc66fSRussell King 111080fc66fSRussell King mov ip, r3, lsr #16 112080fc66fSRussell King orr ip, ip, ip, lsl #16 113080fc66fSRussell King str ip, [r0] 114080fc66fSRussell King 115080fc66fSRussell King.Lno_outsw_2: tst r2, #1 116080fc66fSRussell King 117080fc66fSRussell King ldrne r3, [r1] 118080fc66fSRussell King 119080fc66fSRussell King movne ip, r3, lsl #16 120080fc66fSRussell King orrne ip, ip, ip, lsr #16 121080fc66fSRussell King strne ip, [r0] 122080fc66fSRussell King 123080fc66fSRussell King ldmfd sp!, {r4, r5, r6, pc} 124