1*d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2080fc66fSRussell King/* 3080fc66fSRussell King * linux/arch/arm/lib/io-readsw-armv3.S 4080fc66fSRussell King * 5080fc66fSRussell King * Copyright (C) 1995-2000 Russell King 6080fc66fSRussell King */ 7080fc66fSRussell King#include <linux/linkage.h> 8080fc66fSRussell King#include <asm/assembler.h> 9080fc66fSRussell King 10080fc66fSRussell King.Linsw_bad_alignment: 11080fc66fSRussell King adr r0, .Linsw_bad_align_msg 12080fc66fSRussell King mov r2, lr 13080fc66fSRussell King b panic 14080fc66fSRussell King.Linsw_bad_align_msg: 15080fc66fSRussell King .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" 16080fc66fSRussell King .align 17080fc66fSRussell King 18080fc66fSRussell King.Linsw_align: tst r1, #1 19080fc66fSRussell King bne .Linsw_bad_alignment 20080fc66fSRussell King 21080fc66fSRussell King ldr r3, [r0] 22080fc66fSRussell King strb r3, [r1], #1 23080fc66fSRussell King mov r3, r3, lsr #8 24080fc66fSRussell King strb r3, [r1], #1 25080fc66fSRussell King 26080fc66fSRussell King subs r2, r2, #1 276ebbf2ceSRussell King reteq lr 28080fc66fSRussell King 29080fc66fSRussell KingENTRY(__raw_readsw) 30080fc66fSRussell King teq r2, #0 @ do we have to check for the zero len? 316ebbf2ceSRussell King reteq lr 32080fc66fSRussell King tst r1, #3 33080fc66fSRussell King bne .Linsw_align 34080fc66fSRussell King 35080fc66fSRussell King.Linsw_aligned: mov ip, #0xff 36080fc66fSRussell King orr ip, ip, ip, lsl #8 37080fc66fSRussell King stmfd sp!, {r4, r5, r6, lr} 38080fc66fSRussell King 39080fc66fSRussell King subs r2, r2, #8 40080fc66fSRussell King bmi .Lno_insw_8 41080fc66fSRussell King 42080fc66fSRussell King.Linsw_8_lp: ldr r3, [r0] 43080fc66fSRussell King and r3, r3, ip 44080fc66fSRussell King ldr r4, [r0] 45080fc66fSRussell King orr r3, r3, r4, lsl #16 46080fc66fSRussell King 47080fc66fSRussell King ldr r4, [r0] 48080fc66fSRussell King and r4, r4, ip 49080fc66fSRussell King ldr r5, [r0] 50080fc66fSRussell King orr r4, r4, r5, lsl #16 51080fc66fSRussell King 52080fc66fSRussell King ldr r5, [r0] 53080fc66fSRussell King and r5, r5, ip 54080fc66fSRussell King ldr r6, [r0] 55080fc66fSRussell King orr r5, r5, r6, lsl #16 56080fc66fSRussell King 57080fc66fSRussell King ldr r6, [r0] 58080fc66fSRussell King and r6, r6, ip 59080fc66fSRussell King ldr lr, [r0] 60080fc66fSRussell King orr r6, r6, lr, lsl #16 61080fc66fSRussell King 62080fc66fSRussell King stmia r1!, {r3 - r6} 63080fc66fSRussell King 64080fc66fSRussell King subs r2, r2, #8 65080fc66fSRussell King bpl .Linsw_8_lp 66080fc66fSRussell King 67080fc66fSRussell King tst r2, #7 68e44fc388SStefan Agner ldmfdeq sp!, {r4, r5, r6, pc} 69080fc66fSRussell King 70080fc66fSRussell King.Lno_insw_8: tst r2, #4 71080fc66fSRussell King beq .Lno_insw_4 72080fc66fSRussell King 73080fc66fSRussell King ldr r3, [r0] 74080fc66fSRussell King and r3, r3, ip 75080fc66fSRussell King ldr r4, [r0] 76080fc66fSRussell King orr r3, r3, r4, lsl #16 77080fc66fSRussell King 78080fc66fSRussell King ldr r4, [r0] 79080fc66fSRussell King and r4, r4, ip 80080fc66fSRussell King ldr r5, [r0] 81080fc66fSRussell King orr r4, r4, r5, lsl #16 82080fc66fSRussell King 83080fc66fSRussell King stmia r1!, {r3, r4} 84080fc66fSRussell King 85080fc66fSRussell King.Lno_insw_4: tst r2, #2 86080fc66fSRussell King beq .Lno_insw_2 87080fc66fSRussell King 88080fc66fSRussell King ldr r3, [r0] 89080fc66fSRussell King and r3, r3, ip 90080fc66fSRussell King ldr r4, [r0] 91080fc66fSRussell King orr r3, r3, r4, lsl #16 92080fc66fSRussell King 93080fc66fSRussell King str r3, [r1], #4 94080fc66fSRussell King 95080fc66fSRussell King.Lno_insw_2: tst r2, #1 96080fc66fSRussell King ldrne r3, [r0] 97e44fc388SStefan Agner strbne r3, [r1], #1 98080fc66fSRussell King movne r3, r3, lsr #8 99e44fc388SStefan Agner strbne r3, [r1] 100080fc66fSRussell King 101080fc66fSRussell King ldmfd sp!, {r4, r5, r6, pc} 102080fc66fSRussell King 1038478132aSRussell King 104