xref: /linux/arch/arm/kernel/opcodes.c (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20c9030deSLeif Lindholm /*
30c9030deSLeif Lindholm  *  linux/arch/arm/kernel/opcodes.c
40c9030deSLeif Lindholm  *
50c9030deSLeif Lindholm  *  A32 condition code lookup feature moved from nwfpe/fpopcode.c
60c9030deSLeif Lindholm  */
70c9030deSLeif Lindholm 
80c9030deSLeif Lindholm #include <linux/module.h>
90c9030deSLeif Lindholm #include <asm/opcodes.h>
100c9030deSLeif Lindholm 
110c9030deSLeif Lindholm #define ARM_OPCODE_CONDITION_UNCOND 0xf
120c9030deSLeif Lindholm 
130c9030deSLeif Lindholm /*
140c9030deSLeif Lindholm  * condition code lookup table
150c9030deSLeif Lindholm  * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
160c9030deSLeif Lindholm  *
170c9030deSLeif Lindholm  * bit position in short is condition code: NZCV
180c9030deSLeif Lindholm  */
190c9030deSLeif Lindholm static const unsigned short cc_map[16] = {
200c9030deSLeif Lindholm 	0xF0F0,			/* EQ == Z set            */
210c9030deSLeif Lindholm 	0x0F0F,			/* NE                     */
220c9030deSLeif Lindholm 	0xCCCC,			/* CS == C set            */
230c9030deSLeif Lindholm 	0x3333,			/* CC                     */
240c9030deSLeif Lindholm 	0xFF00,			/* MI == N set            */
250c9030deSLeif Lindholm 	0x00FF,			/* PL                     */
260c9030deSLeif Lindholm 	0xAAAA,			/* VS == V set            */
270c9030deSLeif Lindholm 	0x5555,			/* VC                     */
280c9030deSLeif Lindholm 	0x0C0C,			/* HI == C set && Z clear */
290c9030deSLeif Lindholm 	0xF3F3,			/* LS == C clear || Z set */
300c9030deSLeif Lindholm 	0xAA55,			/* GE == (N==V)           */
310c9030deSLeif Lindholm 	0x55AA,			/* LT == (N!=V)           */
320c9030deSLeif Lindholm 	0x0A05,			/* GT == (!Z && (N==V))   */
330c9030deSLeif Lindholm 	0xF5FA,			/* LE == (Z || (N!=V))    */
340c9030deSLeif Lindholm 	0xFFFF,			/* AL always              */
350c9030deSLeif Lindholm 	0			/* NV                     */
360c9030deSLeif Lindholm };
370c9030deSLeif Lindholm 
380c9030deSLeif Lindholm /*
390c9030deSLeif Lindholm  * Returns:
400c9030deSLeif Lindholm  * ARM_OPCODE_CONDTEST_FAIL   - if condition fails
410c9030deSLeif Lindholm  * ARM_OPCODE_CONDTEST_PASS   - if condition passes (including AL)
420c9030deSLeif Lindholm  * ARM_OPCODE_CONDTEST_UNCOND - if NV condition, or separate unconditional
430c9030deSLeif Lindholm  *                              opcode space from v5 onwards
440c9030deSLeif Lindholm  *
450c9030deSLeif Lindholm  * Code that tests whether a conditional instruction would pass its condition
460c9030deSLeif Lindholm  * check should check that return value == ARM_OPCODE_CONDTEST_PASS.
470c9030deSLeif Lindholm  *
480c9030deSLeif Lindholm  * Code that tests if a condition means that the instruction would be executed
490c9030deSLeif Lindholm  * (regardless of conditional or unconditional) should instead check that the
500c9030deSLeif Lindholm  * return value != ARM_OPCODE_CONDTEST_FAIL.
510c9030deSLeif Lindholm  */
arm_check_condition(u32 opcode,u32 psr)520c9030deSLeif Lindholm asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr)
530c9030deSLeif Lindholm {
540c9030deSLeif Lindholm 	u32 cc_bits  = opcode >> 28;
550c9030deSLeif Lindholm 	u32 psr_cond = psr >> 28;
560c9030deSLeif Lindholm 	unsigned int ret;
570c9030deSLeif Lindholm 
580c9030deSLeif Lindholm 	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
590c9030deSLeif Lindholm 		if ((cc_map[cc_bits] >> (psr_cond)) & 1)
600c9030deSLeif Lindholm 			ret = ARM_OPCODE_CONDTEST_PASS;
610c9030deSLeif Lindholm 		else
620c9030deSLeif Lindholm 			ret = ARM_OPCODE_CONDTEST_FAIL;
630c9030deSLeif Lindholm 	} else {
640c9030deSLeif Lindholm 		ret = ARM_OPCODE_CONDTEST_UNCOND;
650c9030deSLeif Lindholm 	}
660c9030deSLeif Lindholm 
670c9030deSLeif Lindholm 	return ret;
680c9030deSLeif Lindholm }
690c9030deSLeif Lindholm EXPORT_SYMBOL_GPL(arm_check_condition);
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