1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/config.h> 15#include <linux/linkage.h> 16#include <linux/init.h> 17 18#include <asm/assembler.h> 19#include <asm/domain.h> 20#include <asm/procinfo.h> 21#include <asm/ptrace.h> 22#include <asm/asm-offsets.h> 23#include <asm/memory.h> 24#include <asm/thread_info.h> 25#include <asm/system.h> 26 27#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) 28 29/* 30 * swapper_pg_dir is the virtual address of the initial page table. 31 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must 32 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect 33 * the least significant 16 bits to be 0x8000, but we could probably 34 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000. 35 */ 36#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000 37#error KERNEL_RAM_ADDR must start at 0xXXXX8000 38#endif 39 40 .globl swapper_pg_dir 41 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000 42 43 .macro pgtbl, rd 44 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000)) 45 .endm 46 47#ifdef CONFIG_XIP_KERNEL 48#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 49#else 50#define TEXTADDR KERNEL_RAM_ADDR 51#endif 52 53/* 54 * Kernel startup entry point. 55 * --------------------------- 56 * 57 * This is normally called from the decompressor code. The requirements 58 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 59 * r1 = machine nr. 60 * 61 * This code is mostly position independent, so if you link the kernel at 62 * 0xc0008000, you call this at __pa(0xc0008000). 63 * 64 * See linux/arch/arm/tools/mach-types for the complete list of machine 65 * numbers for r1. 66 * 67 * We're trying to keep crap to a minimum; DO NOT add any machine specific 68 * crap here - that's what the boot loader (or in extreme, well justified 69 * circumstances, zImage) is for. 70 */ 71 __INIT 72 .type stext, %function 73ENTRY(stext) 74 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode 75 @ and irqs disabled 76 mrc p15, 0, r9, c0, c0 @ get processor id 77 bl __lookup_processor_type @ r5=procinfo r9=cpuid 78 movs r10, r5 @ invalid processor (r5=0)? 79 beq __error_p @ yes, error 'p' 80 bl __lookup_machine_type @ r5=machinfo 81 movs r8, r5 @ invalid machine (r5=0)? 82 beq __error_a @ yes, error 'a' 83 bl __create_page_tables 84 85 /* 86 * The following calls CPU specific code in a position independent 87 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 88 * xxx_proc_info structure selected by __lookup_machine_type 89 * above. On return, the CPU will be ready for the MMU to be 90 * turned on, and r0 will hold the CPU control register value. 91 */ 92 ldr r13, __switch_data @ address to jump to after 93 @ mmu has been enabled 94 adr lr, __enable_mmu @ return (PIC) address 95 add pc, r10, #PROCINFO_INITFUNC 96 97#if defined(CONFIG_SMP) 98 .type secondary_startup, #function 99ENTRY(secondary_startup) 100 /* 101 * Common entry point for secondary CPUs. 102 * 103 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 104 * the processor type - there is no need to check the machine type 105 * as it has already been validated by the primary processor. 106 */ 107 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC 108 mrc p15, 0, r9, c0, c0 @ get processor id 109 bl __lookup_processor_type 110 movs r10, r5 @ invalid processor? 111 moveq r0, #'p' @ yes, error 'p' 112 beq __error 113 114 /* 115 * Use the page tables supplied from __cpu_up. 116 */ 117 adr r4, __secondary_data 118 ldmia r4, {r5, r6, r13} @ address to jump to after 119 sub r4, r4, r5 @ mmu has been enabled 120 ldr r4, [r6, r4] @ get secondary_data.pgdir 121 adr lr, __enable_mmu @ return address 122 add pc, r10, #12 @ initialise processor 123 @ (return control reg) 124 125 /* 126 * r6 = &secondary_data 127 */ 128ENTRY(__secondary_switched) 129 ldr sp, [r6, #4] @ get secondary_data.stack 130 mov fp, #0 131 b secondary_start_kernel 132 133 .type __secondary_data, %object 134__secondary_data: 135 .long . 136 .long secondary_data 137 .long __secondary_switched 138#endif /* defined(CONFIG_SMP) */ 139 140 141 142/* 143 * Setup common bits before finally enabling the MMU. Essentially 144 * this is just loading the page table pointer and domain access 145 * registers. 146 */ 147 .type __enable_mmu, %function 148__enable_mmu: 149#ifdef CONFIG_ALIGNMENT_TRAP 150 orr r0, r0, #CR_A 151#else 152 bic r0, r0, #CR_A 153#endif 154#ifdef CONFIG_CPU_DCACHE_DISABLE 155 bic r0, r0, #CR_C 156#endif 157#ifdef CONFIG_CPU_BPREDICT_DISABLE 158 bic r0, r0, #CR_Z 159#endif 160#ifdef CONFIG_CPU_ICACHE_DISABLE 161 bic r0, r0, #CR_I 162#endif 163 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 164 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 165 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 166 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 167 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 168 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 169 b __turn_mmu_on 170 171/* 172 * Enable the MMU. This completely changes the structure of the visible 173 * memory space. You will not be able to trace execution through this. 174 * If you have an enquiry about this, *please* check the linux-arm-kernel 175 * mailing list archives BEFORE sending another post to the list. 176 * 177 * r0 = cp#15 control register 178 * r13 = *virtual* address to jump to upon completion 179 * 180 * other registers depend on the function called upon completion 181 */ 182 .align 5 183 .type __turn_mmu_on, %function 184__turn_mmu_on: 185 mov r0, r0 186 mcr p15, 0, r0, c1, c0, 0 @ write control reg 187 mrc p15, 0, r3, c0, c0, 0 @ read id reg 188 mov r3, r3 189 mov r3, r3 190 mov pc, r13 191 192 193 194/* 195 * Setup the initial page tables. We only setup the barest 196 * amount which are required to get the kernel running, which 197 * generally means mapping in the kernel code. 198 * 199 * r8 = machinfo 200 * r9 = cpuid 201 * r10 = procinfo 202 * 203 * Returns: 204 * r0, r3, r6, r7 corrupted 205 * r4 = physical page table address 206 */ 207 .type __create_page_tables, %function 208__create_page_tables: 209 pgtbl r4 @ page table address 210 211 /* 212 * Clear the 16K level 1 swapper page table 213 */ 214 mov r0, r4 215 mov r3, #0 216 add r6, r0, #0x4000 2171: str r3, [r0], #4 218 str r3, [r0], #4 219 str r3, [r0], #4 220 str r3, [r0], #4 221 teq r0, r6 222 bne 1b 223 224 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags 225 226 /* 227 * Create identity mapping for first MB of kernel to 228 * cater for the MMU enable. This identity mapping 229 * will be removed by paging_init(). We use our current program 230 * counter to determine corresponding section base address. 231 */ 232 mov r6, pc, lsr #20 @ start of kernel section 233 orr r3, r7, r6, lsl #20 @ flags + kernel base 234 str r3, [r4, r6, lsl #2] @ identity mapping 235 236 /* 237 * Now setup the pagetables for our kernel direct 238 * mapped region. We round TEXTADDR down to the 239 * nearest megabyte boundary. It is assumed that 240 * the kernel fits within 4 contigous 1MB sections. 241 */ 242 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel 243 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]! 244 add r3, r3, #1 << 20 245 str r3, [r0, #4]! @ KERNEL + 1MB 246 add r3, r3, #1 << 20 247 str r3, [r0, #4]! @ KERNEL + 2MB 248 add r3, r3, #1 << 20 249 str r3, [r0, #4] @ KERNEL + 3MB 250 251 /* 252 * Then map first 1MB of ram in case it contains our boot params. 253 */ 254 add r0, r4, #PAGE_OFFSET >> 18 255 orr r6, r7, #PHYS_OFFSET 256 str r6, [r0] 257 258#ifdef CONFIG_XIP_KERNEL 259 /* 260 * Map some ram to cover our .data and .bss areas. 261 * Mapping 3MB should be plenty. 262 */ 263 sub r3, r4, #PHYS_OFFSET 264 mov r3, r3, lsr #20 265 add r0, r0, r3, lsl #2 266 add r6, r6, r3, lsl #20 267 str r6, [r0], #4 268 add r6, r6, #(1 << 20) 269 str r6, [r0], #4 270 add r6, r6, #(1 << 20) 271 str r6, [r0] 272#endif 273 274#ifdef CONFIG_DEBUG_LL 275 bic r7, r7, #0x0c @ turn off cacheable 276 @ and bufferable bits 277 /* 278 * Map in IO space for serial debugging. 279 * This allows debug messages to be output 280 * via a serial console before paging_init. 281 */ 282 ldr r3, [r8, #MACHINFO_PGOFFIO] 283 add r0, r4, r3 284 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 285 cmp r3, #0x0800 @ limit to 512MB 286 movhi r3, #0x0800 287 add r6, r0, r3 288 ldr r3, [r8, #MACHINFO_PHYSIO] 289 orr r3, r3, r7 2901: str r3, [r0], #4 291 add r3, r3, #1 << 20 292 teq r0, r6 293 bne 1b 294#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 295 /* 296 * If we're using the NetWinder or CATS, we also need to map 297 * in the 16550-type serial port for the debug messages 298 */ 299 add r0, r4, #0xff000000 >> 18 300 orr r3, r7, #0x7c000000 301 str r3, [r0] 302#endif 303#ifdef CONFIG_ARCH_RPC 304 /* 305 * Map in screen at 0x02000000 & SCREEN2_BASE 306 * Similar reasons here - for debug. This is 307 * only for Acorn RiscPC architectures. 308 */ 309 add r0, r4, #0x02000000 >> 18 310 orr r3, r7, #0x02000000 311 str r3, [r0] 312 add r0, r4, #0xd8000000 >> 18 313 str r3, [r0] 314#endif 315#endif 316 mov pc, lr 317 .ltorg 318 319#include "head-common.S" 320