1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/domain.h> 19#include <asm/procinfo.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/memory.h> 23#include <asm/thread_info.h> 24#include <asm/system.h> 25 26#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) 27 28/* 29 * swapper_pg_dir is the virtual address of the initial page table. 30 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must 31 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect 32 * the least significant 16 bits to be 0x8000, but we could probably 33 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000. 34 */ 35#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000 36#error KERNEL_RAM_ADDR must start at 0xXXXX8000 37#endif 38 39 .globl swapper_pg_dir 40 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000 41 42 .macro pgtbl, rd 43 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000)) 44 .endm 45 46#ifdef CONFIG_XIP_KERNEL 47#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 48#else 49#define TEXTADDR KERNEL_RAM_ADDR 50#endif 51 52/* 53 * Kernel startup entry point. 54 * --------------------------- 55 * 56 * This is normally called from the decompressor code. The requirements 57 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 58 * r1 = machine nr. 59 * 60 * This code is mostly position independent, so if you link the kernel at 61 * 0xc0008000, you call this at __pa(0xc0008000). 62 * 63 * See linux/arch/arm/tools/mach-types for the complete list of machine 64 * numbers for r1. 65 * 66 * We're trying to keep crap to a minimum; DO NOT add any machine specific 67 * crap here - that's what the boot loader (or in extreme, well justified 68 * circumstances, zImage) is for. 69 */ 70 __INIT 71 .type stext, %function 72ENTRY(stext) 73 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode 74 @ and irqs disabled 75 mrc p15, 0, r9, c0, c0 @ get processor id 76 bl __lookup_processor_type @ r5=procinfo r9=cpuid 77 movs r10, r5 @ invalid processor (r5=0)? 78 beq __error_p @ yes, error 'p' 79 bl __lookup_machine_type @ r5=machinfo 80 movs r8, r5 @ invalid machine (r5=0)? 81 beq __error_a @ yes, error 'a' 82 bl __create_page_tables 83 84 /* 85 * The following calls CPU specific code in a position independent 86 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 87 * xxx_proc_info structure selected by __lookup_machine_type 88 * above. On return, the CPU will be ready for the MMU to be 89 * turned on, and r0 will hold the CPU control register value. 90 */ 91 ldr r13, __switch_data @ address to jump to after 92 @ mmu has been enabled 93 adr lr, __enable_mmu @ return (PIC) address 94 add pc, r10, #PROCINFO_INITFUNC 95 96#if defined(CONFIG_SMP) 97 .type secondary_startup, #function 98ENTRY(secondary_startup) 99 /* 100 * Common entry point for secondary CPUs. 101 * 102 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 103 * the processor type - there is no need to check the machine type 104 * as it has already been validated by the primary processor. 105 */ 106 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 107 mrc p15, 0, r9, c0, c0 @ get processor id 108 bl __lookup_processor_type 109 movs r10, r5 @ invalid processor? 110 moveq r0, #'p' @ yes, error 'p' 111 beq __error 112 113 /* 114 * Use the page tables supplied from __cpu_up. 115 */ 116 adr r4, __secondary_data 117 ldmia r4, {r5, r7, r13} @ address to jump to after 118 sub r4, r4, r5 @ mmu has been enabled 119 ldr r4, [r7, r4] @ get secondary_data.pgdir 120 adr lr, __enable_mmu @ return address 121 add pc, r10, #PROCINFO_INITFUNC @ initialise processor 122 @ (return control reg) 123 124 /* 125 * r6 = &secondary_data 126 */ 127ENTRY(__secondary_switched) 128 ldr sp, [r7, #4] @ get secondary_data.stack 129 mov fp, #0 130 b secondary_start_kernel 131 132 .type __secondary_data, %object 133__secondary_data: 134 .long . 135 .long secondary_data 136 .long __secondary_switched 137#endif /* defined(CONFIG_SMP) */ 138 139 140 141/* 142 * Setup common bits before finally enabling the MMU. Essentially 143 * this is just loading the page table pointer and domain access 144 * registers. 145 */ 146 .type __enable_mmu, %function 147__enable_mmu: 148#ifdef CONFIG_ALIGNMENT_TRAP 149 orr r0, r0, #CR_A 150#else 151 bic r0, r0, #CR_A 152#endif 153#ifdef CONFIG_CPU_DCACHE_DISABLE 154 bic r0, r0, #CR_C 155#endif 156#ifdef CONFIG_CPU_BPREDICT_DISABLE 157 bic r0, r0, #CR_Z 158#endif 159#ifdef CONFIG_CPU_ICACHE_DISABLE 160 bic r0, r0, #CR_I 161#endif 162 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 163 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 164 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 165 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 166 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 167 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 168 b __turn_mmu_on 169 170/* 171 * Enable the MMU. This completely changes the structure of the visible 172 * memory space. You will not be able to trace execution through this. 173 * If you have an enquiry about this, *please* check the linux-arm-kernel 174 * mailing list archives BEFORE sending another post to the list. 175 * 176 * r0 = cp#15 control register 177 * r13 = *virtual* address to jump to upon completion 178 * 179 * other registers depend on the function called upon completion 180 */ 181 .align 5 182 .type __turn_mmu_on, %function 183__turn_mmu_on: 184 mov r0, r0 185 mcr p15, 0, r0, c1, c0, 0 @ write control reg 186 mrc p15, 0, r3, c0, c0, 0 @ read id reg 187 mov r3, r3 188 mov r3, r3 189 mov pc, r13 190 191 192 193/* 194 * Setup the initial page tables. We only setup the barest 195 * amount which are required to get the kernel running, which 196 * generally means mapping in the kernel code. 197 * 198 * r8 = machinfo 199 * r9 = cpuid 200 * r10 = procinfo 201 * 202 * Returns: 203 * r0, r3, r6, r7 corrupted 204 * r4 = physical page table address 205 */ 206 .type __create_page_tables, %function 207__create_page_tables: 208 pgtbl r4 @ page table address 209 210 /* 211 * Clear the 16K level 1 swapper page table 212 */ 213 mov r0, r4 214 mov r3, #0 215 add r6, r0, #0x4000 2161: str r3, [r0], #4 217 str r3, [r0], #4 218 str r3, [r0], #4 219 str r3, [r0], #4 220 teq r0, r6 221 bne 1b 222 223 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 224 225 /* 226 * Create identity mapping for first MB of kernel to 227 * cater for the MMU enable. This identity mapping 228 * will be removed by paging_init(). We use our current program 229 * counter to determine corresponding section base address. 230 */ 231 mov r6, pc, lsr #20 @ start of kernel section 232 orr r3, r7, r6, lsl #20 @ flags + kernel base 233 str r3, [r4, r6, lsl #2] @ identity mapping 234 235 /* 236 * Now setup the pagetables for our kernel direct 237 * mapped region. We round TEXTADDR down to the 238 * nearest megabyte boundary. It is assumed that 239 * the kernel fits within 4 contigous 1MB sections. 240 */ 241 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel 242 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]! 243 add r3, r3, #1 << 20 244 str r3, [r0, #4]! @ KERNEL + 1MB 245 add r3, r3, #1 << 20 246 str r3, [r0, #4]! @ KERNEL + 2MB 247 add r3, r3, #1 << 20 248 str r3, [r0, #4] @ KERNEL + 3MB 249 250 /* 251 * Then map first 1MB of ram in case it contains our boot params. 252 */ 253 add r0, r4, #PAGE_OFFSET >> 18 254 orr r6, r7, #PHYS_OFFSET 255 str r6, [r0] 256 257#ifdef CONFIG_XIP_KERNEL 258 /* 259 * Map some ram to cover our .data and .bss areas. 260 * Mapping 3MB should be plenty. 261 */ 262 sub r3, r4, #PHYS_OFFSET 263 mov r3, r3, lsr #20 264 add r0, r0, r3, lsl #2 265 add r6, r6, r3, lsl #20 266 str r6, [r0], #4 267 add r6, r6, #(1 << 20) 268 str r6, [r0], #4 269 add r6, r6, #(1 << 20) 270 str r6, [r0] 271#endif 272 273#ifdef CONFIG_DEBUG_LL 274 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 275 /* 276 * Map in IO space for serial debugging. 277 * This allows debug messages to be output 278 * via a serial console before paging_init. 279 */ 280 ldr r3, [r8, #MACHINFO_PGOFFIO] 281 add r0, r4, r3 282 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 283 cmp r3, #0x0800 @ limit to 512MB 284 movhi r3, #0x0800 285 add r6, r0, r3 286 ldr r3, [r8, #MACHINFO_PHYSIO] 287 orr r3, r3, r7 2881: str r3, [r0], #4 289 add r3, r3, #1 << 20 290 teq r0, r6 291 bne 1b 292#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 293 /* 294 * If we're using the NetWinder or CATS, we also need to map 295 * in the 16550-type serial port for the debug messages 296 */ 297 add r0, r4, #0xff000000 >> 18 298 orr r3, r7, #0x7c000000 299 str r3, [r0] 300#endif 301#ifdef CONFIG_ARCH_RPC 302 /* 303 * Map in screen at 0x02000000 & SCREEN2_BASE 304 * Similar reasons here - for debug. This is 305 * only for Acorn RiscPC architectures. 306 */ 307 add r0, r4, #0x02000000 >> 18 308 orr r3, r7, #0x02000000 309 str r3, [r0] 310 add r0, r4, #0xd8000000 >> 18 311 str r3, [r0] 312#endif 313#endif 314 mov pc, lr 315 .ltorg 316 317#include "head-common.S" 318