1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/cp15.h> 19#include <asm/domain.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/memory.h> 23#include <asm/thread_info.h> 24#include <asm/pgtable.h> 25 26#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) 27#include CONFIG_DEBUG_LL_INCLUDE 28#endif 29 30/* 31 * swapper_pg_dir is the virtual address of the initial page table. 32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 34 * the least significant 16 bits to be 0x8000, but we could probably 35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 36 */ 37#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39#error KERNEL_RAM_VADDR must start at 0xXXXX8000 40#endif 41 42#ifdef CONFIG_ARM_LPAE 43 /* LPAE requires an additional page for the PGD */ 44#define PG_DIR_SIZE 0x5000 45#define PMD_ORDER 3 46#else 47#define PG_DIR_SIZE 0x4000 48#define PMD_ORDER 2 49#endif 50 51 .globl swapper_pg_dir 52 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 53 54 .macro pgtbl, rd, phys 55 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE 56 .endm 57 58/* 59 * Kernel startup entry point. 60 * --------------------------- 61 * 62 * This is normally called from the decompressor code. The requirements 63 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 64 * r1 = machine nr, r2 = atags or dtb pointer. 65 * 66 * This code is mostly position independent, so if you link the kernel at 67 * 0xc0008000, you call this at __pa(0xc0008000). 68 * 69 * See linux/arch/arm/tools/mach-types for the complete list of machine 70 * numbers for r1. 71 * 72 * We're trying to keep crap to a minimum; DO NOT add any machine specific 73 * crap here - that's what the boot loader (or in extreme, well justified 74 * circumstances, zImage) is for. 75 */ 76 .arm 77 78 __HEAD 79ENTRY(stext) 80 81 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 82 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 83 THUMB( .thumb ) @ switch to Thumb now. 84 THUMB(1: ) 85 86#ifdef CONFIG_ARM_VIRT_EXT 87 bl __hyp_stub_install 88#endif 89 @ ensure svc mode and all interrupts masked 90 safe_svcmode_maskall r9 91 92 mrc p15, 0, r9, c0, c0 @ get processor id 93 bl __lookup_processor_type @ r5=procinfo r9=cpuid 94 movs r10, r5 @ invalid processor (r5=0)? 95 THUMB( it eq ) @ force fixup-able long branch encoding 96 beq __error_p @ yes, error 'p' 97 98#ifdef CONFIG_ARM_LPAE 99 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 100 and r3, r3, #0xf @ extract VMSA support 101 cmp r3, #5 @ long-descriptor translation table format? 102 THUMB( it lo ) @ force fixup-able long branch encoding 103 blo __error_p @ only classic page table format 104#endif 105 106#ifndef CONFIG_XIP_KERNEL 107 adr r3, 2f 108 ldmia r3, {r4, r8} 109 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 110 add r8, r8, r4 @ PHYS_OFFSET 111#else 112 ldr r8, =PHYS_OFFSET @ always constant in this case 113#endif 114 115 /* 116 * r1 = machine no, r2 = atags or dtb, 117 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 118 */ 119 bl __vet_atags 120#ifdef CONFIG_SMP_ON_UP 121 bl __fixup_smp 122#endif 123#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 124 bl __fixup_pv_table 125#endif 126 bl __create_page_tables 127 128 /* 129 * The following calls CPU specific code in a position independent 130 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 131 * xxx_proc_info structure selected by __lookup_processor_type 132 * above. On return, the CPU will be ready for the MMU to be 133 * turned on, and r0 will hold the CPU control register value. 134 */ 135 ldr r13, =__mmap_switched @ address to jump to after 136 @ mmu has been enabled 137 adr lr, BSYM(1f) @ return (PIC) address 138 mov r8, r4 @ set TTBR1 to swapper_pg_dir 139 ARM( add pc, r10, #PROCINFO_INITFUNC ) 140 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 141 THUMB( mov pc, r12 ) 1421: b __enable_mmu 143ENDPROC(stext) 144 .ltorg 145#ifndef CONFIG_XIP_KERNEL 1462: .long . 147 .long PAGE_OFFSET 148#endif 149 150/* 151 * Setup the initial page tables. We only setup the barest 152 * amount which are required to get the kernel running, which 153 * generally means mapping in the kernel code. 154 * 155 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 156 * 157 * Returns: 158 * r0, r3, r5-r7 corrupted 159 * r4 = physical page table address 160 */ 161__create_page_tables: 162 pgtbl r4, r8 @ page table address 163 164 /* 165 * Clear the swapper page table 166 */ 167 mov r0, r4 168 mov r3, #0 169 add r6, r0, #PG_DIR_SIZE 1701: str r3, [r0], #4 171 str r3, [r0], #4 172 str r3, [r0], #4 173 str r3, [r0], #4 174 teq r0, r6 175 bne 1b 176 177#ifdef CONFIG_ARM_LPAE 178 /* 179 * Build the PGD table (first level) to point to the PMD table. A PGD 180 * entry is 64-bit wide. 181 */ 182 mov r0, r4 183 add r3, r4, #0x1000 @ first PMD table address 184 orr r3, r3, #3 @ PGD block type 185 mov r6, #4 @ PTRS_PER_PGD 186 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 1871: str r3, [r0], #4 @ set bottom PGD entry bits 188 str r7, [r0], #4 @ set top PGD entry bits 189 add r3, r3, #0x1000 @ next PMD table 190 subs r6, r6, #1 191 bne 1b 192 193 add r4, r4, #0x1000 @ point to the PMD tables 194#endif 195 196 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 197 198 /* 199 * Create identity mapping to cater for __enable_mmu. 200 * This identity mapping will be removed by paging_init(). 201 */ 202 adr r0, __turn_mmu_on_loc 203 ldmia r0, {r3, r5, r6} 204 sub r0, r0, r3 @ virt->phys offset 205 add r5, r5, r0 @ phys __turn_mmu_on 206 add r6, r6, r0 @ phys __turn_mmu_on_end 207 mov r5, r5, lsr #SECTION_SHIFT 208 mov r6, r6, lsr #SECTION_SHIFT 209 2101: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 211 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 212 cmp r5, r6 213 addlo r5, r5, #1 @ next section 214 blo 1b 215 216 /* 217 * Map our RAM from the start to the end of the kernel .bss section. 218 */ 219 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) 220 ldr r6, =(_end - 1) 221 orr r3, r8, r7 222 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2231: str r3, [r0], #1 << PMD_ORDER 224 add r3, r3, #1 << SECTION_SHIFT 225 cmp r0, r6 226 bls 1b 227 228#ifdef CONFIG_XIP_KERNEL 229 /* 230 * Map the kernel image separately as it is not located in RAM. 231 */ 232#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 233 mov r3, pc 234 mov r3, r3, lsr #SECTION_SHIFT 235 orr r3, r7, r3, lsl #SECTION_SHIFT 236 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 237 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 238 ldr r6, =(_edata_loc - 1) 239 add r0, r0, #1 << PMD_ORDER 240 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2411: cmp r0, r6 242 add r3, r3, #1 << SECTION_SHIFT 243 strls r3, [r0], #1 << PMD_ORDER 244 bls 1b 245#endif 246 247 /* 248 * Then map boot params address in r2 if specified. 249 */ 250 mov r0, r2, lsr #SECTION_SHIFT 251 movs r0, r0, lsl #SECTION_SHIFT 252 subne r3, r0, r8 253 addne r3, r3, #PAGE_OFFSET 254 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 255 orrne r6, r7, r0 256 strne r6, [r3] 257 258#ifdef CONFIG_DEBUG_LL 259#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) 260 /* 261 * Map in IO space for serial debugging. 262 * This allows debug messages to be output 263 * via a serial console before paging_init. 264 */ 265 addruart r7, r3, r0 266 267 mov r3, r3, lsr #SECTION_SHIFT 268 mov r3, r3, lsl #PMD_ORDER 269 270 add r0, r4, r3 271 mov r3, r7, lsr #SECTION_SHIFT 272 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 273 orr r3, r7, r3, lsl #SECTION_SHIFT 274#ifdef CONFIG_ARM_LPAE 275 mov r7, #1 << (54 - 32) @ XN 276#else 277 orr r3, r3, #PMD_SECT_XN 278#endif 279 str r3, [r0], #4 280#ifdef CONFIG_ARM_LPAE 281 str r7, [r0], #4 282#endif 283 284#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ 285 /* we don't need any serial debugging mappings */ 286 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 287#endif 288 289#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 290 /* 291 * If we're using the NetWinder or CATS, we also need to map 292 * in the 16550-type serial port for the debug messages 293 */ 294 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 295 orr r3, r7, #0x7c000000 296 str r3, [r0] 297#endif 298#ifdef CONFIG_ARCH_RPC 299 /* 300 * Map in screen at 0x02000000 & SCREEN2_BASE 301 * Similar reasons here - for debug. This is 302 * only for Acorn RiscPC architectures. 303 */ 304 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 305 orr r3, r7, #0x02000000 306 str r3, [r0] 307 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 308 str r3, [r0] 309#endif 310#endif 311#ifdef CONFIG_ARM_LPAE 312 sub r4, r4, #0x1000 @ point to the PGD table 313#endif 314 mov pc, lr 315ENDPROC(__create_page_tables) 316 .ltorg 317 .align 318__turn_mmu_on_loc: 319 .long . 320 .long __turn_mmu_on 321 .long __turn_mmu_on_end 322 323#if defined(CONFIG_SMP) 324 __CPUINIT 325ENTRY(secondary_startup) 326 /* 327 * Common entry point for secondary CPUs. 328 * 329 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 330 * the processor type - there is no need to check the machine type 331 * as it has already been validated by the primary processor. 332 */ 333#ifdef CONFIG_ARM_VIRT_EXT 334 bl __hyp_stub_install 335#endif 336 safe_svcmode_maskall r9 337 338 mrc p15, 0, r9, c0, c0 @ get processor id 339 bl __lookup_processor_type 340 movs r10, r5 @ invalid processor? 341 moveq r0, #'p' @ yes, error 'p' 342 THUMB( it eq ) @ force fixup-able long branch encoding 343 beq __error_p 344 345 /* 346 * Use the page tables supplied from __cpu_up. 347 */ 348 adr r4, __secondary_data 349 ldmia r4, {r5, r7, r12} @ address to jump to after 350 sub lr, r4, r5 @ mmu has been enabled 351 ldr r4, [r7, lr] @ get secondary_data.pgdir 352 add r7, r7, #4 353 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 354 adr lr, BSYM(__enable_mmu) @ return address 355 mov r13, r12 @ __secondary_switched address 356 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 357 @ (return control reg) 358 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 359 THUMB( mov pc, r12 ) 360ENDPROC(secondary_startup) 361 362 /* 363 * r6 = &secondary_data 364 */ 365ENTRY(__secondary_switched) 366 ldr sp, [r7, #4] @ get secondary_data.stack 367 mov fp, #0 368 b secondary_start_kernel 369ENDPROC(__secondary_switched) 370 371 .align 372 373 .type __secondary_data, %object 374__secondary_data: 375 .long . 376 .long secondary_data 377 .long __secondary_switched 378#endif /* defined(CONFIG_SMP) */ 379 380 381 382/* 383 * Setup common bits before finally enabling the MMU. Essentially 384 * this is just loading the page table pointer and domain access 385 * registers. 386 * 387 * r0 = cp#15 control register 388 * r1 = machine ID 389 * r2 = atags or dtb pointer 390 * r4 = page table pointer 391 * r9 = processor ID 392 * r13 = *virtual* address to jump to upon completion 393 */ 394__enable_mmu: 395#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 396 orr r0, r0, #CR_A 397#else 398 bic r0, r0, #CR_A 399#endif 400#ifdef CONFIG_CPU_DCACHE_DISABLE 401 bic r0, r0, #CR_C 402#endif 403#ifdef CONFIG_CPU_BPREDICT_DISABLE 404 bic r0, r0, #CR_Z 405#endif 406#ifdef CONFIG_CPU_ICACHE_DISABLE 407 bic r0, r0, #CR_I 408#endif 409#ifdef CONFIG_ARM_LPAE 410 mov r5, #0 411 mcrr p15, 0, r4, r5, c2 @ load TTBR0 412#else 413 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 414 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 415 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 416 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 417 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 418 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 419#endif 420 b __turn_mmu_on 421ENDPROC(__enable_mmu) 422 423/* 424 * Enable the MMU. This completely changes the structure of the visible 425 * memory space. You will not be able to trace execution through this. 426 * If you have an enquiry about this, *please* check the linux-arm-kernel 427 * mailing list archives BEFORE sending another post to the list. 428 * 429 * r0 = cp#15 control register 430 * r1 = machine ID 431 * r2 = atags or dtb pointer 432 * r9 = processor ID 433 * r13 = *virtual* address to jump to upon completion 434 * 435 * other registers depend on the function called upon completion 436 */ 437 .align 5 438 .pushsection .idmap.text, "ax" 439ENTRY(__turn_mmu_on) 440 mov r0, r0 441 instr_sync 442 mcr p15, 0, r0, c1, c0, 0 @ write control reg 443 mrc p15, 0, r3, c0, c0, 0 @ read id reg 444 instr_sync 445 mov r3, r3 446 mov r3, r13 447 mov pc, r3 448__turn_mmu_on_end: 449ENDPROC(__turn_mmu_on) 450 .popsection 451 452 453#ifdef CONFIG_SMP_ON_UP 454 __INIT 455__fixup_smp: 456 and r3, r9, #0x000f0000 @ architecture version 457 teq r3, #0x000f0000 @ CPU ID supported? 458 bne __fixup_smp_on_up @ no, assume UP 459 460 bic r3, r9, #0x00ff0000 461 bic r3, r3, #0x0000000f @ mask 0xff00fff0 462 mov r4, #0x41000000 463 orr r4, r4, #0x0000b000 464 orr r4, r4, #0x00000020 @ val 0x4100b020 465 teq r3, r4 @ ARM 11MPCore? 466 moveq pc, lr @ yes, assume SMP 467 468 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 469 and r0, r0, #0xc0000000 @ multiprocessing extensions and 470 teq r0, #0x80000000 @ not part of a uniprocessor system? 471 moveq pc, lr @ yes, assume SMP 472 473__fixup_smp_on_up: 474 adr r0, 1f 475 ldmia r0, {r3 - r5} 476 sub r3, r0, r3 477 add r4, r4, r3 478 add r5, r5, r3 479 b __do_fixup_smp_on_up 480ENDPROC(__fixup_smp) 481 482 .align 4831: .word . 484 .word __smpalt_begin 485 .word __smpalt_end 486 487 .pushsection .data 488 .globl smp_on_up 489smp_on_up: 490 ALT_SMP(.long 1) 491 ALT_UP(.long 0) 492 .popsection 493#endif 494 495 .text 496__do_fixup_smp_on_up: 497 cmp r4, r5 498 movhs pc, lr 499 ldmia r4!, {r0, r6} 500 ARM( str r6, [r0, r3] ) 501 THUMB( add r0, r0, r3 ) 502#ifdef __ARMEB__ 503 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 504#endif 505 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 506 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 507 THUMB( strh r6, [r0] ) 508 b __do_fixup_smp_on_up 509ENDPROC(__do_fixup_smp_on_up) 510 511ENTRY(fixup_smp) 512 stmfd sp!, {r4 - r6, lr} 513 mov r4, r0 514 add r5, r0, r1 515 mov r3, #0 516 bl __do_fixup_smp_on_up 517 ldmfd sp!, {r4 - r6, pc} 518ENDPROC(fixup_smp) 519 520#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 521 522/* __fixup_pv_table - patch the stub instructions with the delta between 523 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 524 * can be expressed by an immediate shifter operand. The stub instruction 525 * has a form of '(add|sub) rd, rn, #imm'. 526 */ 527 __HEAD 528__fixup_pv_table: 529 adr r0, 1f 530 ldmia r0, {r3-r5, r7} 531 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 532 add r4, r4, r3 @ adjust table start address 533 add r5, r5, r3 @ adjust table end address 534 add r7, r7, r3 @ adjust __pv_phys_offset address 535 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 536 mov r6, r3, lsr #24 @ constant for add/sub instructions 537 teq r3, r6, lsl #24 @ must be 16MiB aligned 538THUMB( it ne @ cross section branch ) 539 bne __error 540 str r6, [r7, #4] @ save to __pv_offset 541 b __fixup_a_pv_table 542ENDPROC(__fixup_pv_table) 543 544 .align 5451: .long . 546 .long __pv_table_begin 547 .long __pv_table_end 5482: .long __pv_phys_offset 549 550 .text 551__fixup_a_pv_table: 552#ifdef CONFIG_THUMB2_KERNEL 553 lsls r6, #24 554 beq 2f 555 clz r7, r6 556 lsr r6, #24 557 lsl r6, r7 558 bic r6, #0x0080 559 lsrs r7, #1 560 orrcs r6, #0x0080 561 orr r6, r6, r7, lsl #12 562 orr r6, #0x4000 563 b 2f 5641: add r7, r3 565 ldrh ip, [r7, #2] 566 and ip, 0x8f00 567 orr ip, r6 @ mask in offset bits 31-24 568 strh ip, [r7, #2] 5692: cmp r4, r5 570 ldrcc r7, [r4], #4 @ use branch for delay slot 571 bcc 1b 572 bx lr 573#else 574 b 2f 5751: ldr ip, [r7, r3] 576 bic ip, ip, #0x000000ff 577 orr ip, ip, r6 @ mask in offset bits 31-24 578 str ip, [r7, r3] 5792: cmp r4, r5 580 ldrcc r7, [r4], #4 @ use branch for delay slot 581 bcc 1b 582 mov pc, lr 583#endif 584ENDPROC(__fixup_a_pv_table) 585 586ENTRY(fixup_pv_table) 587 stmfd sp!, {r4 - r7, lr} 588 ldr r2, 2f @ get address of __pv_phys_offset 589 mov r3, #0 @ no offset 590 mov r4, r0 @ r0 = table start 591 add r5, r0, r1 @ r1 = table size 592 ldr r6, [r2, #4] @ get __pv_offset 593 bl __fixup_a_pv_table 594 ldmfd sp!, {r4 - r7, pc} 595ENDPROC(fixup_pv_table) 596 597 .align 5982: .long __pv_phys_offset 599 600 .data 601 .globl __pv_phys_offset 602 .type __pv_phys_offset, %object 603__pv_phys_offset: 604 .long 0 605 .size __pv_phys_offset, . - __pv_phys_offset 606__pv_offset: 607 .long 0 608#endif 609 610#include "head-common.S" 611