1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/domain.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/memory.h> 22#include <asm/thread_info.h> 23#include <asm/system.h> 24#include <asm/pgtable.h> 25 26#ifdef CONFIG_DEBUG_LL 27#include <mach/debug-macro.S> 28#endif 29 30/* 31 * swapper_pg_dir is the virtual address of the initial page table. 32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 34 * the least significant 16 bits to be 0x8000, but we could probably 35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 36 */ 37#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 38#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 39#error KERNEL_RAM_VADDR must start at 0xXXXX8000 40#endif 41 42#ifdef CONFIG_ARM_LPAE 43 /* LPAE requires an additional page for the PGD */ 44#define PG_DIR_SIZE 0x5000 45#define PMD_ORDER 3 46#else 47#define PG_DIR_SIZE 0x4000 48#define PMD_ORDER 2 49#endif 50 51 .globl swapper_pg_dir 52 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 53 54 .macro pgtbl, rd, phys 55 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE 56 .endm 57 58#ifdef CONFIG_XIP_KERNEL 59#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 60#define KERNEL_END _edata_loc 61#else 62#define KERNEL_START KERNEL_RAM_VADDR 63#define KERNEL_END _end 64#endif 65 66/* 67 * Kernel startup entry point. 68 * --------------------------- 69 * 70 * This is normally called from the decompressor code. The requirements 71 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 72 * r1 = machine nr, r2 = atags or dtb pointer. 73 * 74 * This code is mostly position independent, so if you link the kernel at 75 * 0xc0008000, you call this at __pa(0xc0008000). 76 * 77 * See linux/arch/arm/tools/mach-types for the complete list of machine 78 * numbers for r1. 79 * 80 * We're trying to keep crap to a minimum; DO NOT add any machine specific 81 * crap here - that's what the boot loader (or in extreme, well justified 82 * circumstances, zImage) is for. 83 */ 84 .arm 85 86 __HEAD 87ENTRY(stext) 88 89 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 90 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 91 THUMB( .thumb ) @ switch to Thumb now. 92 THUMB(1: ) 93 94 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 95 @ and irqs disabled 96 mrc p15, 0, r9, c0, c0 @ get processor id 97 bl __lookup_processor_type @ r5=procinfo r9=cpuid 98 movs r10, r5 @ invalid processor (r5=0)? 99 THUMB( it eq ) @ force fixup-able long branch encoding 100 beq __error_p @ yes, error 'p' 101 102#ifndef CONFIG_XIP_KERNEL 103 adr r3, 2f 104 ldmia r3, {r4, r8} 105 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 106 add r8, r8, r4 @ PHYS_OFFSET 107#else 108 ldr r8, =PHYS_OFFSET @ always constant in this case 109#endif 110 111 /* 112 * r1 = machine no, r2 = atags or dtb, 113 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 114 */ 115 bl __vet_atags 116#ifdef CONFIG_SMP_ON_UP 117 bl __fixup_smp 118#endif 119#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 120 bl __fixup_pv_table 121#endif 122 bl __create_page_tables 123 124 /* 125 * The following calls CPU specific code in a position independent 126 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 127 * xxx_proc_info structure selected by __lookup_processor_type 128 * above. On return, the CPU will be ready for the MMU to be 129 * turned on, and r0 will hold the CPU control register value. 130 */ 131 ldr r13, =__mmap_switched @ address to jump to after 132 @ mmu has been enabled 133 adr lr, BSYM(1f) @ return (PIC) address 134 mov r8, r4 @ set TTBR1 to swapper_pg_dir 135 ARM( add pc, r10, #PROCINFO_INITFUNC ) 136 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 137 THUMB( mov pc, r12 ) 1381: b __enable_mmu 139ENDPROC(stext) 140 .ltorg 141#ifndef CONFIG_XIP_KERNEL 1422: .long . 143 .long PAGE_OFFSET 144#endif 145 146/* 147 * Setup the initial page tables. We only setup the barest 148 * amount which are required to get the kernel running, which 149 * generally means mapping in the kernel code. 150 * 151 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 152 * 153 * Returns: 154 * r0, r3, r5-r7 corrupted 155 * r4 = physical page table address 156 */ 157__create_page_tables: 158 pgtbl r4, r8 @ page table address 159 160 /* 161 * Clear the swapper page table 162 */ 163 mov r0, r4 164 mov r3, #0 165 add r6, r0, #PG_DIR_SIZE 1661: str r3, [r0], #4 167 str r3, [r0], #4 168 str r3, [r0], #4 169 str r3, [r0], #4 170 teq r0, r6 171 bne 1b 172 173#ifdef CONFIG_ARM_LPAE 174 /* 175 * Build the PGD table (first level) to point to the PMD table. A PGD 176 * entry is 64-bit wide. 177 */ 178 mov r0, r4 179 add r3, r4, #0x1000 @ first PMD table address 180 orr r3, r3, #3 @ PGD block type 181 mov r6, #4 @ PTRS_PER_PGD 182 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 1831: str r3, [r0], #4 @ set bottom PGD entry bits 184 str r7, [r0], #4 @ set top PGD entry bits 185 add r3, r3, #0x1000 @ next PMD table 186 subs r6, r6, #1 187 bne 1b 188 189 add r4, r4, #0x1000 @ point to the PMD tables 190#endif 191 192 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 193 194 /* 195 * Create identity mapping to cater for __enable_mmu. 196 * This identity mapping will be removed by paging_init(). 197 */ 198 adr r0, __turn_mmu_on_loc 199 ldmia r0, {r3, r5, r6} 200 sub r0, r0, r3 @ virt->phys offset 201 add r5, r5, r0 @ phys __turn_mmu_on 202 add r6, r6, r0 @ phys __turn_mmu_on_end 203 mov r5, r5, lsr #SECTION_SHIFT 204 mov r6, r6, lsr #SECTION_SHIFT 205 2061: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 207 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 208 cmp r5, r6 209 addlo r5, r5, #1 @ next section 210 blo 1b 211 212 /* 213 * Now setup the pagetables for our kernel direct 214 * mapped region. 215 */ 216 mov r3, pc 217 mov r3, r3, lsr #SECTION_SHIFT 218 orr r3, r7, r3, lsl #SECTION_SHIFT 219 add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 220 str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 221 ldr r6, =(KERNEL_END - 1) 222 add r0, r0, #1 << PMD_ORDER 223 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2241: cmp r0, r6 225 add r3, r3, #1 << SECTION_SHIFT 226 strls r3, [r0], #1 << PMD_ORDER 227 bls 1b 228 229#ifdef CONFIG_XIP_KERNEL 230 /* 231 * Map some ram to cover our .data and .bss areas. 232 */ 233 add r3, r8, #TEXT_OFFSET 234 orr r3, r3, r7 235 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 236 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]! 237 ldr r6, =(_end - 1) 238 add r0, r0, #4 239 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2401: cmp r0, r6 241 add r3, r3, #1 << 20 242 strls r3, [r0], #4 243 bls 1b 244#endif 245 246 /* 247 * Then map boot params address in r2 or the first 1MB (2MB with LPAE) 248 * of ram if boot params address is not specified. 249 */ 250 mov r0, r2, lsr #SECTION_SHIFT 251 movs r0, r0, lsl #SECTION_SHIFT 252 moveq r0, r8 253 sub r3, r0, r8 254 add r3, r3, #PAGE_OFFSET 255 add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) 256 orr r6, r7, r0 257 str r6, [r3] 258 259#ifdef CONFIG_DEBUG_LL 260#ifndef CONFIG_DEBUG_ICEDCC 261 /* 262 * Map in IO space for serial debugging. 263 * This allows debug messages to be output 264 * via a serial console before paging_init. 265 */ 266 addruart r7, r3, r0 267 268 mov r3, r3, lsr #SECTION_SHIFT 269 mov r3, r3, lsl #PMD_ORDER 270 271 add r0, r4, r3 272 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 273 cmp r3, #0x0800 @ limit to 512MB 274 movhi r3, #0x0800 275 add r6, r0, r3 276 mov r3, r7, lsr #SECTION_SHIFT 277 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 278 orr r3, r7, r3, lsl #SECTION_SHIFT 279#ifdef CONFIG_ARM_LPAE 280 mov r7, #1 << (54 - 32) @ XN 281#else 282 orr r3, r3, #PMD_SECT_XN 283#endif 2841: str r3, [r0], #4 285#ifdef CONFIG_ARM_LPAE 286 str r7, [r0], #4 287#endif 288 add r3, r3, #1 << SECTION_SHIFT 289 cmp r0, r6 290 blo 1b 291 292#else /* CONFIG_DEBUG_ICEDCC */ 293 /* we don't need any serial debugging mappings for ICEDCC */ 294 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 295#endif /* !CONFIG_DEBUG_ICEDCC */ 296 297#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 298 /* 299 * If we're using the NetWinder or CATS, we also need to map 300 * in the 16550-type serial port for the debug messages 301 */ 302 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 303 orr r3, r7, #0x7c000000 304 str r3, [r0] 305#endif 306#ifdef CONFIG_ARCH_RPC 307 /* 308 * Map in screen at 0x02000000 & SCREEN2_BASE 309 * Similar reasons here - for debug. This is 310 * only for Acorn RiscPC architectures. 311 */ 312 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 313 orr r3, r7, #0x02000000 314 str r3, [r0] 315 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 316 str r3, [r0] 317#endif 318#endif 319#ifdef CONFIG_ARM_LPAE 320 sub r4, r4, #0x1000 @ point to the PGD table 321#endif 322 mov pc, lr 323ENDPROC(__create_page_tables) 324 .ltorg 325 .align 326__turn_mmu_on_loc: 327 .long . 328 .long __turn_mmu_on 329 .long __turn_mmu_on_end 330 331#if defined(CONFIG_SMP) 332 __CPUINIT 333ENTRY(secondary_startup) 334 /* 335 * Common entry point for secondary CPUs. 336 * 337 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 338 * the processor type - there is no need to check the machine type 339 * as it has already been validated by the primary processor. 340 */ 341 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 342 mrc p15, 0, r9, c0, c0 @ get processor id 343 bl __lookup_processor_type 344 movs r10, r5 @ invalid processor? 345 moveq r0, #'p' @ yes, error 'p' 346 THUMB( it eq ) @ force fixup-able long branch encoding 347 beq __error_p 348 349 /* 350 * Use the page tables supplied from __cpu_up. 351 */ 352 adr r4, __secondary_data 353 ldmia r4, {r5, r7, r12} @ address to jump to after 354 sub lr, r4, r5 @ mmu has been enabled 355 ldr r4, [r7, lr] @ get secondary_data.pgdir 356 add r7, r7, #4 357 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 358 adr lr, BSYM(__enable_mmu) @ return address 359 mov r13, r12 @ __secondary_switched address 360 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 361 @ (return control reg) 362 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 363 THUMB( mov pc, r12 ) 364ENDPROC(secondary_startup) 365 366 /* 367 * r6 = &secondary_data 368 */ 369ENTRY(__secondary_switched) 370 ldr sp, [r7, #4] @ get secondary_data.stack 371 mov fp, #0 372 b secondary_start_kernel 373ENDPROC(__secondary_switched) 374 375 .align 376 377 .type __secondary_data, %object 378__secondary_data: 379 .long . 380 .long secondary_data 381 .long __secondary_switched 382#endif /* defined(CONFIG_SMP) */ 383 384 385 386/* 387 * Setup common bits before finally enabling the MMU. Essentially 388 * this is just loading the page table pointer and domain access 389 * registers. 390 * 391 * r0 = cp#15 control register 392 * r1 = machine ID 393 * r2 = atags or dtb pointer 394 * r4 = page table pointer 395 * r9 = processor ID 396 * r13 = *virtual* address to jump to upon completion 397 */ 398__enable_mmu: 399#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 400 orr r0, r0, #CR_A 401#else 402 bic r0, r0, #CR_A 403#endif 404#ifdef CONFIG_CPU_DCACHE_DISABLE 405 bic r0, r0, #CR_C 406#endif 407#ifdef CONFIG_CPU_BPREDICT_DISABLE 408 bic r0, r0, #CR_Z 409#endif 410#ifdef CONFIG_CPU_ICACHE_DISABLE 411 bic r0, r0, #CR_I 412#endif 413#ifdef CONFIG_ARM_LPAE 414 mov r5, #0 415 mcrr p15, 0, r4, r5, c2 @ load TTBR0 416#else 417 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 418 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 419 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 420 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 421 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 422 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 423#endif 424 b __turn_mmu_on 425ENDPROC(__enable_mmu) 426 427/* 428 * Enable the MMU. This completely changes the structure of the visible 429 * memory space. You will not be able to trace execution through this. 430 * If you have an enquiry about this, *please* check the linux-arm-kernel 431 * mailing list archives BEFORE sending another post to the list. 432 * 433 * r0 = cp#15 control register 434 * r1 = machine ID 435 * r2 = atags or dtb pointer 436 * r9 = processor ID 437 * r13 = *virtual* address to jump to upon completion 438 * 439 * other registers depend on the function called upon completion 440 */ 441 .align 5 442 .pushsection .idmap.text, "ax" 443ENTRY(__turn_mmu_on) 444 mov r0, r0 445 instr_sync 446 mcr p15, 0, r0, c1, c0, 0 @ write control reg 447 mrc p15, 0, r3, c0, c0, 0 @ read id reg 448 instr_sync 449 mov r3, r3 450 mov r3, r13 451 mov pc, r3 452__turn_mmu_on_end: 453ENDPROC(__turn_mmu_on) 454 .popsection 455 456 457#ifdef CONFIG_SMP_ON_UP 458 __INIT 459__fixup_smp: 460 and r3, r9, #0x000f0000 @ architecture version 461 teq r3, #0x000f0000 @ CPU ID supported? 462 bne __fixup_smp_on_up @ no, assume UP 463 464 bic r3, r9, #0x00ff0000 465 bic r3, r3, #0x0000000f @ mask 0xff00fff0 466 mov r4, #0x41000000 467 orr r4, r4, #0x0000b000 468 orr r4, r4, #0x00000020 @ val 0x4100b020 469 teq r3, r4 @ ARM 11MPCore? 470 moveq pc, lr @ yes, assume SMP 471 472 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 473 and r0, r0, #0xc0000000 @ multiprocessing extensions and 474 teq r0, #0x80000000 @ not part of a uniprocessor system? 475 moveq pc, lr @ yes, assume SMP 476 477__fixup_smp_on_up: 478 adr r0, 1f 479 ldmia r0, {r3 - r5} 480 sub r3, r0, r3 481 add r4, r4, r3 482 add r5, r5, r3 483 b __do_fixup_smp_on_up 484ENDPROC(__fixup_smp) 485 486 .align 4871: .word . 488 .word __smpalt_begin 489 .word __smpalt_end 490 491 .pushsection .data 492 .globl smp_on_up 493smp_on_up: 494 ALT_SMP(.long 1) 495 ALT_UP(.long 0) 496 .popsection 497#endif 498 499 .text 500__do_fixup_smp_on_up: 501 cmp r4, r5 502 movhs pc, lr 503 ldmia r4!, {r0, r6} 504 ARM( str r6, [r0, r3] ) 505 THUMB( add r0, r0, r3 ) 506#ifdef __ARMEB__ 507 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 508#endif 509 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 510 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 511 THUMB( strh r6, [r0] ) 512 b __do_fixup_smp_on_up 513ENDPROC(__do_fixup_smp_on_up) 514 515ENTRY(fixup_smp) 516 stmfd sp!, {r4 - r6, lr} 517 mov r4, r0 518 add r5, r0, r1 519 mov r3, #0 520 bl __do_fixup_smp_on_up 521 ldmfd sp!, {r4 - r6, pc} 522ENDPROC(fixup_smp) 523 524#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 525 526/* __fixup_pv_table - patch the stub instructions with the delta between 527 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 528 * can be expressed by an immediate shifter operand. The stub instruction 529 * has a form of '(add|sub) rd, rn, #imm'. 530 */ 531 __HEAD 532__fixup_pv_table: 533 adr r0, 1f 534 ldmia r0, {r3-r5, r7} 535 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 536 add r4, r4, r3 @ adjust table start address 537 add r5, r5, r3 @ adjust table end address 538 add r7, r7, r3 @ adjust __pv_phys_offset address 539 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 540 mov r6, r3, lsr #24 @ constant for add/sub instructions 541 teq r3, r6, lsl #24 @ must be 16MiB aligned 542THUMB( it ne @ cross section branch ) 543 bne __error 544 str r6, [r7, #4] @ save to __pv_offset 545 b __fixup_a_pv_table 546ENDPROC(__fixup_pv_table) 547 548 .align 5491: .long . 550 .long __pv_table_begin 551 .long __pv_table_end 5522: .long __pv_phys_offset 553 554 .text 555__fixup_a_pv_table: 556#ifdef CONFIG_THUMB2_KERNEL 557 lsls r6, #24 558 beq 2f 559 clz r7, r6 560 lsr r6, #24 561 lsl r6, r7 562 bic r6, #0x0080 563 lsrs r7, #1 564 orrcs r6, #0x0080 565 orr r6, r6, r7, lsl #12 566 orr r6, #0x4000 567 b 2f 5681: add r7, r3 569 ldrh ip, [r7, #2] 570 and ip, 0x8f00 571 orr ip, r6 @ mask in offset bits 31-24 572 strh ip, [r7, #2] 5732: cmp r4, r5 574 ldrcc r7, [r4], #4 @ use branch for delay slot 575 bcc 1b 576 bx lr 577#else 578 b 2f 5791: ldr ip, [r7, r3] 580 bic ip, ip, #0x000000ff 581 orr ip, ip, r6 @ mask in offset bits 31-24 582 str ip, [r7, r3] 5832: cmp r4, r5 584 ldrcc r7, [r4], #4 @ use branch for delay slot 585 bcc 1b 586 mov pc, lr 587#endif 588ENDPROC(__fixup_a_pv_table) 589 590ENTRY(fixup_pv_table) 591 stmfd sp!, {r4 - r7, lr} 592 ldr r2, 2f @ get address of __pv_phys_offset 593 mov r3, #0 @ no offset 594 mov r4, r0 @ r0 = table start 595 add r5, r0, r1 @ r1 = table size 596 ldr r6, [r2, #4] @ get __pv_offset 597 bl __fixup_a_pv_table 598 ldmfd sp!, {r4 - r7, pc} 599ENDPROC(fixup_pv_table) 600 601 .align 6022: .long __pv_phys_offset 603 604 .data 605 .globl __pv_phys_offset 606 .type __pv_phys_offset, %object 607__pv_phys_offset: 608 .long 0 609 .size __pv_phys_offset, . - __pv_phys_offset 610__pv_offset: 611 .long 0 612#endif 613 614#include "head-common.S" 615