1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Kernel startup code for all 32-bit CPUs 11 */ 12#include <linux/config.h> 13#include <linux/linkage.h> 14#include <linux/init.h> 15 16#include <asm/assembler.h> 17#include <asm/domain.h> 18#include <asm/mach-types.h> 19#include <asm/procinfo.h> 20#include <asm/ptrace.h> 21#include <asm/constants.h> 22#include <asm/thread_info.h> 23#include <asm/system.h> 24 25#define PROCINFO_MMUFLAGS 8 26#define PROCINFO_INITFUNC 12 27 28#define MACHINFO_TYPE 0 29#define MACHINFO_PHYSRAM 4 30#define MACHINFO_PHYSIO 8 31#define MACHINFO_PGOFFIO 12 32#define MACHINFO_NAME 16 33 34#ifndef CONFIG_XIP_KERNEL 35/* 36 * We place the page tables 16K below TEXTADDR. Therefore, we must make sure 37 * that TEXTADDR is correctly set. Currently, we expect the least significant 38 * 16 bits to be 0x8000, but we could probably relax this restriction to 39 * TEXTADDR >= PAGE_OFFSET + 0x4000 40 * 41 * Note that swapper_pg_dir is the virtual address of the page tables, and 42 * pgtbl gives us a position-independent reference to these tables. We can 43 * do this because stext == TEXTADDR 44 */ 45#if (TEXTADDR & 0xffff) != 0x8000 46#error TEXTADDR must start at 0xXXXX8000 47#endif 48 49 .globl swapper_pg_dir 50 .equ swapper_pg_dir, TEXTADDR - 0x4000 51 52 .macro pgtbl, rd, phys 53 adr \rd, stext 54 sub \rd, \rd, #0x4000 55 .endm 56#else 57/* 58 * XIP Kernel: 59 * 60 * We place the page tables 16K below DATAADDR. Therefore, we must make sure 61 * that DATAADDR is correctly set. Currently, we expect the least significant 62 * 16 bits to be 0x8000, but we could probably relax this restriction to 63 * DATAADDR >= PAGE_OFFSET + 0x4000 64 * 65 * Note that pgtbl is meant to return the physical address of swapper_pg_dir. 66 * We can't make it relative to the kernel position in this case since 67 * the kernel can physically be anywhere. 68 */ 69#if (DATAADDR & 0xffff) != 0x8000 70#error DATAADDR must start at 0xXXXX8000 71#endif 72 73 .globl swapper_pg_dir 74 .equ swapper_pg_dir, DATAADDR - 0x4000 75 76 .macro pgtbl, rd, phys 77 ldr \rd, =((DATAADDR - 0x4000) - VIRT_OFFSET) 78 add \rd, \rd, \phys 79 .endm 80#endif 81 82/* 83 * Kernel startup entry point. 84 * --------------------------- 85 * 86 * This is normally called from the decompressor code. The requirements 87 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 88 * r1 = machine nr. 89 * 90 * This code is mostly position independent, so if you link the kernel at 91 * 0xc0008000, you call this at __pa(0xc0008000). 92 * 93 * See linux/arch/arm/tools/mach-types for the complete list of machine 94 * numbers for r1. 95 * 96 * We're trying to keep crap to a minimum; DO NOT add any machine specific 97 * crap here - that's what the boot loader (or in extreme, well justified 98 * circumstances, zImage) is for. 99 */ 100 __INIT 101 .type stext, %function 102ENTRY(stext) 103 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode 104 @ and irqs disabled 105 bl __lookup_processor_type @ r5=procinfo r9=cpuid 106 movs r10, r5 @ invalid processor (r5=0)? 107 beq __error_p @ yes, error 'p' 108 bl __lookup_machine_type @ r5=machinfo 109 movs r8, r5 @ invalid machine (r5=0)? 110 beq __error_a @ yes, error 'a' 111 bl __create_page_tables 112 113 /* 114 * The following calls CPU specific code in a position independent 115 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 116 * xxx_proc_info structure selected by __lookup_machine_type 117 * above. On return, the CPU will be ready for the MMU to be 118 * turned on, and r0 will hold the CPU control register value. 119 */ 120 ldr r13, __switch_data @ address to jump to after 121 @ mmu has been enabled 122 adr lr, __enable_mmu @ return (PIC) address 123 add pc, r10, #PROCINFO_INITFUNC 124 125 .type __switch_data, %object 126__switch_data: 127 .long __mmap_switched 128 .long __data_loc @ r4 129 .long __data_start @ r5 130 .long __bss_start @ r6 131 .long _end @ r7 132 .long processor_id @ r4 133 .long __machine_arch_type @ r5 134 .long cr_alignment @ r6 135 .long init_thread_union + THREAD_START_SP @ sp 136 137/* 138 * The following fragment of code is executed with the MMU on, and uses 139 * absolute addresses; this is not position independent. 140 * 141 * r0 = cp#15 control register 142 * r1 = machine ID 143 * r9 = processor ID 144 */ 145 .type __mmap_switched, %function 146__mmap_switched: 147 adr r3, __switch_data + 4 148 149 ldmia r3!, {r4, r5, r6, r7} 150 cmp r4, r5 @ Copy data segment if needed 1511: cmpne r5, r6 152 ldrne fp, [r4], #4 153 strne fp, [r5], #4 154 bne 1b 155 156 mov fp, #0 @ Clear BSS (and zero fp) 1571: cmp r6, r7 158 strcc fp, [r6],#4 159 bcc 1b 160 161 ldmia r3, {r4, r5, r6, sp} 162 str r9, [r4] @ Save processor ID 163 str r1, [r5] @ Save machine type 164 bic r4, r0, #CR_A @ Clear 'A' bit 165 stmia r6, {r0, r4} @ Save control register values 166 b start_kernel 167 168 169 170/* 171 * Setup common bits before finally enabling the MMU. Essentially 172 * this is just loading the page table pointer and domain access 173 * registers. 174 */ 175 .type __enable_mmu, %function 176__enable_mmu: 177#ifdef CONFIG_ALIGNMENT_TRAP 178 orr r0, r0, #CR_A 179#else 180 bic r0, r0, #CR_A 181#endif 182#ifdef CONFIG_CPU_DCACHE_DISABLE 183 bic r0, r0, #CR_C 184#endif 185#ifdef CONFIG_CPU_BPREDICT_DISABLE 186 bic r0, r0, #CR_Z 187#endif 188#ifdef CONFIG_CPU_ICACHE_DISABLE 189 bic r0, r0, #CR_I 190#endif 191 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 192 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 193 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 194 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 195 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 196 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 197 b __turn_mmu_on 198 199/* 200 * Enable the MMU. This completely changes the structure of the visible 201 * memory space. You will not be able to trace execution through this. 202 * If you have an enquiry about this, *please* check the linux-arm-kernel 203 * mailing list archives BEFORE sending another post to the list. 204 * 205 * r0 = cp#15 control register 206 * r13 = *virtual* address to jump to upon completion 207 * 208 * other registers depend on the function called upon completion 209 */ 210 .align 5 211 .type __turn_mmu_on, %function 212__turn_mmu_on: 213 mov r0, r0 214 mcr p15, 0, r0, c1, c0, 0 @ write control reg 215 mrc p15, 0, r3, c0, c0, 0 @ read id reg 216 mov r3, r3 217 mov r3, r3 218 mov pc, r13 219 220 221 222/* 223 * Setup the initial page tables. We only setup the barest 224 * amount which are required to get the kernel running, which 225 * generally means mapping in the kernel code. 226 * 227 * r8 = machinfo 228 * r9 = cpuid 229 * r10 = procinfo 230 * 231 * Returns: 232 * r0, r3, r5, r6, r7 corrupted 233 * r4 = physical page table address 234 */ 235 .type __create_page_tables, %function 236__create_page_tables: 237 ldr r5, [r8, #MACHINFO_PHYSRAM] @ physram 238 pgtbl r4, r5 @ page table address 239 240 /* 241 * Clear the 16K level 1 swapper page table 242 */ 243 mov r0, r4 244 mov r3, #0 245 add r6, r0, #0x4000 2461: str r3, [r0], #4 247 str r3, [r0], #4 248 str r3, [r0], #4 249 str r3, [r0], #4 250 teq r0, r6 251 bne 1b 252 253 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags 254 255 /* 256 * Create identity mapping for first MB of kernel to 257 * cater for the MMU enable. This identity mapping 258 * will be removed by paging_init(). We use our current program 259 * counter to determine corresponding section base address. 260 */ 261 mov r6, pc, lsr #20 @ start of kernel section 262 orr r3, r7, r6, lsl #20 @ flags + kernel base 263 str r3, [r4, r6, lsl #2] @ identity mapping 264 265 /* 266 * Now setup the pagetables for our kernel direct 267 * mapped region. We round TEXTADDR down to the 268 * nearest megabyte boundary. It is assumed that 269 * the kernel fits within 4 contigous 1MB sections. 270 */ 271 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel 272 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]! 273 add r3, r3, #1 << 20 274 str r3, [r0, #4]! @ KERNEL + 1MB 275 add r3, r3, #1 << 20 276 str r3, [r0, #4]! @ KERNEL + 2MB 277 add r3, r3, #1 << 20 278 str r3, [r0, #4] @ KERNEL + 3MB 279 280 /* 281 * Then map first 1MB of ram in case it contains our boot params. 282 */ 283 add r0, r4, #VIRT_OFFSET >> 18 284 orr r6, r5, r7 285 str r6, [r0] 286 287#ifdef CONFIG_XIP_KERNEL 288 /* 289 * Map some ram to cover our .data and .bss areas. 290 * Mapping 3MB should be plenty. 291 */ 292 sub r3, r4, r5 293 mov r3, r3, lsr #20 294 add r0, r0, r3, lsl #2 295 add r6, r6, r3, lsl #20 296 str r6, [r0], #4 297 add r6, r6, #(1 << 20) 298 str r6, [r0], #4 299 add r6, r6, #(1 << 20) 300 str r6, [r0] 301#endif 302 303 bic r7, r7, #0x0c @ turn off cacheable 304 @ and bufferable bits 305#ifdef CONFIG_DEBUG_LL 306 /* 307 * Map in IO space for serial debugging. 308 * This allows debug messages to be output 309 * via a serial console before paging_init. 310 */ 311 ldr r3, [r8, #MACHINFO_PGOFFIO] 312 add r0, r4, r3 313 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 314 cmp r3, #0x0800 @ limit to 512MB 315 movhi r3, #0x0800 316 add r6, r0, r3 317 ldr r3, [r8, #MACHINFO_PHYSIO] 318 orr r3, r3, r7 3191: str r3, [r0], #4 320 add r3, r3, #1 << 20 321 teq r0, r6 322 bne 1b 323#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 324 /* 325 * If we're using the NetWinder, we need to map in 326 * the 16550-type serial port for the debug messages 327 */ 328 teq r1, #MACH_TYPE_NETWINDER 329 teqne r1, #MACH_TYPE_CATS 330 bne 1f 331 add r0, r4, #0x3fc0 @ ff000000 332 mov r3, #0x7c000000 333 orr r3, r3, r7 334 str r3, [r0], #4 335 add r3, r3, #1 << 20 336 str r3, [r0], #4 3371: 338#endif 339#endif 340#ifdef CONFIG_ARCH_RPC 341 /* 342 * Map in screen at 0x02000000 & SCREEN2_BASE 343 * Similar reasons here - for debug. This is 344 * only for Acorn RiscPC architectures. 345 */ 346 add r0, r4, #0x80 @ 02000000 347 mov r3, #0x02000000 348 orr r3, r3, r7 349 str r3, [r0] 350 add r0, r4, #0x3600 @ d8000000 351 str r3, [r0] 352#endif 353 mov pc, lr 354 .ltorg 355 356 357 358/* 359 * Exception handling. Something went wrong and we can't proceed. We 360 * ought to tell the user, but since we don't have any guarantee that 361 * we're even running on the right architecture, we do virtually nothing. 362 * 363 * If CONFIG_DEBUG_LL is set we try to print out something about the error 364 * and hope for the best (useful if bootloader fails to pass a proper 365 * machine ID for example). 366 */ 367 368 .type __error_p, %function 369__error_p: 370#ifdef CONFIG_DEBUG_LL 371 adr r0, str_p1 372 bl printascii 373 b __error 374str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n" 375 .align 376#endif 377 378 .type __error_a, %function 379__error_a: 380#ifdef CONFIG_DEBUG_LL 381 mov r4, r1 @ preserve machine ID 382 adr r0, str_a1 383 bl printascii 384 mov r0, r4 385 bl printhex8 386 adr r0, str_a2 387 bl printascii 388 adr r3, 3f 389 ldmia r3, {r4, r5, r6} @ get machine desc list 390 sub r4, r3, r4 @ get offset between virt&phys 391 add r5, r5, r4 @ convert virt addresses to 392 add r6, r6, r4 @ physical address space 3931: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type 394 bl printhex8 395 mov r0, #'\t' 396 bl printch 397 ldr r0, [r5, #MACHINFO_NAME] @ get machine name 398 add r0, r0, r4 399 bl printascii 400 mov r0, #'\n' 401 bl printch 402 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc 403 cmp r5, r6 404 blo 1b 405 adr r0, str_a3 406 bl printascii 407 b __error 408str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x" 409str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n" 410str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n" 411 .align 412#endif 413 414 .type __error, %function 415__error: 416#ifdef CONFIG_ARCH_RPC 417/* 418 * Turn the screen red on a error - RiscPC only. 419 */ 420 mov r0, #0x02000000 421 mov r3, #0x11 422 orr r3, r3, r3, lsl #8 423 orr r3, r3, r3, lsl #16 424 str r3, [r0], #4 425 str r3, [r0], #4 426 str r3, [r0], #4 427 str r3, [r0], #4 428#endif 4291: mov r0, r0 430 b 1b 431 432 433/* 434 * Read processor ID register (CP#15, CR0), and look up in the linker-built 435 * supported processor list. Note that we can't use the absolute addresses 436 * for the __proc_info lists since we aren't running with the MMU on 437 * (and therefore, we are not in the correct address space). We have to 438 * calculate the offset. 439 * 440 * Returns: 441 * r3, r4, r6 corrupted 442 * r5 = proc_info pointer in physical address space 443 * r9 = cpuid 444 */ 445 .type __lookup_processor_type, %function 446__lookup_processor_type: 447 adr r3, 3f 448 ldmda r3, {r5, r6, r9} 449 sub r3, r3, r9 @ get offset between virt&phys 450 add r5, r5, r3 @ convert virt addresses to 451 add r6, r6, r3 @ physical address space 452 mrc p15, 0, r9, c0, c0 @ get processor id 4531: ldmia r5, {r3, r4} @ value, mask 454 and r4, r4, r9 @ mask wanted bits 455 teq r3, r4 456 beq 2f 457 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list) 458 cmp r5, r6 459 blo 1b 460 mov r5, #0 @ unknown processor 4612: mov pc, lr 462 463/* 464 * This provides a C-API version of the above function. 465 */ 466ENTRY(lookup_processor_type) 467 stmfd sp!, {r4 - r6, r9, lr} 468 bl __lookup_processor_type 469 mov r0, r5 470 ldmfd sp!, {r4 - r6, r9, pc} 471 472/* 473 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for 474 * more information about the __proc_info and __arch_info structures. 475 */ 476 .long __proc_info_begin 477 .long __proc_info_end 4783: .long . 479 .long __arch_info_begin 480 .long __arch_info_end 481 482/* 483 * Lookup machine architecture in the linker-build list of architectures. 484 * Note that we can't use the absolute addresses for the __arch_info 485 * lists since we aren't running with the MMU on (and therefore, we are 486 * not in the correct address space). We have to calculate the offset. 487 * 488 * r1 = machine architecture number 489 * Returns: 490 * r3, r4, r6 corrupted 491 * r5 = mach_info pointer in physical address space 492 */ 493 .type __lookup_machine_type, %function 494__lookup_machine_type: 495 adr r3, 3b 496 ldmia r3, {r4, r5, r6} 497 sub r3, r3, r4 @ get offset between virt&phys 498 add r5, r5, r3 @ convert virt addresses to 499 add r6, r6, r3 @ physical address space 5001: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type 501 teq r3, r1 @ matches loader number? 502 beq 2f @ found 503 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc 504 cmp r5, r6 505 blo 1b 506 mov r5, #0 @ unknown machine 5072: mov pc, lr 508 509/* 510 * This provides a C-API version of the above function. 511 */ 512ENTRY(lookup_machine_type) 513 stmfd sp!, {r4 - r6, lr} 514 mov r1, r0 515 bl __lookup_machine_type 516 mov r0, r5 517 ldmfd sp!, {r4 - r6, pc} 518