1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/domain.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/memory.h> 22#include <asm/thread_info.h> 23#include <asm/system.h> 24 25#ifdef CONFIG_DEBUG_LL 26#include <mach/debug-macro.S> 27#endif 28 29/* 30 * swapper_pg_dir is the virtual address of the initial page table. 31 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 32 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 33 * the least significant 16 bits to be 0x8000, but we could probably 34 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 35 */ 36#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 37#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 38#error KERNEL_RAM_VADDR must start at 0xXXXX8000 39#endif 40 41 .globl swapper_pg_dir 42 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 43 44 .macro pgtbl, rd, phys 45 add \rd, \phys, #TEXT_OFFSET - 0x4000 46 .endm 47 48#ifdef CONFIG_XIP_KERNEL 49#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 50#define KERNEL_END _edata_loc 51#else 52#define KERNEL_START KERNEL_RAM_VADDR 53#define KERNEL_END _end 54#endif 55 56/* 57 * Kernel startup entry point. 58 * --------------------------- 59 * 60 * This is normally called from the decompressor code. The requirements 61 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 62 * r1 = machine nr, r2 = atags or dtb pointer. 63 * 64 * This code is mostly position independent, so if you link the kernel at 65 * 0xc0008000, you call this at __pa(0xc0008000). 66 * 67 * See linux/arch/arm/tools/mach-types for the complete list of machine 68 * numbers for r1. 69 * 70 * We're trying to keep crap to a minimum; DO NOT add any machine specific 71 * crap here - that's what the boot loader (or in extreme, well justified 72 * circumstances, zImage) is for. 73 */ 74 .arm 75 76 __HEAD 77ENTRY(stext) 78 79 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. 80 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 81 THUMB( .thumb ) @ switch to Thumb now. 82 THUMB(1: ) 83 84 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode 85 @ and irqs disabled 86 mrc p15, 0, r9, c0, c0 @ get processor id 87 bl __lookup_processor_type @ r5=procinfo r9=cpuid 88 movs r10, r5 @ invalid processor (r5=0)? 89 THUMB( it eq ) @ force fixup-able long branch encoding 90 beq __error_p @ yes, error 'p' 91 92#ifndef CONFIG_XIP_KERNEL 93 adr r3, 2f 94 ldmia r3, {r4, r8} 95 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 96 add r8, r8, r4 @ PHYS_OFFSET 97#else 98 ldr r8, =PLAT_PHYS_OFFSET 99#endif 100 101 /* 102 * r1 = machine no, r2 = atags or dtb, 103 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 104 */ 105 bl __vet_atags 106#ifdef CONFIG_SMP_ON_UP 107 bl __fixup_smp 108#endif 109#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 110 bl __fixup_pv_table 111#endif 112 bl __create_page_tables 113 114 /* 115 * The following calls CPU specific code in a position independent 116 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 117 * xxx_proc_info structure selected by __lookup_processor_type 118 * above. On return, the CPU will be ready for the MMU to be 119 * turned on, and r0 will hold the CPU control register value. 120 */ 121 ldr r13, =__mmap_switched @ address to jump to after 122 @ mmu has been enabled 123 adr lr, BSYM(1f) @ return (PIC) address 124 mov r8, r4 @ set TTBR1 to swapper_pg_dir 125 ARM( add pc, r10, #PROCINFO_INITFUNC ) 126 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 127 THUMB( mov pc, r12 ) 1281: b __enable_mmu 129ENDPROC(stext) 130 .ltorg 131#ifndef CONFIG_XIP_KERNEL 1322: .long . 133 .long PAGE_OFFSET 134#endif 135 136/* 137 * Setup the initial page tables. We only setup the barest 138 * amount which are required to get the kernel running, which 139 * generally means mapping in the kernel code. 140 * 141 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 142 * 143 * Returns: 144 * r0, r3, r5-r7 corrupted 145 * r4 = physical page table address 146 */ 147__create_page_tables: 148 pgtbl r4, r8 @ page table address 149 150 /* 151 * Clear the 16K level 1 swapper page table 152 */ 153 mov r0, r4 154 mov r3, #0 155 add r6, r0, #0x4000 1561: str r3, [r0], #4 157 str r3, [r0], #4 158 str r3, [r0], #4 159 str r3, [r0], #4 160 teq r0, r6 161 bne 1b 162 163 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 164 165 /* 166 * Create identity mapping to cater for __enable_mmu. 167 * This identity mapping will be removed by paging_init(). 168 */ 169 adr r0, __enable_mmu_loc 170 ldmia r0, {r3, r5, r6} 171 sub r0, r0, r3 @ virt->phys offset 172 add r5, r5, r0 @ phys __enable_mmu 173 add r6, r6, r0 @ phys __enable_mmu_end 174 mov r5, r5, lsr #20 175 mov r6, r6, lsr #20 176 1771: orr r3, r7, r5, lsl #20 @ flags + kernel base 178 str r3, [r4, r5, lsl #2] @ identity mapping 179 teq r5, r6 180 addne r5, r5, #1 @ next section 181 bne 1b 182 183 /* 184 * Now setup the pagetables for our kernel direct 185 * mapped region. 186 */ 187 mov r3, pc 188 mov r3, r3, lsr #20 189 orr r3, r7, r3, lsl #20 190 add r0, r4, #(KERNEL_START & 0xff000000) >> 18 191 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! 192 ldr r6, =(KERNEL_END - 1) 193 add r0, r0, #4 194 add r6, r4, r6, lsr #18 1951: cmp r0, r6 196 add r3, r3, #1 << 20 197 strls r3, [r0], #4 198 bls 1b 199 200#ifdef CONFIG_XIP_KERNEL 201 /* 202 * Map some ram to cover our .data and .bss areas. 203 */ 204 add r3, r8, #TEXT_OFFSET 205 orr r3, r3, r7 206 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 207 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! 208 ldr r6, =(_end - 1) 209 add r0, r0, #4 210 add r6, r4, r6, lsr #18 2111: cmp r0, r6 212 add r3, r3, #1 << 20 213 strls r3, [r0], #4 214 bls 1b 215#endif 216 217 /* 218 * Then map boot params address in r2 or 219 * the first 1MB of ram if boot params address is not specified. 220 */ 221 mov r0, r2, lsr #20 222 movs r0, r0, lsl #20 223 moveq r0, r8 224 sub r3, r0, r8 225 add r3, r3, #PAGE_OFFSET 226 add r3, r4, r3, lsr #18 227 orr r6, r7, r0 228 str r6, [r3] 229 230#ifdef CONFIG_DEBUG_LL 231#ifndef CONFIG_DEBUG_ICEDCC 232 /* 233 * Map in IO space for serial debugging. 234 * This allows debug messages to be output 235 * via a serial console before paging_init. 236 */ 237 addruart r7, r3 238 239 mov r3, r3, lsr #20 240 mov r3, r3, lsl #2 241 242 add r0, r4, r3 243 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 244 cmp r3, #0x0800 @ limit to 512MB 245 movhi r3, #0x0800 246 add r6, r0, r3 247 mov r3, r7, lsr #20 248 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 249 orr r3, r7, r3, lsl #20 2501: str r3, [r0], #4 251 add r3, r3, #1 << 20 252 teq r0, r6 253 bne 1b 254 255#else /* CONFIG_DEBUG_ICEDCC */ 256 /* we don't need any serial debugging mappings for ICEDCC */ 257 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 258#endif /* !CONFIG_DEBUG_ICEDCC */ 259 260#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 261 /* 262 * If we're using the NetWinder or CATS, we also need to map 263 * in the 16550-type serial port for the debug messages 264 */ 265 add r0, r4, #0xff000000 >> 18 266 orr r3, r7, #0x7c000000 267 str r3, [r0] 268#endif 269#ifdef CONFIG_ARCH_RPC 270 /* 271 * Map in screen at 0x02000000 & SCREEN2_BASE 272 * Similar reasons here - for debug. This is 273 * only for Acorn RiscPC architectures. 274 */ 275 add r0, r4, #0x02000000 >> 18 276 orr r3, r7, #0x02000000 277 str r3, [r0] 278 add r0, r4, #0xd8000000 >> 18 279 str r3, [r0] 280#endif 281#endif 282 mov pc, lr 283ENDPROC(__create_page_tables) 284 .ltorg 285 .align 286__enable_mmu_loc: 287 .long . 288 .long __enable_mmu 289 .long __enable_mmu_end 290 291#if defined(CONFIG_SMP) 292 __CPUINIT 293ENTRY(secondary_startup) 294 /* 295 * Common entry point for secondary CPUs. 296 * 297 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 298 * the processor type - there is no need to check the machine type 299 * as it has already been validated by the primary processor. 300 */ 301 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 302 mrc p15, 0, r9, c0, c0 @ get processor id 303 bl __lookup_processor_type 304 movs r10, r5 @ invalid processor? 305 moveq r0, #'p' @ yes, error 'p' 306 THUMB( it eq ) @ force fixup-able long branch encoding 307 beq __error_p 308 309 /* 310 * Use the page tables supplied from __cpu_up. 311 */ 312 adr r4, __secondary_data 313 ldmia r4, {r5, r7, r12} @ address to jump to after 314 sub lr, r4, r5 @ mmu has been enabled 315 ldr r4, [r7, lr] @ get secondary_data.pgdir 316 add r7, r7, #4 317 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 318 adr lr, BSYM(__enable_mmu) @ return address 319 mov r13, r12 @ __secondary_switched address 320 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor 321 @ (return control reg) 322 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 323 THUMB( mov pc, r12 ) 324ENDPROC(secondary_startup) 325 326 /* 327 * r6 = &secondary_data 328 */ 329ENTRY(__secondary_switched) 330 ldr sp, [r7, #4] @ get secondary_data.stack 331 mov fp, #0 332 b secondary_start_kernel 333ENDPROC(__secondary_switched) 334 335 .align 336 337 .type __secondary_data, %object 338__secondary_data: 339 .long . 340 .long secondary_data 341 .long __secondary_switched 342#endif /* defined(CONFIG_SMP) */ 343 344 345 346/* 347 * Setup common bits before finally enabling the MMU. Essentially 348 * this is just loading the page table pointer and domain access 349 * registers. 350 * 351 * r0 = cp#15 control register 352 * r1 = machine ID 353 * r2 = atags or dtb pointer 354 * r4 = page table pointer 355 * r9 = processor ID 356 * r13 = *virtual* address to jump to upon completion 357 */ 358__enable_mmu: 359#ifdef CONFIG_ALIGNMENT_TRAP 360 orr r0, r0, #CR_A 361#else 362 bic r0, r0, #CR_A 363#endif 364#ifdef CONFIG_CPU_DCACHE_DISABLE 365 bic r0, r0, #CR_C 366#endif 367#ifdef CONFIG_CPU_BPREDICT_DISABLE 368 bic r0, r0, #CR_Z 369#endif 370#ifdef CONFIG_CPU_ICACHE_DISABLE 371 bic r0, r0, #CR_I 372#endif 373 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 374 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 375 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 376 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 377 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 378 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 379 b __turn_mmu_on 380ENDPROC(__enable_mmu) 381 382/* 383 * Enable the MMU. This completely changes the structure of the visible 384 * memory space. You will not be able to trace execution through this. 385 * If you have an enquiry about this, *please* check the linux-arm-kernel 386 * mailing list archives BEFORE sending another post to the list. 387 * 388 * r0 = cp#15 control register 389 * r1 = machine ID 390 * r2 = atags or dtb pointer 391 * r9 = processor ID 392 * r13 = *virtual* address to jump to upon completion 393 * 394 * other registers depend on the function called upon completion 395 */ 396 .align 5 397__turn_mmu_on: 398 mov r0, r0 399 mcr p15, 0, r0, c1, c0, 0 @ write control reg 400 mrc p15, 0, r3, c0, c0, 0 @ read id reg 401 mov r3, r3 402 mov r3, r13 403 mov pc, r3 404__enable_mmu_end: 405ENDPROC(__turn_mmu_on) 406 407 408#ifdef CONFIG_SMP_ON_UP 409 __INIT 410__fixup_smp: 411 and r3, r9, #0x000f0000 @ architecture version 412 teq r3, #0x000f0000 @ CPU ID supported? 413 bne __fixup_smp_on_up @ no, assume UP 414 415 bic r3, r9, #0x00ff0000 416 bic r3, r3, #0x0000000f @ mask 0xff00fff0 417 mov r4, #0x41000000 418 orr r4, r4, #0x0000b000 419 orr r4, r4, #0x00000020 @ val 0x4100b020 420 teq r3, r4 @ ARM 11MPCore? 421 moveq pc, lr @ yes, assume SMP 422 423 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 424 and r0, r0, #0xc0000000 @ multiprocessing extensions and 425 teq r0, #0x80000000 @ not part of a uniprocessor system? 426 moveq pc, lr @ yes, assume SMP 427 428__fixup_smp_on_up: 429 adr r0, 1f 430 ldmia r0, {r3 - r5} 431 sub r3, r0, r3 432 add r4, r4, r3 433 add r5, r5, r3 434 b __do_fixup_smp_on_up 435ENDPROC(__fixup_smp) 436 437 .align 4381: .word . 439 .word __smpalt_begin 440 .word __smpalt_end 441 442 .pushsection .data 443 .globl smp_on_up 444smp_on_up: 445 ALT_SMP(.long 1) 446 ALT_UP(.long 0) 447 .popsection 448#endif 449 450 .text 451__do_fixup_smp_on_up: 452 cmp r4, r5 453 movhs pc, lr 454 ldmia r4!, {r0, r6} 455 ARM( str r6, [r0, r3] ) 456 THUMB( add r0, r0, r3 ) 457#ifdef __ARMEB__ 458 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 459#endif 460 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 461 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 462 THUMB( strh r6, [r0] ) 463 b __do_fixup_smp_on_up 464ENDPROC(__do_fixup_smp_on_up) 465 466ENTRY(fixup_smp) 467 stmfd sp!, {r4 - r6, lr} 468 mov r4, r0 469 add r5, r0, r1 470 mov r3, #0 471 bl __do_fixup_smp_on_up 472 ldmfd sp!, {r4 - r6, pc} 473ENDPROC(fixup_smp) 474 475#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 476 477/* __fixup_pv_table - patch the stub instructions with the delta between 478 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 479 * can be expressed by an immediate shifter operand. The stub instruction 480 * has a form of '(add|sub) rd, rn, #imm'. 481 */ 482 __HEAD 483__fixup_pv_table: 484 adr r0, 1f 485 ldmia r0, {r3-r5, r7} 486 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 487 add r4, r4, r3 @ adjust table start address 488 add r5, r5, r3 @ adjust table end address 489 add r7, r7, r3 @ adjust __pv_phys_offset address 490 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset 491#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 492 mov r6, r3, lsr #24 @ constant for add/sub instructions 493 teq r3, r6, lsl #24 @ must be 16MiB aligned 494#else 495 mov r6, r3, lsr #16 @ constant for add/sub instructions 496 teq r3, r6, lsl #16 @ must be 64kiB aligned 497#endif 498THUMB( it ne @ cross section branch ) 499 bne __error 500 str r6, [r7, #4] @ save to __pv_offset 501 b __fixup_a_pv_table 502ENDPROC(__fixup_pv_table) 503 504 .align 5051: .long . 506 .long __pv_table_begin 507 .long __pv_table_end 5082: .long __pv_phys_offset 509 510 .text 511__fixup_a_pv_table: 512#ifdef CONFIG_THUMB2_KERNEL 513#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 514 lsls r0, r6, #24 515 lsr r6, #8 516 beq 1f 517 clz r7, r0 518 lsr r0, #24 519 lsl r0, r7 520 bic r0, 0x0080 521 lsrs r7, #1 522 orrcs r0, #0x0080 523 orr r0, r0, r7, lsl #12 524#endif 5251: lsls r6, #24 526 beq 4f 527 clz r7, r6 528 lsr r6, #24 529 lsl r6, r7 530 bic r6, #0x0080 531 lsrs r7, #1 532 orrcs r6, #0x0080 533 orr r6, r6, r7, lsl #12 534 orr r6, #0x4000 535 b 4f 5362: @ at this point the C flag is always clear 537 add r7, r3 538#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 539 ldrh ip, [r7] 540 tst ip, 0x0400 @ the i bit tells us LS or MS byte 541 beq 3f 542 cmp r0, #0 @ set C flag, and ... 543 biceq ip, 0x0400 @ immediate zero value has a special encoding 544 streqh ip, [r7] @ that requires the i bit cleared 545#endif 5463: ldrh ip, [r7, #2] 547 and ip, 0x8f00 548 orrcc ip, r6 @ mask in offset bits 31-24 549 orrcs ip, r0 @ mask in offset bits 23-16 550 strh ip, [r7, #2] 5514: cmp r4, r5 552 ldrcc r7, [r4], #4 @ use branch for delay slot 553 bcc 2b 554 bx lr 555#else 556#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT 557 and r0, r6, #255 @ offset bits 23-16 558 mov r6, r6, lsr #8 @ offset bits 31-24 559#else 560 mov r0, #0 @ just in case... 561#endif 562 b 3f 5632: ldr ip, [r7, r3] 564 bic ip, ip, #0x000000ff 565 tst ip, #0x400 @ rotate shift tells us LS or MS byte 566 orrne ip, ip, r6 @ mask in offset bits 31-24 567 orreq ip, ip, r0 @ mask in offset bits 23-16 568 str ip, [r7, r3] 5693: cmp r4, r5 570 ldrcc r7, [r4], #4 @ use branch for delay slot 571 bcc 2b 572 mov pc, lr 573#endif 574ENDPROC(__fixup_a_pv_table) 575 576ENTRY(fixup_pv_table) 577 stmfd sp!, {r4 - r7, lr} 578 ldr r2, 2f @ get address of __pv_phys_offset 579 mov r3, #0 @ no offset 580 mov r4, r0 @ r0 = table start 581 add r5, r0, r1 @ r1 = table size 582 ldr r6, [r2, #4] @ get __pv_offset 583 bl __fixup_a_pv_table 584 ldmfd sp!, {r4 - r7, pc} 585ENDPROC(fixup_pv_table) 586 587 .align 5882: .long __pv_phys_offset 589 590 .data 591 .globl __pv_phys_offset 592 .type __pv_phys_offset, %object 593__pv_phys_offset: 594 .long 0 595 .size __pv_phys_offset, . - __pv_phys_offset 596__pv_offset: 597 .long 0 598#endif 599 600#include "head-common.S" 601