1/* 2 * linux/arch/arm/kernel/head.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (c) 2003 ARM Limited 6 * All Rights Reserved 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Kernel startup code for all 32-bit CPUs 13 */ 14#include <linux/config.h> 15#include <linux/linkage.h> 16#include <linux/init.h> 17 18#include <asm/assembler.h> 19#include <asm/domain.h> 20#include <asm/procinfo.h> 21#include <asm/ptrace.h> 22#include <asm/asm-offsets.h> 23#include <asm/memory.h> 24#include <asm/thread_info.h> 25#include <asm/system.h> 26 27#define PROCINFO_MMUFLAGS 8 28#define PROCINFO_INITFUNC 12 29 30#define MACHINFO_TYPE 0 31#define MACHINFO_PHYSRAM 4 32#define MACHINFO_PHYSIO 8 33#define MACHINFO_PGOFFIO 12 34#define MACHINFO_NAME 16 35 36#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET) 37 38/* 39 * swapper_pg_dir is the virtual address of the initial page table. 40 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must 41 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect 42 * the least significant 16 bits to be 0x8000, but we could probably 43 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000. 44 */ 45#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000 46#error KERNEL_RAM_ADDR must start at 0xXXXX8000 47#endif 48 49 .globl swapper_pg_dir 50 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000 51 52 .macro pgtbl, rd 53 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000)) 54 .endm 55 56#ifdef CONFIG_XIP_KERNEL 57#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 58#else 59#define TEXTADDR KERNEL_RAM_ADDR 60#endif 61 62/* 63 * Kernel startup entry point. 64 * --------------------------- 65 * 66 * This is normally called from the decompressor code. The requirements 67 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 68 * r1 = machine nr. 69 * 70 * This code is mostly position independent, so if you link the kernel at 71 * 0xc0008000, you call this at __pa(0xc0008000). 72 * 73 * See linux/arch/arm/tools/mach-types for the complete list of machine 74 * numbers for r1. 75 * 76 * We're trying to keep crap to a minimum; DO NOT add any machine specific 77 * crap here - that's what the boot loader (or in extreme, well justified 78 * circumstances, zImage) is for. 79 */ 80 __INIT 81 .type stext, %function 82ENTRY(stext) 83 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode 84 @ and irqs disabled 85 bl __lookup_processor_type @ r5=procinfo r9=cpuid 86 movs r10, r5 @ invalid processor (r5=0)? 87 beq __error_p @ yes, error 'p' 88 bl __lookup_machine_type @ r5=machinfo 89 movs r8, r5 @ invalid machine (r5=0)? 90 beq __error_a @ yes, error 'a' 91 bl __create_page_tables 92 93 /* 94 * The following calls CPU specific code in a position independent 95 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 96 * xxx_proc_info structure selected by __lookup_machine_type 97 * above. On return, the CPU will be ready for the MMU to be 98 * turned on, and r0 will hold the CPU control register value. 99 */ 100 ldr r13, __switch_data @ address to jump to after 101 @ mmu has been enabled 102 adr lr, __enable_mmu @ return (PIC) address 103 add pc, r10, #PROCINFO_INITFUNC 104 105 .type __switch_data, %object 106__switch_data: 107 .long __mmap_switched 108 .long __data_loc @ r4 109 .long __data_start @ r5 110 .long __bss_start @ r6 111 .long _end @ r7 112 .long processor_id @ r4 113 .long __machine_arch_type @ r5 114 .long cr_alignment @ r6 115 .long init_thread_union + THREAD_START_SP @ sp 116 117/* 118 * The following fragment of code is executed with the MMU on, and uses 119 * absolute addresses; this is not position independent. 120 * 121 * r0 = cp#15 control register 122 * r1 = machine ID 123 * r9 = processor ID 124 */ 125 .type __mmap_switched, %function 126__mmap_switched: 127 adr r3, __switch_data + 4 128 129 ldmia r3!, {r4, r5, r6, r7} 130 cmp r4, r5 @ Copy data segment if needed 1311: cmpne r5, r6 132 ldrne fp, [r4], #4 133 strne fp, [r5], #4 134 bne 1b 135 136 mov fp, #0 @ Clear BSS (and zero fp) 1371: cmp r6, r7 138 strcc fp, [r6],#4 139 bcc 1b 140 141 ldmia r3, {r4, r5, r6, sp} 142 str r9, [r4] @ Save processor ID 143 str r1, [r5] @ Save machine type 144 bic r4, r0, #CR_A @ Clear 'A' bit 145 stmia r6, {r0, r4} @ Save control register values 146 b start_kernel 147 148#if defined(CONFIG_SMP) 149 .type secondary_startup, #function 150ENTRY(secondary_startup) 151 /* 152 * Common entry point for secondary CPUs. 153 * 154 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 155 * the processor type - there is no need to check the machine type 156 * as it has already been validated by the primary processor. 157 */ 158 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC 159 bl __lookup_processor_type 160 movs r10, r5 @ invalid processor? 161 moveq r0, #'p' @ yes, error 'p' 162 beq __error 163 164 /* 165 * Use the page tables supplied from __cpu_up. 166 */ 167 adr r4, __secondary_data 168 ldmia r4, {r5, r6, r13} @ address to jump to after 169 sub r4, r4, r5 @ mmu has been enabled 170 ldr r4, [r6, r4] @ get secondary_data.pgdir 171 adr lr, __enable_mmu @ return address 172 add pc, r10, #12 @ initialise processor 173 @ (return control reg) 174 175 /* 176 * r6 = &secondary_data 177 */ 178ENTRY(__secondary_switched) 179 ldr sp, [r6, #4] @ get secondary_data.stack 180 mov fp, #0 181 b secondary_start_kernel 182 183 .type __secondary_data, %object 184__secondary_data: 185 .long . 186 .long secondary_data 187 .long __secondary_switched 188#endif /* defined(CONFIG_SMP) */ 189 190 191 192/* 193 * Setup common bits before finally enabling the MMU. Essentially 194 * this is just loading the page table pointer and domain access 195 * registers. 196 */ 197 .type __enable_mmu, %function 198__enable_mmu: 199#ifdef CONFIG_ALIGNMENT_TRAP 200 orr r0, r0, #CR_A 201#else 202 bic r0, r0, #CR_A 203#endif 204#ifdef CONFIG_CPU_DCACHE_DISABLE 205 bic r0, r0, #CR_C 206#endif 207#ifdef CONFIG_CPU_BPREDICT_DISABLE 208 bic r0, r0, #CR_Z 209#endif 210#ifdef CONFIG_CPU_ICACHE_DISABLE 211 bic r0, r0, #CR_I 212#endif 213 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ 214 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 215 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ 216 domain_val(DOMAIN_IO, DOMAIN_CLIENT)) 217 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 218 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 219 b __turn_mmu_on 220 221/* 222 * Enable the MMU. This completely changes the structure of the visible 223 * memory space. You will not be able to trace execution through this. 224 * If you have an enquiry about this, *please* check the linux-arm-kernel 225 * mailing list archives BEFORE sending another post to the list. 226 * 227 * r0 = cp#15 control register 228 * r13 = *virtual* address to jump to upon completion 229 * 230 * other registers depend on the function called upon completion 231 */ 232 .align 5 233 .type __turn_mmu_on, %function 234__turn_mmu_on: 235 mov r0, r0 236 mcr p15, 0, r0, c1, c0, 0 @ write control reg 237 mrc p15, 0, r3, c0, c0, 0 @ read id reg 238 mov r3, r3 239 mov r3, r3 240 mov pc, r13 241 242 243 244/* 245 * Setup the initial page tables. We only setup the barest 246 * amount which are required to get the kernel running, which 247 * generally means mapping in the kernel code. 248 * 249 * r8 = machinfo 250 * r9 = cpuid 251 * r10 = procinfo 252 * 253 * Returns: 254 * r0, r3, r6, r7 corrupted 255 * r4 = physical page table address 256 */ 257 .type __create_page_tables, %function 258__create_page_tables: 259 pgtbl r4 @ page table address 260 261 /* 262 * Clear the 16K level 1 swapper page table 263 */ 264 mov r0, r4 265 mov r3, #0 266 add r6, r0, #0x4000 2671: str r3, [r0], #4 268 str r3, [r0], #4 269 str r3, [r0], #4 270 str r3, [r0], #4 271 teq r0, r6 272 bne 1b 273 274 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags 275 276 /* 277 * Create identity mapping for first MB of kernel to 278 * cater for the MMU enable. This identity mapping 279 * will be removed by paging_init(). We use our current program 280 * counter to determine corresponding section base address. 281 */ 282 mov r6, pc, lsr #20 @ start of kernel section 283 orr r3, r7, r6, lsl #20 @ flags + kernel base 284 str r3, [r4, r6, lsl #2] @ identity mapping 285 286 /* 287 * Now setup the pagetables for our kernel direct 288 * mapped region. We round TEXTADDR down to the 289 * nearest megabyte boundary. It is assumed that 290 * the kernel fits within 4 contigous 1MB sections. 291 */ 292 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel 293 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]! 294 add r3, r3, #1 << 20 295 str r3, [r0, #4]! @ KERNEL + 1MB 296 add r3, r3, #1 << 20 297 str r3, [r0, #4]! @ KERNEL + 2MB 298 add r3, r3, #1 << 20 299 str r3, [r0, #4] @ KERNEL + 3MB 300 301 /* 302 * Then map first 1MB of ram in case it contains our boot params. 303 */ 304 add r0, r4, #PAGE_OFFSET >> 18 305 orr r6, r7, #PHYS_OFFSET 306 str r6, [r0] 307 308#ifdef CONFIG_XIP_KERNEL 309 /* 310 * Map some ram to cover our .data and .bss areas. 311 * Mapping 3MB should be plenty. 312 */ 313 sub r3, r4, #PHYS_OFFSET 314 mov r3, r3, lsr #20 315 add r0, r0, r3, lsl #2 316 add r6, r6, r3, lsl #20 317 str r6, [r0], #4 318 add r6, r6, #(1 << 20) 319 str r6, [r0], #4 320 add r6, r6, #(1 << 20) 321 str r6, [r0] 322#endif 323 324#ifdef CONFIG_DEBUG_LL 325 bic r7, r7, #0x0c @ turn off cacheable 326 @ and bufferable bits 327 /* 328 * Map in IO space for serial debugging. 329 * This allows debug messages to be output 330 * via a serial console before paging_init. 331 */ 332 ldr r3, [r8, #MACHINFO_PGOFFIO] 333 add r0, r4, r3 334 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 335 cmp r3, #0x0800 @ limit to 512MB 336 movhi r3, #0x0800 337 add r6, r0, r3 338 ldr r3, [r8, #MACHINFO_PHYSIO] 339 orr r3, r3, r7 3401: str r3, [r0], #4 341 add r3, r3, #1 << 20 342 teq r0, r6 343 bne 1b 344#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 345 /* 346 * If we're using the NetWinder or CATS, we also need to map 347 * in the 16550-type serial port for the debug messages 348 */ 349 add r0, r4, #0xff000000 >> 18 350 orr r3, r7, #0x7c000000 351 str r3, [r0] 352#endif 353#ifdef CONFIG_ARCH_RPC 354 /* 355 * Map in screen at 0x02000000 & SCREEN2_BASE 356 * Similar reasons here - for debug. This is 357 * only for Acorn RiscPC architectures. 358 */ 359 add r0, r4, #0x02000000 >> 18 360 orr r3, r7, #0x02000000 361 str r3, [r0] 362 add r0, r4, #0xd8000000 >> 18 363 str r3, [r0] 364#endif 365#endif 366 mov pc, lr 367 .ltorg 368 369 370 371/* 372 * Exception handling. Something went wrong and we can't proceed. We 373 * ought to tell the user, but since we don't have any guarantee that 374 * we're even running on the right architecture, we do virtually nothing. 375 * 376 * If CONFIG_DEBUG_LL is set we try to print out something about the error 377 * and hope for the best (useful if bootloader fails to pass a proper 378 * machine ID for example). 379 */ 380 381 .type __error_p, %function 382__error_p: 383#ifdef CONFIG_DEBUG_LL 384 adr r0, str_p1 385 bl printascii 386 b __error 387str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n" 388 .align 389#endif 390 391 .type __error_a, %function 392__error_a: 393#ifdef CONFIG_DEBUG_LL 394 mov r4, r1 @ preserve machine ID 395 adr r0, str_a1 396 bl printascii 397 mov r0, r4 398 bl printhex8 399 adr r0, str_a2 400 bl printascii 401 adr r3, 3f 402 ldmia r3, {r4, r5, r6} @ get machine desc list 403 sub r4, r3, r4 @ get offset between virt&phys 404 add r5, r5, r4 @ convert virt addresses to 405 add r6, r6, r4 @ physical address space 4061: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type 407 bl printhex8 408 mov r0, #'\t' 409 bl printch 410 ldr r0, [r5, #MACHINFO_NAME] @ get machine name 411 add r0, r0, r4 412 bl printascii 413 mov r0, #'\n' 414 bl printch 415 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc 416 cmp r5, r6 417 blo 1b 418 adr r0, str_a3 419 bl printascii 420 b __error 421str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x" 422str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n" 423str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n" 424 .align 425#endif 426 427 .type __error, %function 428__error: 429#ifdef CONFIG_ARCH_RPC 430/* 431 * Turn the screen red on a error - RiscPC only. 432 */ 433 mov r0, #0x02000000 434 mov r3, #0x11 435 orr r3, r3, r3, lsl #8 436 orr r3, r3, r3, lsl #16 437 str r3, [r0], #4 438 str r3, [r0], #4 439 str r3, [r0], #4 440 str r3, [r0], #4 441#endif 4421: mov r0, r0 443 b 1b 444 445 446/* 447 * Read processor ID register (CP#15, CR0), and look up in the linker-built 448 * supported processor list. Note that we can't use the absolute addresses 449 * for the __proc_info lists since we aren't running with the MMU on 450 * (and therefore, we are not in the correct address space). We have to 451 * calculate the offset. 452 * 453 * Returns: 454 * r3, r4, r6 corrupted 455 * r5 = proc_info pointer in physical address space 456 * r9 = cpuid 457 */ 458 .type __lookup_processor_type, %function 459__lookup_processor_type: 460 adr r3, 3f 461 ldmda r3, {r5, r6, r9} 462 sub r3, r3, r9 @ get offset between virt&phys 463 add r5, r5, r3 @ convert virt addresses to 464 add r6, r6, r3 @ physical address space 465 mrc p15, 0, r9, c0, c0 @ get processor id 4661: ldmia r5, {r3, r4} @ value, mask 467 and r4, r4, r9 @ mask wanted bits 468 teq r3, r4 469 beq 2f 470 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list) 471 cmp r5, r6 472 blo 1b 473 mov r5, #0 @ unknown processor 4742: mov pc, lr 475 476/* 477 * This provides a C-API version of the above function. 478 */ 479ENTRY(lookup_processor_type) 480 stmfd sp!, {r4 - r6, r9, lr} 481 bl __lookup_processor_type 482 mov r0, r5 483 ldmfd sp!, {r4 - r6, r9, pc} 484 485/* 486 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for 487 * more information about the __proc_info and __arch_info structures. 488 */ 489 .long __proc_info_begin 490 .long __proc_info_end 4913: .long . 492 .long __arch_info_begin 493 .long __arch_info_end 494 495/* 496 * Lookup machine architecture in the linker-build list of architectures. 497 * Note that we can't use the absolute addresses for the __arch_info 498 * lists since we aren't running with the MMU on (and therefore, we are 499 * not in the correct address space). We have to calculate the offset. 500 * 501 * r1 = machine architecture number 502 * Returns: 503 * r3, r4, r6 corrupted 504 * r5 = mach_info pointer in physical address space 505 */ 506 .type __lookup_machine_type, %function 507__lookup_machine_type: 508 adr r3, 3b 509 ldmia r3, {r4, r5, r6} 510 sub r3, r3, r4 @ get offset between virt&phys 511 add r5, r5, r3 @ convert virt addresses to 512 add r6, r6, r3 @ physical address space 5131: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type 514 teq r3, r1 @ matches loader number? 515 beq 2f @ found 516 add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc 517 cmp r5, r6 518 blo 1b 519 mov r5, #0 @ unknown machine 5202: mov pc, lr 521 522/* 523 * This provides a C-API version of the above function. 524 */ 525ENTRY(lookup_machine_type) 526 stmfd sp!, {r4 - r6, lr} 527 mov r1, r0 528 bl __lookup_machine_type 529 mov r0, r5 530 ldmfd sp!, {r4 - r6, pc} 531