1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes 15 * it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <asm/arch/entry-macro.S> 22#include <asm/thread_notify.h> 23 24#include "entry-header.S" 25 26/* 27 * Interrupt handling. Preserves r7, r8, r9 28 */ 29 .macro irq_handler 301: get_irqnr_and_base r0, r6, r5, lr 31 movne r1, sp 32 @ 33 @ routine called with r0 = irq number, r1 = struct pt_regs * 34 @ 35 adrne lr, 1b 36 bne asm_do_IRQ 37 38#ifdef CONFIG_SMP 39 /* 40 * XXX 41 * 42 * this macro assumes that irqstat (r6) and base (r5) are 43 * preserved from get_irqnr_and_base above 44 */ 45 test_for_ipi r0, r6, r5, lr 46 movne r0, sp 47 adrne lr, 1b 48 bne do_IPI 49 50#ifdef CONFIG_LOCAL_TIMERS 51 test_for_ltirq r0, r6, r5, lr 52 movne r0, sp 53 adrne lr, 1b 54 bne do_local_timer 55#endif 56#endif 57 58 .endm 59 60/* 61 * Invalid mode handlers 62 */ 63 .macro inv_entry, reason 64 sub sp, sp, #S_FRAME_SIZE 65 stmib sp, {r1 - lr} 66 mov r1, #\reason 67 .endm 68 69__pabt_invalid: 70 inv_entry BAD_PREFETCH 71 b common_invalid 72 73__dabt_invalid: 74 inv_entry BAD_DATA 75 b common_invalid 76 77__irq_invalid: 78 inv_entry BAD_IRQ 79 b common_invalid 80 81__und_invalid: 82 inv_entry BAD_UNDEFINSTR 83 84 @ 85 @ XXX fall through to common_invalid 86 @ 87 88@ 89@ common_invalid - generic code for failed exception (re-entrant version of handlers) 90@ 91common_invalid: 92 zero_fp 93 94 ldmia r0, {r4 - r6} 95 add r0, sp, #S_PC @ here for interlock avoidance 96 mov r7, #-1 @ "" "" "" "" 97 str r4, [sp] @ save preserved r0 98 stmia r0, {r5 - r7} @ lr_<exception>, 99 @ cpsr_<exception>, "old_r0" 100 101 mov r0, sp 102 and r2, r6, #0x1f 103 b bad_mode 104 105/* 106 * SVC mode handlers 107 */ 108 109#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 110#define SPFIX(code...) code 111#else 112#define SPFIX(code...) 113#endif 114 115 .macro svc_entry 116 sub sp, sp, #S_FRAME_SIZE 117 SPFIX( tst sp, #4 ) 118 SPFIX( bicne sp, sp, #4 ) 119 stmib sp, {r1 - r12} 120 121 ldmia r0, {r1 - r3} 122 add r5, sp, #S_SP @ here for interlock avoidance 123 mov r4, #-1 @ "" "" "" "" 124 add r0, sp, #S_FRAME_SIZE @ "" "" "" "" 125 SPFIX( addne r0, r0, #4 ) 126 str r1, [sp] @ save the "real" r0 copied 127 @ from the exception stack 128 129 mov r1, lr 130 131 @ 132 @ We are now ready to fill in the remaining blanks on the stack: 133 @ 134 @ r0 - sp_svc 135 @ r1 - lr_svc 136 @ r2 - lr_<exception>, already fixed up for correct return/restart 137 @ r3 - spsr_<exception> 138 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 139 @ 140 stmia r5, {r0 - r4} 141 .endm 142 143 .align 5 144__dabt_svc: 145 svc_entry 146 147 @ 148 @ get ready to re-enable interrupts if appropriate 149 @ 150 mrs r9, cpsr 151 tst r3, #PSR_I_BIT 152 biceq r9, r9, #PSR_I_BIT 153 154 @ 155 @ Call the processor-specific abort handler: 156 @ 157 @ r2 - aborted context pc 158 @ r3 - aborted context cpsr 159 @ 160 @ The abort handler must return the aborted address in r0, and 161 @ the fault status register in r1. r9 must be preserved. 162 @ 163#ifdef MULTI_ABORT 164 ldr r4, .LCprocfns 165 mov lr, pc 166 ldr pc, [r4] 167#else 168 bl CPU_ABORT_HANDLER 169#endif 170 171 @ 172 @ set desired IRQ state, then call main handler 173 @ 174 msr cpsr_c, r9 175 mov r2, sp 176 bl do_DataAbort 177 178 @ 179 @ IRQs off again before pulling preserved data off the stack 180 @ 181 disable_irq 182 183 @ 184 @ restore SPSR and restart the instruction 185 @ 186 ldr r0, [sp, #S_PSR] 187 msr spsr_cxsf, r0 188 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 189 190 .align 5 191__irq_svc: 192 svc_entry 193 194#ifdef CONFIG_PREEMPT 195 get_thread_info tsk 196 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 197 add r7, r8, #1 @ increment it 198 str r7, [tsk, #TI_PREEMPT] 199#endif 200 201 irq_handler 202#ifdef CONFIG_PREEMPT 203 ldr r0, [tsk, #TI_FLAGS] @ get flags 204 tst r0, #_TIF_NEED_RESCHED 205 blne svc_preempt 206preempt_return: 207 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value 208 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 209 teq r0, r7 210 strne r0, [r0, -r0] @ bug() 211#endif 212 ldr r0, [sp, #S_PSR] @ irqs are already disabled 213 msr spsr_cxsf, r0 214 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 215 216 .ltorg 217 218#ifdef CONFIG_PREEMPT 219svc_preempt: 220 teq r8, #0 @ was preempt count = 0 221 ldreq r6, .LCirq_stat 222 movne pc, lr @ no 223 ldr r0, [r6, #4] @ local_irq_count 224 ldr r1, [r6, #8] @ local_bh_count 225 adds r0, r0, r1 226 movne pc, lr 227 mov r7, #0 @ preempt_schedule_irq 228 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 2291: bl preempt_schedule_irq @ irq en/disable is done inside 230 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 231 tst r0, #_TIF_NEED_RESCHED 232 beq preempt_return @ go again 233 b 1b 234#endif 235 236 .align 5 237__und_svc: 238 svc_entry 239 240 @ 241 @ call emulation code, which returns using r9 if it has emulated 242 @ the instruction, or the more conventional lr if we are to treat 243 @ this as a real undefined instruction 244 @ 245 @ r0 - instruction 246 @ 247 ldr r0, [r2, #-4] 248 adr r9, 1f 249 bl call_fpe 250 251 mov r0, sp @ struct pt_regs *regs 252 bl do_undefinstr 253 254 @ 255 @ IRQs off again before pulling preserved data off the stack 256 @ 2571: disable_irq 258 259 @ 260 @ restore SPSR and restart the instruction 261 @ 262 ldr lr, [sp, #S_PSR] @ Get SVC cpsr 263 msr spsr_cxsf, lr 264 ldmia sp, {r0 - pc}^ @ Restore SVC registers 265 266 .align 5 267__pabt_svc: 268 svc_entry 269 270 @ 271 @ re-enable interrupts if appropriate 272 @ 273 mrs r9, cpsr 274 tst r3, #PSR_I_BIT 275 biceq r9, r9, #PSR_I_BIT 276 msr cpsr_c, r9 277 278 @ 279 @ set args, then call main handler 280 @ 281 @ r0 - address of faulting instruction 282 @ r1 - pointer to registers on stack 283 @ 284 mov r0, r2 @ address (pc) 285 mov r1, sp @ regs 286 bl do_PrefetchAbort @ call abort handler 287 288 @ 289 @ IRQs off again before pulling preserved data off the stack 290 @ 291 disable_irq 292 293 @ 294 @ restore SPSR and restart the instruction 295 @ 296 ldr r0, [sp, #S_PSR] 297 msr spsr_cxsf, r0 298 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 299 300 .align 5 301.LCcralign: 302 .word cr_alignment 303#ifdef MULTI_ABORT 304.LCprocfns: 305 .word processor 306#endif 307.LCfp: 308 .word fp_enter 309#ifdef CONFIG_PREEMPT 310.LCirq_stat: 311 .word irq_stat 312#endif 313 314/* 315 * User mode handlers 316 * 317 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 318 */ 319 320#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 321#error "sizeof(struct pt_regs) must be a multiple of 8" 322#endif 323 324 .macro usr_entry 325 sub sp, sp, #S_FRAME_SIZE 326 stmib sp, {r1 - r12} 327 328 ldmia r0, {r1 - r3} 329 add r0, sp, #S_PC @ here for interlock avoidance 330 mov r4, #-1 @ "" "" "" "" 331 332 str r1, [sp] @ save the "real" r0 copied 333 @ from the exception stack 334 335#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 336#ifndef CONFIG_MMU 337#warning "NPTL on non MMU needs fixing" 338#else 339 @ make sure our user space atomic helper is aborted 340 cmp r2, #TASK_SIZE 341 bichs r3, r3, #PSR_Z_BIT 342#endif 343#endif 344 345 @ 346 @ We are now ready to fill in the remaining blanks on the stack: 347 @ 348 @ r2 - lr_<exception>, already fixed up for correct return/restart 349 @ r3 - spsr_<exception> 350 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 351 @ 352 @ Also, separately save sp_usr and lr_usr 353 @ 354 stmia r0, {r2 - r4} 355 stmdb r0, {sp, lr}^ 356 357 @ 358 @ Enable the alignment trap while in kernel mode 359 @ 360 alignment_trap r0 361 362 @ 363 @ Clear FP to mark the first stack frame 364 @ 365 zero_fp 366 .endm 367 368 .align 5 369__dabt_usr: 370 usr_entry 371 372 @ 373 @ Call the processor-specific abort handler: 374 @ 375 @ r2 - aborted context pc 376 @ r3 - aborted context cpsr 377 @ 378 @ The abort handler must return the aborted address in r0, and 379 @ the fault status register in r1. 380 @ 381#ifdef MULTI_ABORT 382 ldr r4, .LCprocfns 383 mov lr, pc 384 ldr pc, [r4] 385#else 386 bl CPU_ABORT_HANDLER 387#endif 388 389 @ 390 @ IRQs on, then call the main handler 391 @ 392 enable_irq 393 mov r2, sp 394 adr lr, ret_from_exception 395 b do_DataAbort 396 397 .align 5 398__irq_usr: 399 usr_entry 400 401 get_thread_info tsk 402#ifdef CONFIG_PREEMPT 403 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 404 add r7, r8, #1 @ increment it 405 str r7, [tsk, #TI_PREEMPT] 406#endif 407 408 irq_handler 409#ifdef CONFIG_PREEMPT 410 ldr r0, [tsk, #TI_PREEMPT] 411 str r8, [tsk, #TI_PREEMPT] 412 teq r0, r7 413 strne r0, [r0, -r0] 414#endif 415 416 mov why, #0 417 b ret_to_user 418 419 .ltorg 420 421 .align 5 422__und_usr: 423 usr_entry 424 425 tst r3, #PSR_T_BIT @ Thumb mode? 426 bne fpundefinstr @ ignore FP 427 sub r4, r2, #4 428 429 @ 430 @ fall through to the emulation code, which returns using r9 if 431 @ it has emulated the instruction, or the more conventional lr 432 @ if we are to treat this as a real undefined instruction 433 @ 434 @ r0 - instruction 435 @ 4361: ldrt r0, [r4] 437 adr r9, ret_from_exception 438 adr lr, fpundefinstr 439 @ 440 @ fallthrough to call_fpe 441 @ 442 443/* 444 * The out of line fixup for the ldrt above. 445 */ 446 .section .fixup, "ax" 4472: mov pc, r9 448 .previous 449 .section __ex_table,"a" 450 .long 1b, 2b 451 .previous 452 453/* 454 * Check whether the instruction is a co-processor instruction. 455 * If yes, we need to call the relevant co-processor handler. 456 * 457 * Note that we don't do a full check here for the co-processor 458 * instructions; all instructions with bit 27 set are well 459 * defined. The only instructions that should fault are the 460 * co-processor instructions. However, we have to watch out 461 * for the ARM6/ARM7 SWI bug. 462 * 463 * Emulators may wish to make use of the following registers: 464 * r0 = instruction opcode. 465 * r2 = PC+4 466 * r10 = this threads thread_info structure. 467 */ 468call_fpe: 469 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 470#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 471 and r8, r0, #0x0f000000 @ mask out op-code bits 472 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 473#endif 474 moveq pc, lr 475 get_thread_info r10 @ get current thread 476 and r8, r0, #0x00000f00 @ mask out CP number 477 mov r7, #1 478 add r6, r10, #TI_USED_CP 479 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] 480#ifdef CONFIG_IWMMXT 481 @ Test if we need to give access to iWMMXt coprocessors 482 ldr r5, [r10, #TI_FLAGS] 483 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 484 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 485 bcs iwmmxt_task_enable 486#endif 487 add pc, pc, r8, lsr #6 488 mov r0, r0 489 490 mov pc, lr @ CP#0 491 b do_fpe @ CP#1 (FPE) 492 b do_fpe @ CP#2 (FPE) 493 mov pc, lr @ CP#3 494#ifdef CONFIG_CRUNCH 495 b crunch_task_enable @ CP#4 (MaverickCrunch) 496 b crunch_task_enable @ CP#5 (MaverickCrunch) 497 b crunch_task_enable @ CP#6 (MaverickCrunch) 498#else 499 mov pc, lr @ CP#4 500 mov pc, lr @ CP#5 501 mov pc, lr @ CP#6 502#endif 503 mov pc, lr @ CP#7 504 mov pc, lr @ CP#8 505 mov pc, lr @ CP#9 506#ifdef CONFIG_VFP 507 b do_vfp @ CP#10 (VFP) 508 b do_vfp @ CP#11 (VFP) 509#else 510 mov pc, lr @ CP#10 (VFP) 511 mov pc, lr @ CP#11 (VFP) 512#endif 513 mov pc, lr @ CP#12 514 mov pc, lr @ CP#13 515 mov pc, lr @ CP#14 (Debug) 516 mov pc, lr @ CP#15 (Control) 517 518do_fpe: 519 enable_irq 520 ldr r4, .LCfp 521 add r10, r10, #TI_FPSTATE @ r10 = workspace 522 ldr pc, [r4] @ Call FP module USR entry point 523 524/* 525 * The FP module is called with these registers set: 526 * r0 = instruction 527 * r2 = PC+4 528 * r9 = normal "successful" return address 529 * r10 = FP workspace 530 * lr = unrecognised FP instruction return address 531 */ 532 533 .data 534ENTRY(fp_enter) 535 .word fpundefinstr 536 .text 537 538fpundefinstr: 539 mov r0, sp 540 adr lr, ret_from_exception 541 b do_undefinstr 542 543 .align 5 544__pabt_usr: 545 usr_entry 546 547 enable_irq @ Enable interrupts 548 mov r0, r2 @ address (pc) 549 mov r1, sp @ regs 550 bl do_PrefetchAbort @ call abort handler 551 /* fall through */ 552/* 553 * This is the return code to user mode for abort handlers 554 */ 555ENTRY(ret_from_exception) 556 get_thread_info tsk 557 mov why, #0 558 b ret_to_user 559 560/* 561 * Register switch for ARMv3 and ARMv4 processors 562 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 563 * previous and next are guaranteed not to be the same. 564 */ 565ENTRY(__switch_to) 566 add ip, r1, #TI_CPU_SAVE 567 ldr r3, [r2, #TI_TP_VALUE] 568 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack 569#ifdef CONFIG_MMU 570 ldr r6, [r2, #TI_CPU_DOMAIN] 571#endif 572#if __LINUX_ARM_ARCH__ >= 6 573#ifdef CONFIG_CPU_32v6K 574 clrex 575#else 576 strex r5, r4, [ip] @ Clear exclusive monitor 577#endif 578#endif 579#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT) 580 mra r4, r5, acc0 581 stmia ip, {r4, r5} 582#endif 583#if defined(CONFIG_HAS_TLS_REG) 584 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 585#elif !defined(CONFIG_TLS_REG_EMUL) 586 mov r4, #0xffff0fff 587 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 588#endif 589#ifdef CONFIG_MMU 590 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 591#endif 592#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT) 593 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra 594 ldmib r4, {r4, r5} 595 mar acc0, r4, r5 596#endif 597 mov r5, r0 598 add r4, r2, #TI_CPU_SAVE 599 ldr r0, =thread_notify_head 600 mov r1, #THREAD_NOTIFY_SWITCH 601 bl atomic_notifier_call_chain 602 mov r0, r5 603 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 604 605 __INIT 606 607/* 608 * User helpers. 609 * 610 * These are segment of kernel provided user code reachable from user space 611 * at a fixed address in kernel memory. This is used to provide user space 612 * with some operations which require kernel help because of unimplemented 613 * native feature and/or instructions in many ARM CPUs. The idea is for 614 * this code to be executed directly in user mode for best efficiency but 615 * which is too intimate with the kernel counter part to be left to user 616 * libraries. In fact this code might even differ from one CPU to another 617 * depending on the available instruction set and restrictions like on 618 * SMP systems. In other words, the kernel reserves the right to change 619 * this code as needed without warning. Only the entry points and their 620 * results are guaranteed to be stable. 621 * 622 * Each segment is 32-byte aligned and will be moved to the top of the high 623 * vector page. New segments (if ever needed) must be added in front of 624 * existing ones. This mechanism should be used only for things that are 625 * really small and justified, and not be abused freely. 626 * 627 * User space is expected to implement those things inline when optimizing 628 * for a processor that has the necessary native support, but only if such 629 * resulting binaries are already to be incompatible with earlier ARM 630 * processors due to the use of unsupported instructions other than what 631 * is provided here. In other words don't make binaries unable to run on 632 * earlier processors just for the sake of not using these kernel helpers 633 * if your compiled code is not going to use the new instructions for other 634 * purpose. 635 */ 636 637 .macro usr_ret, reg 638#ifdef CONFIG_ARM_THUMB 639 bx \reg 640#else 641 mov pc, \reg 642#endif 643 .endm 644 645 .align 5 646 .globl __kuser_helper_start 647__kuser_helper_start: 648 649/* 650 * Reference prototype: 651 * 652 * void __kernel_memory_barrier(void) 653 * 654 * Input: 655 * 656 * lr = return address 657 * 658 * Output: 659 * 660 * none 661 * 662 * Clobbered: 663 * 664 * the Z flag might be lost 665 * 666 * Definition and user space usage example: 667 * 668 * typedef void (__kernel_dmb_t)(void); 669 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 670 * 671 * Apply any needed memory barrier to preserve consistency with data modified 672 * manually and __kuser_cmpxchg usage. 673 * 674 * This could be used as follows: 675 * 676 * #define __kernel_dmb() \ 677 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 678 * : : : "r0", "lr","cc" ) 679 */ 680 681__kuser_memory_barrier: @ 0xffff0fa0 682 683#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) 684 mcr p15, 0, r0, c7, c10, 5 @ dmb 685#endif 686 usr_ret lr 687 688 .align 5 689 690/* 691 * Reference prototype: 692 * 693 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 694 * 695 * Input: 696 * 697 * r0 = oldval 698 * r1 = newval 699 * r2 = ptr 700 * lr = return address 701 * 702 * Output: 703 * 704 * r0 = returned value (zero or non-zero) 705 * C flag = set if r0 == 0, clear if r0 != 0 706 * 707 * Clobbered: 708 * 709 * r3, ip, flags 710 * 711 * Definition and user space usage example: 712 * 713 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 714 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 715 * 716 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 717 * Return zero if *ptr was changed or non-zero if no exchange happened. 718 * The C flag is also set if *ptr was changed to allow for assembly 719 * optimization in the calling code. 720 * 721 * Notes: 722 * 723 * - This routine already includes memory barriers as needed. 724 * 725 * - A failure might be transient, i.e. it is possible, although unlikely, 726 * that "failure" be returned even if *ptr == oldval. 727 * 728 * For example, a user space atomic_add implementation could look like this: 729 * 730 * #define atomic_add(ptr, val) \ 731 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 732 * register unsigned int __result asm("r1"); \ 733 * asm volatile ( \ 734 * "1: @ atomic_add\n\t" \ 735 * "ldr r0, [r2]\n\t" \ 736 * "mov r3, #0xffff0fff\n\t" \ 737 * "add lr, pc, #4\n\t" \ 738 * "add r1, r0, %2\n\t" \ 739 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 740 * "bcc 1b" \ 741 * : "=&r" (__result) \ 742 * : "r" (__ptr), "rIL" (val) \ 743 * : "r0","r3","ip","lr","cc","memory" ); \ 744 * __result; }) 745 */ 746 747__kuser_cmpxchg: @ 0xffff0fc0 748 749#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 750 751 /* 752 * Poor you. No fast solution possible... 753 * The kernel itself must perform the operation. 754 * A special ghost syscall is used for that (see traps.c). 755 */ 756 stmfd sp!, {r7, lr} 757 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 758 orr r7, r7, #0xf0 759 swi #0x9ffff0 760 ldmfd sp!, {r7, pc} 761 762#elif __LINUX_ARM_ARCH__ < 6 763 764 /* 765 * Theory of operation: 766 * 767 * We set the Z flag before loading oldval. If ever an exception 768 * occurs we can not be sure the loaded value will still be the same 769 * when the exception returns, therefore the user exception handler 770 * will clear the Z flag whenever the interrupted user code was 771 * actually from the kernel address space (see the usr_entry macro). 772 * 773 * The post-increment on the str is used to prevent a race with an 774 * exception happening just after the str instruction which would 775 * clear the Z flag although the exchange was done. 776 */ 777#ifdef CONFIG_MMU 778 teq ip, ip @ set Z flag 779 ldr ip, [r2] @ load current val 780 add r3, r2, #1 @ prepare store ptr 781 teqeq ip, r0 @ compare with oldval if still allowed 782 streq r1, [r3, #-1]! @ store newval if still allowed 783 subs r0, r2, r3 @ if r2 == r3 the str occured 784#else 785#warning "NPTL on non MMU needs fixing" 786 mov r0, #-1 787 adds r0, r0, #0 788#endif 789 usr_ret lr 790 791#else 792 793#ifdef CONFIG_SMP 794 mcr p15, 0, r0, c7, c10, 5 @ dmb 795#endif 796 ldrex r3, [r2] 797 subs r3, r3, r0 798 strexeq r3, r1, [r2] 799 rsbs r0, r3, #0 800#ifdef CONFIG_SMP 801 mcr p15, 0, r0, c7, c10, 5 @ dmb 802#endif 803 usr_ret lr 804 805#endif 806 807 .align 5 808 809/* 810 * Reference prototype: 811 * 812 * int __kernel_get_tls(void) 813 * 814 * Input: 815 * 816 * lr = return address 817 * 818 * Output: 819 * 820 * r0 = TLS value 821 * 822 * Clobbered: 823 * 824 * the Z flag might be lost 825 * 826 * Definition and user space usage example: 827 * 828 * typedef int (__kernel_get_tls_t)(void); 829 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 830 * 831 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 832 * 833 * This could be used as follows: 834 * 835 * #define __kernel_get_tls() \ 836 * ({ register unsigned int __val asm("r0"); \ 837 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 838 * : "=r" (__val) : : "lr","cc" ); \ 839 * __val; }) 840 */ 841 842__kuser_get_tls: @ 0xffff0fe0 843 844#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 845 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 846#else 847 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 848#endif 849 usr_ret lr 850 851 .rep 5 852 .word 0 @ pad up to __kuser_helper_version 853 .endr 854 855/* 856 * Reference declaration: 857 * 858 * extern unsigned int __kernel_helper_version; 859 * 860 * Definition and user space usage example: 861 * 862 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 863 * 864 * User space may read this to determine the curent number of helpers 865 * available. 866 */ 867 868__kuser_helper_version: @ 0xffff0ffc 869 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 870 871 .globl __kuser_helper_end 872__kuser_helper_end: 873 874 875/* 876 * Vector stubs. 877 * 878 * This code is copied to 0xffff0200 so we can use branches in the 879 * vectors, rather than ldr's. Note that this code must not 880 * exceed 0x300 bytes. 881 * 882 * Common stub entry macro: 883 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 884 * 885 * SP points to a minimal amount of processor-private memory, the address 886 * of which is copied into r0 for the mode specific abort handler. 887 */ 888 .macro vector_stub, name, mode, correction=0 889 .align 5 890 891vector_\name: 892 .if \correction 893 sub lr, lr, #\correction 894 .endif 895 896 @ 897 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 898 @ (parent CPSR) 899 @ 900 stmia sp, {r0, lr} @ save r0, lr 901 mrs lr, spsr 902 str lr, [sp, #8] @ save spsr 903 904 @ 905 @ Prepare for SVC32 mode. IRQs remain disabled. 906 @ 907 mrs r0, cpsr 908 eor r0, r0, #(\mode ^ SVC_MODE) 909 msr spsr_cxsf, r0 910 911 @ 912 @ the branch table must immediately follow this code 913 @ 914 and lr, lr, #0x0f 915 mov r0, sp 916 ldr lr, [pc, lr, lsl #2] 917 movs pc, lr @ branch to handler in SVC mode 918 .endm 919 920 .globl __stubs_start 921__stubs_start: 922/* 923 * Interrupt dispatcher 924 */ 925 vector_stub irq, IRQ_MODE, 4 926 927 .long __irq_usr @ 0 (USR_26 / USR_32) 928 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 929 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 930 .long __irq_svc @ 3 (SVC_26 / SVC_32) 931 .long __irq_invalid @ 4 932 .long __irq_invalid @ 5 933 .long __irq_invalid @ 6 934 .long __irq_invalid @ 7 935 .long __irq_invalid @ 8 936 .long __irq_invalid @ 9 937 .long __irq_invalid @ a 938 .long __irq_invalid @ b 939 .long __irq_invalid @ c 940 .long __irq_invalid @ d 941 .long __irq_invalid @ e 942 .long __irq_invalid @ f 943 944/* 945 * Data abort dispatcher 946 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 947 */ 948 vector_stub dabt, ABT_MODE, 8 949 950 .long __dabt_usr @ 0 (USR_26 / USR_32) 951 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 952 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 953 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 954 .long __dabt_invalid @ 4 955 .long __dabt_invalid @ 5 956 .long __dabt_invalid @ 6 957 .long __dabt_invalid @ 7 958 .long __dabt_invalid @ 8 959 .long __dabt_invalid @ 9 960 .long __dabt_invalid @ a 961 .long __dabt_invalid @ b 962 .long __dabt_invalid @ c 963 .long __dabt_invalid @ d 964 .long __dabt_invalid @ e 965 .long __dabt_invalid @ f 966 967/* 968 * Prefetch abort dispatcher 969 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 970 */ 971 vector_stub pabt, ABT_MODE, 4 972 973 .long __pabt_usr @ 0 (USR_26 / USR_32) 974 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 975 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 976 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 977 .long __pabt_invalid @ 4 978 .long __pabt_invalid @ 5 979 .long __pabt_invalid @ 6 980 .long __pabt_invalid @ 7 981 .long __pabt_invalid @ 8 982 .long __pabt_invalid @ 9 983 .long __pabt_invalid @ a 984 .long __pabt_invalid @ b 985 .long __pabt_invalid @ c 986 .long __pabt_invalid @ d 987 .long __pabt_invalid @ e 988 .long __pabt_invalid @ f 989 990/* 991 * Undef instr entry dispatcher 992 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 993 */ 994 vector_stub und, UND_MODE 995 996 .long __und_usr @ 0 (USR_26 / USR_32) 997 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 998 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 999 .long __und_svc @ 3 (SVC_26 / SVC_32) 1000 .long __und_invalid @ 4 1001 .long __und_invalid @ 5 1002 .long __und_invalid @ 6 1003 .long __und_invalid @ 7 1004 .long __und_invalid @ 8 1005 .long __und_invalid @ 9 1006 .long __und_invalid @ a 1007 .long __und_invalid @ b 1008 .long __und_invalid @ c 1009 .long __und_invalid @ d 1010 .long __und_invalid @ e 1011 .long __und_invalid @ f 1012 1013 .align 5 1014 1015/*============================================================================= 1016 * Undefined FIQs 1017 *----------------------------------------------------------------------------- 1018 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1019 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1020 * Basically to switch modes, we *HAVE* to clobber one register... brain 1021 * damage alert! I don't think that we can execute any code in here in any 1022 * other mode than FIQ... Ok you can switch to another mode, but you can't 1023 * get out of that mode without clobbering one register. 1024 */ 1025vector_fiq: 1026 disable_fiq 1027 subs pc, lr, #4 1028 1029/*============================================================================= 1030 * Address exception handler 1031 *----------------------------------------------------------------------------- 1032 * These aren't too critical. 1033 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1034 */ 1035 1036vector_addrexcptn: 1037 b vector_addrexcptn 1038 1039/* 1040 * We group all the following data together to optimise 1041 * for CPUs with separate I & D caches. 1042 */ 1043 .align 5 1044 1045.LCvswi: 1046 .word vector_swi 1047 1048 .globl __stubs_end 1049__stubs_end: 1050 1051 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1052 1053 .globl __vectors_start 1054__vectors_start: 1055 swi SYS_ERROR0 1056 b vector_und + stubs_offset 1057 ldr pc, .LCvswi + stubs_offset 1058 b vector_pabt + stubs_offset 1059 b vector_dabt + stubs_offset 1060 b vector_addrexcptn + stubs_offset 1061 b vector_irq + stubs_offset 1062 b vector_fiq + stubs_offset 1063 1064 .globl __vectors_end 1065__vectors_end: 1066 1067 .data 1068 1069 .globl cr_alignment 1070 .globl cr_no_alignment 1071cr_alignment: 1072 .space 4 1073cr_no_alignment: 1074 .space 4 1075