1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/assembler.h> 19#include <asm/memory.h> 20#include <asm/glue-df.h> 21#include <asm/glue-pf.h> 22#include <asm/vfpmacros.h> 23#ifndef CONFIG_MULTI_IRQ_HANDLER 24#include <mach/entry-macro.S> 25#endif 26#include <asm/thread_notify.h> 27#include <asm/unwind.h> 28#include <asm/unistd.h> 29#include <asm/tls.h> 30#include <asm/system_info.h> 31 32#include "entry-header.S" 33#include <asm/entry-macro-multi.S> 34#include <asm/probes.h> 35 36/* 37 * Interrupt handling. 38 */ 39 .macro irq_handler 40#ifdef CONFIG_MULTI_IRQ_HANDLER 41 ldr r1, =handle_arch_irq 42 mov r0, sp 43 adr lr, BSYM(9997f) 44 ldr pc, [r1] 45#else 46 arch_irq_handler_default 47#endif 489997: 49 .endm 50 51 .macro pabt_helper 52 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 53#ifdef MULTI_PABORT 54 ldr ip, .LCprocfns 55 mov lr, pc 56 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 57#else 58 bl CPU_PABORT_HANDLER 59#endif 60 .endm 61 62 .macro dabt_helper 63 64 @ 65 @ Call the processor-specific abort handler: 66 @ 67 @ r2 - pt_regs 68 @ r4 - aborted context pc 69 @ r5 - aborted context psr 70 @ 71 @ The abort handler must return the aborted address in r0, and 72 @ the fault status register in r1. r9 must be preserved. 73 @ 74#ifdef MULTI_DABORT 75 ldr ip, .LCprocfns 76 mov lr, pc 77 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 78#else 79 bl CPU_DABORT_HANDLER 80#endif 81 .endm 82 83#ifdef CONFIG_KPROBES 84 .section .kprobes.text,"ax",%progbits 85#else 86 .text 87#endif 88 89/* 90 * Invalid mode handlers 91 */ 92 .macro inv_entry, reason 93 sub sp, sp, #S_FRAME_SIZE 94 ARM( stmib sp, {r1 - lr} ) 95 THUMB( stmia sp, {r0 - r12} ) 96 THUMB( str sp, [sp, #S_SP] ) 97 THUMB( str lr, [sp, #S_LR] ) 98 mov r1, #\reason 99 .endm 100 101__pabt_invalid: 102 inv_entry BAD_PREFETCH 103 b common_invalid 104ENDPROC(__pabt_invalid) 105 106__dabt_invalid: 107 inv_entry BAD_DATA 108 b common_invalid 109ENDPROC(__dabt_invalid) 110 111__irq_invalid: 112 inv_entry BAD_IRQ 113 b common_invalid 114ENDPROC(__irq_invalid) 115 116__und_invalid: 117 inv_entry BAD_UNDEFINSTR 118 119 @ 120 @ XXX fall through to common_invalid 121 @ 122 123@ 124@ common_invalid - generic code for failed exception (re-entrant version of handlers) 125@ 126common_invalid: 127 zero_fp 128 129 ldmia r0, {r4 - r6} 130 add r0, sp, #S_PC @ here for interlock avoidance 131 mov r7, #-1 @ "" "" "" "" 132 str r4, [sp] @ save preserved r0 133 stmia r0, {r5 - r7} @ lr_<exception>, 134 @ cpsr_<exception>, "old_r0" 135 136 mov r0, sp 137 b bad_mode 138ENDPROC(__und_invalid) 139 140/* 141 * SVC mode handlers 142 */ 143 144#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 145#define SPFIX(code...) code 146#else 147#define SPFIX(code...) 148#endif 149 150 .macro svc_entry, stack_hole=0, trace=1 151 UNWIND(.fnstart ) 152 UNWIND(.save {r0 - pc} ) 153 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 154#ifdef CONFIG_THUMB2_KERNEL 155 SPFIX( str r0, [sp] ) @ temporarily saved 156 SPFIX( mov r0, sp ) 157 SPFIX( tst r0, #4 ) @ test original stack alignment 158 SPFIX( ldr r0, [sp] ) @ restored 159#else 160 SPFIX( tst sp, #4 ) 161#endif 162 SPFIX( subeq sp, sp, #4 ) 163 stmia sp, {r1 - r12} 164 165 ldmia r0, {r3 - r5} 166 add r7, sp, #S_SP - 4 @ here for interlock avoidance 167 mov r6, #-1 @ "" "" "" "" 168 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) 169 SPFIX( addeq r2, r2, #4 ) 170 str r3, [sp, #-4]! @ save the "real" r0 copied 171 @ from the exception stack 172 173 mov r3, lr 174 175 @ 176 @ We are now ready to fill in the remaining blanks on the stack: 177 @ 178 @ r2 - sp_svc 179 @ r3 - lr_svc 180 @ r4 - lr_<exception>, already fixed up for correct return/restart 181 @ r5 - spsr_<exception> 182 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 183 @ 184 stmia r7, {r2 - r6} 185 186 .if \trace 187#ifdef CONFIG_TRACE_IRQFLAGS 188 bl trace_hardirqs_off 189#endif 190 .endif 191 .endm 192 193 .align 5 194__dabt_svc: 195 svc_entry 196 mov r2, sp 197 dabt_helper 198 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 199 svc_exit r5 @ return from exception 200 UNWIND(.fnend ) 201ENDPROC(__dabt_svc) 202 203 .align 5 204__irq_svc: 205 svc_entry 206 irq_handler 207 208#ifdef CONFIG_PREEMPT 209 get_thread_info tsk 210 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 211 ldr r0, [tsk, #TI_FLAGS] @ get flags 212 teq r8, #0 @ if preempt count != 0 213 movne r0, #0 @ force flags to 0 214 tst r0, #_TIF_NEED_RESCHED 215 blne svc_preempt 216#endif 217 218 svc_exit r5, irq = 1 @ return from exception 219 UNWIND(.fnend ) 220ENDPROC(__irq_svc) 221 222 .ltorg 223 224#ifdef CONFIG_PREEMPT 225svc_preempt: 226 mov r8, lr 2271: bl preempt_schedule_irq @ irq en/disable is done inside 228 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 229 tst r0, #_TIF_NEED_RESCHED 230 reteq r8 @ go again 231 b 1b 232#endif 233 234__und_fault: 235 @ Correct the PC such that it is pointing at the instruction 236 @ which caused the fault. If the faulting instruction was ARM 237 @ the PC will be pointing at the next instruction, and have to 238 @ subtract 4. Otherwise, it is Thumb, and the PC will be 239 @ pointing at the second half of the Thumb instruction. We 240 @ have to subtract 2. 241 ldr r2, [r0, #S_PC] 242 sub r2, r2, r1 243 str r2, [r0, #S_PC] 244 b do_undefinstr 245ENDPROC(__und_fault) 246 247 .align 5 248__und_svc: 249#ifdef CONFIG_KPROBES 250 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 251 @ it obviously needs free stack space which then will belong to 252 @ the saved context. 253 svc_entry MAX_STACK_SIZE 254#else 255 svc_entry 256#endif 257 @ 258 @ call emulation code, which returns using r9 if it has emulated 259 @ the instruction, or the more conventional lr if we are to treat 260 @ this as a real undefined instruction 261 @ 262 @ r0 - instruction 263 @ 264#ifndef CONFIG_THUMB2_KERNEL 265 ldr r0, [r4, #-4] 266#else 267 mov r1, #2 268 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 269 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 270 blo __und_svc_fault 271 ldrh r9, [r4] @ bottom 16 bits 272 add r4, r4, #2 273 str r4, [sp, #S_PC] 274 orr r0, r9, r0, lsl #16 275#endif 276 adr r9, BSYM(__und_svc_finish) 277 mov r2, r4 278 bl call_fpe 279 280 mov r1, #4 @ PC correction to apply 281__und_svc_fault: 282 mov r0, sp @ struct pt_regs *regs 283 bl __und_fault 284 285__und_svc_finish: 286 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 287 svc_exit r5 @ return from exception 288 UNWIND(.fnend ) 289ENDPROC(__und_svc) 290 291 .align 5 292__pabt_svc: 293 svc_entry 294 mov r2, sp @ regs 295 pabt_helper 296 svc_exit r5 @ return from exception 297 UNWIND(.fnend ) 298ENDPROC(__pabt_svc) 299 300 .align 5 301__fiq_svc: 302 svc_entry trace=0 303 mov r0, sp @ struct pt_regs *regs 304 bl handle_fiq_as_nmi 305 svc_exit_via_fiq 306 UNWIND(.fnend ) 307ENDPROC(__fiq_svc) 308 309 .align 5 310.LCcralign: 311 .word cr_alignment 312#ifdef MULTI_DABORT 313.LCprocfns: 314 .word processor 315#endif 316.LCfp: 317 .word fp_enter 318 319/* 320 * Abort mode handlers 321 */ 322 323@ 324@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 325@ and reuses the same macros. However in abort mode we must also 326@ save/restore lr_abt and spsr_abt to make nested aborts safe. 327@ 328 .align 5 329__fiq_abt: 330 svc_entry trace=0 331 332 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 333 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 334 THUMB( msr cpsr_c, r0 ) 335 mov r1, lr @ Save lr_abt 336 mrs r2, spsr @ Save spsr_abt, abort is now safe 337 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 338 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 339 THUMB( msr cpsr_c, r0 ) 340 stmfd sp!, {r1 - r2} 341 342 add r0, sp, #8 @ struct pt_regs *regs 343 bl handle_fiq_as_nmi 344 345 ldmfd sp!, {r1 - r2} 346 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 347 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 348 THUMB( msr cpsr_c, r0 ) 349 mov lr, r1 @ Restore lr_abt, abort is unsafe 350 msr spsr_cxsf, r2 @ Restore spsr_abt 351 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 352 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 353 THUMB( msr cpsr_c, r0 ) 354 355 svc_exit_via_fiq 356 UNWIND(.fnend ) 357ENDPROC(__fiq_abt) 358 359/* 360 * User mode handlers 361 * 362 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 363 */ 364 365#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 366#error "sizeof(struct pt_regs) must be a multiple of 8" 367#endif 368 369 .macro usr_entry, trace=1 370 UNWIND(.fnstart ) 371 UNWIND(.cantunwind ) @ don't unwind the user space 372 sub sp, sp, #S_FRAME_SIZE 373 ARM( stmib sp, {r1 - r12} ) 374 THUMB( stmia sp, {r0 - r12} ) 375 376 ATRAP( mrc p15, 0, r7, c1, c0, 0) 377 ATRAP( ldr r8, .LCcralign) 378 379 ldmia r0, {r3 - r5} 380 add r0, sp, #S_PC @ here for interlock avoidance 381 mov r6, #-1 @ "" "" "" "" 382 383 str r3, [sp] @ save the "real" r0 copied 384 @ from the exception stack 385 386 ATRAP( ldr r8, [r8, #0]) 387 388 @ 389 @ We are now ready to fill in the remaining blanks on the stack: 390 @ 391 @ r4 - lr_<exception>, already fixed up for correct return/restart 392 @ r5 - spsr_<exception> 393 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 394 @ 395 @ Also, separately save sp_usr and lr_usr 396 @ 397 stmia r0, {r4 - r6} 398 ARM( stmdb r0, {sp, lr}^ ) 399 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 400 401 @ Enable the alignment trap while in kernel mode 402 ATRAP( teq r8, r7) 403 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 404 405 @ 406 @ Clear FP to mark the first stack frame 407 @ 408 zero_fp 409 410 .if \trace 411#ifdef CONFIG_IRQSOFF_TRACER 412 bl trace_hardirqs_off 413#endif 414 ct_user_exit save = 0 415 .endif 416 .endm 417 418 .macro kuser_cmpxchg_check 419#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \ 420 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 421#ifndef CONFIG_MMU 422#warning "NPTL on non MMU needs fixing" 423#else 424 @ Make sure our user space atomic helper is restarted 425 @ if it was interrupted in a critical region. Here we 426 @ perform a quick test inline since it should be false 427 @ 99.9999% of the time. The rest is done out of line. 428 cmp r4, #TASK_SIZE 429 blhs kuser_cmpxchg64_fixup 430#endif 431#endif 432 .endm 433 434 .align 5 435__dabt_usr: 436 usr_entry 437 kuser_cmpxchg_check 438 mov r2, sp 439 dabt_helper 440 b ret_from_exception 441 UNWIND(.fnend ) 442ENDPROC(__dabt_usr) 443 444 .align 5 445__irq_usr: 446 usr_entry 447 kuser_cmpxchg_check 448 irq_handler 449 get_thread_info tsk 450 mov why, #0 451 b ret_to_user_from_irq 452 UNWIND(.fnend ) 453ENDPROC(__irq_usr) 454 455 .ltorg 456 457 .align 5 458__und_usr: 459 usr_entry 460 461 mov r2, r4 462 mov r3, r5 463 464 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 465 @ faulting instruction depending on Thumb mode. 466 @ r3 = regs->ARM_cpsr 467 @ 468 @ The emulation code returns using r9 if it has emulated the 469 @ instruction, or the more conventional lr if we are to treat 470 @ this as a real undefined instruction 471 @ 472 adr r9, BSYM(ret_from_exception) 473 474 @ IRQs must be enabled before attempting to read the instruction from 475 @ user space since that could cause a page/translation fault if the 476 @ page table was modified by another CPU. 477 enable_irq 478 479 tst r3, #PSR_T_BIT @ Thumb mode? 480 bne __und_usr_thumb 481 sub r4, r2, #4 @ ARM instr at LR - 4 4821: ldrt r0, [r4] 483 ARM_BE8(rev r0, r0) @ little endian instruction 484 485 @ r0 = 32-bit ARM instruction which caused the exception 486 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 487 @ r4 = PC value for the faulting instruction 488 @ lr = 32-bit undefined instruction function 489 adr lr, BSYM(__und_usr_fault_32) 490 b call_fpe 491 492__und_usr_thumb: 493 @ Thumb instruction 494 sub r4, r2, #2 @ First half of thumb instr at LR - 2 495#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 496/* 497 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 498 * can never be supported in a single kernel, this code is not applicable at 499 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 500 * made about .arch directives. 501 */ 502#if __LINUX_ARM_ARCH__ < 7 503/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 504#define NEED_CPU_ARCHITECTURE 505 ldr r5, .LCcpu_architecture 506 ldr r5, [r5] 507 cmp r5, #CPU_ARCH_ARMv7 508 blo __und_usr_fault_16 @ 16bit undefined instruction 509/* 510 * The following code won't get run unless the running CPU really is v7, so 511 * coding round the lack of ldrht on older arches is pointless. Temporarily 512 * override the assembler target arch with the minimum required instead: 513 */ 514 .arch armv6t2 515#endif 5162: ldrht r5, [r4] 517ARM_BE8(rev16 r5, r5) @ little endian instruction 518 cmp r5, #0xe800 @ 32bit instruction if xx != 0 519 blo __und_usr_fault_16 @ 16bit undefined instruction 5203: ldrht r0, [r2] 521ARM_BE8(rev16 r0, r0) @ little endian instruction 522 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 523 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 524 orr r0, r0, r5, lsl #16 525 adr lr, BSYM(__und_usr_fault_32) 526 @ r0 = the two 16-bit Thumb instructions which caused the exception 527 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 528 @ r4 = PC value for the first 16-bit Thumb instruction 529 @ lr = 32bit undefined instruction function 530 531#if __LINUX_ARM_ARCH__ < 7 532/* If the target arch was overridden, change it back: */ 533#ifdef CONFIG_CPU_32v6K 534 .arch armv6k 535#else 536 .arch armv6 537#endif 538#endif /* __LINUX_ARM_ARCH__ < 7 */ 539#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 540 b __und_usr_fault_16 541#endif 542 UNWIND(.fnend) 543ENDPROC(__und_usr) 544 545/* 546 * The out of line fixup for the ldrt instructions above. 547 */ 548 .pushsection .fixup, "ax" 549 .align 2 5504: str r4, [sp, #S_PC] @ retry current instruction 551 ret r9 552 .popsection 553 .pushsection __ex_table,"a" 554 .long 1b, 4b 555#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 556 .long 2b, 4b 557 .long 3b, 4b 558#endif 559 .popsection 560 561/* 562 * Check whether the instruction is a co-processor instruction. 563 * If yes, we need to call the relevant co-processor handler. 564 * 565 * Note that we don't do a full check here for the co-processor 566 * instructions; all instructions with bit 27 set are well 567 * defined. The only instructions that should fault are the 568 * co-processor instructions. However, we have to watch out 569 * for the ARM6/ARM7 SWI bug. 570 * 571 * NEON is a special case that has to be handled here. Not all 572 * NEON instructions are co-processor instructions, so we have 573 * to make a special case of checking for them. Plus, there's 574 * five groups of them, so we have a table of mask/opcode pairs 575 * to check against, and if any match then we branch off into the 576 * NEON handler code. 577 * 578 * Emulators may wish to make use of the following registers: 579 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 580 * r2 = PC value to resume execution after successful emulation 581 * r9 = normal "successful" return address 582 * r10 = this threads thread_info structure 583 * lr = unrecognised instruction return address 584 * IRQs enabled, FIQs enabled. 585 */ 586 @ 587 @ Fall-through from Thumb-2 __und_usr 588 @ 589#ifdef CONFIG_NEON 590 get_thread_info r10 @ get current thread 591 adr r6, .LCneon_thumb_opcodes 592 b 2f 593#endif 594call_fpe: 595 get_thread_info r10 @ get current thread 596#ifdef CONFIG_NEON 597 adr r6, .LCneon_arm_opcodes 5982: ldr r5, [r6], #4 @ mask value 599 ldr r7, [r6], #4 @ opcode bits matching in mask 600 cmp r5, #0 @ end mask? 601 beq 1f 602 and r8, r0, r5 603 cmp r8, r7 @ NEON instruction? 604 bne 2b 605 mov r7, #1 606 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 607 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 608 b do_vfp @ let VFP handler handle this 6091: 610#endif 611 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 612 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 613 reteq lr 614 and r8, r0, #0x00000f00 @ mask out CP number 615 THUMB( lsr r8, r8, #8 ) 616 mov r7, #1 617 add r6, r10, #TI_USED_CP 618 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 619 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 620#ifdef CONFIG_IWMMXT 621 @ Test if we need to give access to iWMMXt coprocessors 622 ldr r5, [r10, #TI_FLAGS] 623 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 624 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 625 bcs iwmmxt_task_enable 626#endif 627 ARM( add pc, pc, r8, lsr #6 ) 628 THUMB( lsl r8, r8, #2 ) 629 THUMB( add pc, r8 ) 630 nop 631 632 ret.w lr @ CP#0 633 W(b) do_fpe @ CP#1 (FPE) 634 W(b) do_fpe @ CP#2 (FPE) 635 ret.w lr @ CP#3 636#ifdef CONFIG_CRUNCH 637 b crunch_task_enable @ CP#4 (MaverickCrunch) 638 b crunch_task_enable @ CP#5 (MaverickCrunch) 639 b crunch_task_enable @ CP#6 (MaverickCrunch) 640#else 641 ret.w lr @ CP#4 642 ret.w lr @ CP#5 643 ret.w lr @ CP#6 644#endif 645 ret.w lr @ CP#7 646 ret.w lr @ CP#8 647 ret.w lr @ CP#9 648#ifdef CONFIG_VFP 649 W(b) do_vfp @ CP#10 (VFP) 650 W(b) do_vfp @ CP#11 (VFP) 651#else 652 ret.w lr @ CP#10 (VFP) 653 ret.w lr @ CP#11 (VFP) 654#endif 655 ret.w lr @ CP#12 656 ret.w lr @ CP#13 657 ret.w lr @ CP#14 (Debug) 658 ret.w lr @ CP#15 (Control) 659 660#ifdef NEED_CPU_ARCHITECTURE 661 .align 2 662.LCcpu_architecture: 663 .word __cpu_architecture 664#endif 665 666#ifdef CONFIG_NEON 667 .align 6 668 669.LCneon_arm_opcodes: 670 .word 0xfe000000 @ mask 671 .word 0xf2000000 @ opcode 672 673 .word 0xff100000 @ mask 674 .word 0xf4000000 @ opcode 675 676 .word 0x00000000 @ mask 677 .word 0x00000000 @ opcode 678 679.LCneon_thumb_opcodes: 680 .word 0xef000000 @ mask 681 .word 0xef000000 @ opcode 682 683 .word 0xff100000 @ mask 684 .word 0xf9000000 @ opcode 685 686 .word 0x00000000 @ mask 687 .word 0x00000000 @ opcode 688#endif 689 690do_fpe: 691 ldr r4, .LCfp 692 add r10, r10, #TI_FPSTATE @ r10 = workspace 693 ldr pc, [r4] @ Call FP module USR entry point 694 695/* 696 * The FP module is called with these registers set: 697 * r0 = instruction 698 * r2 = PC+4 699 * r9 = normal "successful" return address 700 * r10 = FP workspace 701 * lr = unrecognised FP instruction return address 702 */ 703 704 .pushsection .data 705ENTRY(fp_enter) 706 .word no_fp 707 .popsection 708 709ENTRY(no_fp) 710 ret lr 711ENDPROC(no_fp) 712 713__und_usr_fault_32: 714 mov r1, #4 715 b 1f 716__und_usr_fault_16: 717 mov r1, #2 7181: mov r0, sp 719 adr lr, BSYM(ret_from_exception) 720 b __und_fault 721ENDPROC(__und_usr_fault_32) 722ENDPROC(__und_usr_fault_16) 723 724 .align 5 725__pabt_usr: 726 usr_entry 727 mov r2, sp @ regs 728 pabt_helper 729 UNWIND(.fnend ) 730 /* fall through */ 731/* 732 * This is the return code to user mode for abort handlers 733 */ 734ENTRY(ret_from_exception) 735 UNWIND(.fnstart ) 736 UNWIND(.cantunwind ) 737 get_thread_info tsk 738 mov why, #0 739 b ret_to_user 740 UNWIND(.fnend ) 741ENDPROC(__pabt_usr) 742ENDPROC(ret_from_exception) 743 744 .align 5 745__fiq_usr: 746 usr_entry trace=0 747 kuser_cmpxchg_check 748 mov r0, sp @ struct pt_regs *regs 749 bl handle_fiq_as_nmi 750 get_thread_info tsk 751 restore_user_regs fast = 0, offset = 0 752 UNWIND(.fnend ) 753ENDPROC(__fiq_usr) 754 755/* 756 * Register switch for ARMv3 and ARMv4 processors 757 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 758 * previous and next are guaranteed not to be the same. 759 */ 760ENTRY(__switch_to) 761 UNWIND(.fnstart ) 762 UNWIND(.cantunwind ) 763 add ip, r1, #TI_CPU_SAVE 764 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 765 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 766 THUMB( str sp, [ip], #4 ) 767 THUMB( str lr, [ip], #4 ) 768 ldr r4, [r2, #TI_TP_VALUE] 769 ldr r5, [r2, #TI_TP_VALUE + 4] 770#ifdef CONFIG_CPU_USE_DOMAINS 771 ldr r6, [r2, #TI_CPU_DOMAIN] 772#endif 773 switch_tls r1, r4, r5, r3, r7 774#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 775 ldr r7, [r2, #TI_TASK] 776 ldr r8, =__stack_chk_guard 777 ldr r7, [r7, #TSK_STACK_CANARY] 778#endif 779#ifdef CONFIG_CPU_USE_DOMAINS 780 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 781#endif 782 mov r5, r0 783 add r4, r2, #TI_CPU_SAVE 784 ldr r0, =thread_notify_head 785 mov r1, #THREAD_NOTIFY_SWITCH 786 bl atomic_notifier_call_chain 787#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 788 str r7, [r8] 789#endif 790 THUMB( mov ip, r4 ) 791 mov r0, r5 792 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 793 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 794 THUMB( ldr sp, [ip], #4 ) 795 THUMB( ldr pc, [ip] ) 796 UNWIND(.fnend ) 797ENDPROC(__switch_to) 798 799 __INIT 800 801/* 802 * User helpers. 803 * 804 * Each segment is 32-byte aligned and will be moved to the top of the high 805 * vector page. New segments (if ever needed) must be added in front of 806 * existing ones. This mechanism should be used only for things that are 807 * really small and justified, and not be abused freely. 808 * 809 * See Documentation/arm/kernel_user_helpers.txt for formal definitions. 810 */ 811 THUMB( .arm ) 812 813 .macro usr_ret, reg 814#ifdef CONFIG_ARM_THUMB 815 bx \reg 816#else 817 ret \reg 818#endif 819 .endm 820 821 .macro kuser_pad, sym, size 822 .if (. - \sym) & 3 823 .rept 4 - (. - \sym) & 3 824 .byte 0 825 .endr 826 .endif 827 .rept (\size - (. - \sym)) / 4 828 .word 0xe7fddef1 829 .endr 830 .endm 831 832#ifdef CONFIG_KUSER_HELPERS 833 .align 5 834 .globl __kuser_helper_start 835__kuser_helper_start: 836 837/* 838 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 839 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 840 */ 841 842__kuser_cmpxchg64: @ 0xffff0f60 843 844#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 845 846 /* 847 * Poor you. No fast solution possible... 848 * The kernel itself must perform the operation. 849 * A special ghost syscall is used for that (see traps.c). 850 */ 851 stmfd sp!, {r7, lr} 852 ldr r7, 1f @ it's 20 bits 853 swi __ARM_NR_cmpxchg64 854 ldmfd sp!, {r7, pc} 8551: .word __ARM_NR_cmpxchg64 856 857#elif defined(CONFIG_CPU_32v6K) 858 859 stmfd sp!, {r4, r5, r6, r7} 860 ldrd r4, r5, [r0] @ load old val 861 ldrd r6, r7, [r1] @ load new val 862 smp_dmb arm 8631: ldrexd r0, r1, [r2] @ load current val 864 eors r3, r0, r4 @ compare with oldval (1) 865 eoreqs r3, r1, r5 @ compare with oldval (2) 866 strexdeq r3, r6, r7, [r2] @ store newval if eq 867 teqeq r3, #1 @ success? 868 beq 1b @ if no then retry 869 smp_dmb arm 870 rsbs r0, r3, #0 @ set returned val and C flag 871 ldmfd sp!, {r4, r5, r6, r7} 872 usr_ret lr 873 874#elif !defined(CONFIG_SMP) 875 876#ifdef CONFIG_MMU 877 878 /* 879 * The only thing that can break atomicity in this cmpxchg64 880 * implementation is either an IRQ or a data abort exception 881 * causing another process/thread to be scheduled in the middle of 882 * the critical sequence. The same strategy as for cmpxchg is used. 883 */ 884 stmfd sp!, {r4, r5, r6, lr} 885 ldmia r0, {r4, r5} @ load old val 886 ldmia r1, {r6, lr} @ load new val 8871: ldmia r2, {r0, r1} @ load current val 888 eors r3, r0, r4 @ compare with oldval (1) 889 eoreqs r3, r1, r5 @ compare with oldval (2) 8902: stmeqia r2, {r6, lr} @ store newval if eq 891 rsbs r0, r3, #0 @ set return val and C flag 892 ldmfd sp!, {r4, r5, r6, pc} 893 894 .text 895kuser_cmpxchg64_fixup: 896 @ Called from kuser_cmpxchg_fixup. 897 @ r4 = address of interrupted insn (must be preserved). 898 @ sp = saved regs. r7 and r8 are clobbered. 899 @ 1b = first critical insn, 2b = last critical insn. 900 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 901 mov r7, #0xffff0fff 902 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 903 subs r8, r4, r7 904 rsbcss r8, r8, #(2b - 1b) 905 strcs r7, [sp, #S_PC] 906#if __LINUX_ARM_ARCH__ < 6 907 bcc kuser_cmpxchg32_fixup 908#endif 909 ret lr 910 .previous 911 912#else 913#warning "NPTL on non MMU needs fixing" 914 mov r0, #-1 915 adds r0, r0, #0 916 usr_ret lr 917#endif 918 919#else 920#error "incoherent kernel configuration" 921#endif 922 923 kuser_pad __kuser_cmpxchg64, 64 924 925__kuser_memory_barrier: @ 0xffff0fa0 926 smp_dmb arm 927 usr_ret lr 928 929 kuser_pad __kuser_memory_barrier, 32 930 931__kuser_cmpxchg: @ 0xffff0fc0 932 933#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 934 935 /* 936 * Poor you. No fast solution possible... 937 * The kernel itself must perform the operation. 938 * A special ghost syscall is used for that (see traps.c). 939 */ 940 stmfd sp!, {r7, lr} 941 ldr r7, 1f @ it's 20 bits 942 swi __ARM_NR_cmpxchg 943 ldmfd sp!, {r7, pc} 9441: .word __ARM_NR_cmpxchg 945 946#elif __LINUX_ARM_ARCH__ < 6 947 948#ifdef CONFIG_MMU 949 950 /* 951 * The only thing that can break atomicity in this cmpxchg 952 * implementation is either an IRQ or a data abort exception 953 * causing another process/thread to be scheduled in the middle 954 * of the critical sequence. To prevent this, code is added to 955 * the IRQ and data abort exception handlers to set the pc back 956 * to the beginning of the critical section if it is found to be 957 * within that critical section (see kuser_cmpxchg_fixup). 958 */ 9591: ldr r3, [r2] @ load current val 960 subs r3, r3, r0 @ compare with oldval 9612: streq r1, [r2] @ store newval if eq 962 rsbs r0, r3, #0 @ set return val and C flag 963 usr_ret lr 964 965 .text 966kuser_cmpxchg32_fixup: 967 @ Called from kuser_cmpxchg_check macro. 968 @ r4 = address of interrupted insn (must be preserved). 969 @ sp = saved regs. r7 and r8 are clobbered. 970 @ 1b = first critical insn, 2b = last critical insn. 971 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 972 mov r7, #0xffff0fff 973 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 974 subs r8, r4, r7 975 rsbcss r8, r8, #(2b - 1b) 976 strcs r7, [sp, #S_PC] 977 ret lr 978 .previous 979 980#else 981#warning "NPTL on non MMU needs fixing" 982 mov r0, #-1 983 adds r0, r0, #0 984 usr_ret lr 985#endif 986 987#else 988 989 smp_dmb arm 9901: ldrex r3, [r2] 991 subs r3, r3, r0 992 strexeq r3, r1, [r2] 993 teqeq r3, #1 994 beq 1b 995 rsbs r0, r3, #0 996 /* beware -- each __kuser slot must be 8 instructions max */ 997 ALT_SMP(b __kuser_memory_barrier) 998 ALT_UP(usr_ret lr) 999 1000#endif 1001 1002 kuser_pad __kuser_cmpxchg, 32 1003 1004__kuser_get_tls: @ 0xffff0fe0 1005 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1006 usr_ret lr 1007 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1008 kuser_pad __kuser_get_tls, 16 1009 .rep 3 1010 .word 0 @ 0xffff0ff0 software TLS value, then 1011 .endr @ pad up to __kuser_helper_version 1012 1013__kuser_helper_version: @ 0xffff0ffc 1014 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1015 1016 .globl __kuser_helper_end 1017__kuser_helper_end: 1018 1019#endif 1020 1021 THUMB( .thumb ) 1022 1023/* 1024 * Vector stubs. 1025 * 1026 * This code is copied to 0xffff1000 so we can use branches in the 1027 * vectors, rather than ldr's. Note that this code must not exceed 1028 * a page size. 1029 * 1030 * Common stub entry macro: 1031 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1032 * 1033 * SP points to a minimal amount of processor-private memory, the address 1034 * of which is copied into r0 for the mode specific abort handler. 1035 */ 1036 .macro vector_stub, name, mode, correction=0 1037 .align 5 1038 1039vector_\name: 1040 .if \correction 1041 sub lr, lr, #\correction 1042 .endif 1043 1044 @ 1045 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1046 @ (parent CPSR) 1047 @ 1048 stmia sp, {r0, lr} @ save r0, lr 1049 mrs lr, spsr 1050 str lr, [sp, #8] @ save spsr 1051 1052 @ 1053 @ Prepare for SVC32 mode. IRQs remain disabled. 1054 @ 1055 mrs r0, cpsr 1056 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1057 msr spsr_cxsf, r0 1058 1059 @ 1060 @ the branch table must immediately follow this code 1061 @ 1062 and lr, lr, #0x0f 1063 THUMB( adr r0, 1f ) 1064 THUMB( ldr lr, [r0, lr, lsl #2] ) 1065 mov r0, sp 1066 ARM( ldr lr, [pc, lr, lsl #2] ) 1067 movs pc, lr @ branch to handler in SVC mode 1068ENDPROC(vector_\name) 1069 1070 .align 2 1071 @ handler addresses follow this label 10721: 1073 .endm 1074 1075 .section .stubs, "ax", %progbits 1076__stubs_start: 1077 @ This must be the first word 1078 .word vector_swi 1079 1080vector_rst: 1081 ARM( swi SYS_ERROR0 ) 1082 THUMB( svc #0 ) 1083 THUMB( nop ) 1084 b vector_und 1085 1086/* 1087 * Interrupt dispatcher 1088 */ 1089 vector_stub irq, IRQ_MODE, 4 1090 1091 .long __irq_usr @ 0 (USR_26 / USR_32) 1092 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1093 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1094 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1095 .long __irq_invalid @ 4 1096 .long __irq_invalid @ 5 1097 .long __irq_invalid @ 6 1098 .long __irq_invalid @ 7 1099 .long __irq_invalid @ 8 1100 .long __irq_invalid @ 9 1101 .long __irq_invalid @ a 1102 .long __irq_invalid @ b 1103 .long __irq_invalid @ c 1104 .long __irq_invalid @ d 1105 .long __irq_invalid @ e 1106 .long __irq_invalid @ f 1107 1108/* 1109 * Data abort dispatcher 1110 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1111 */ 1112 vector_stub dabt, ABT_MODE, 8 1113 1114 .long __dabt_usr @ 0 (USR_26 / USR_32) 1115 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1116 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1117 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1118 .long __dabt_invalid @ 4 1119 .long __dabt_invalid @ 5 1120 .long __dabt_invalid @ 6 1121 .long __dabt_invalid @ 7 1122 .long __dabt_invalid @ 8 1123 .long __dabt_invalid @ 9 1124 .long __dabt_invalid @ a 1125 .long __dabt_invalid @ b 1126 .long __dabt_invalid @ c 1127 .long __dabt_invalid @ d 1128 .long __dabt_invalid @ e 1129 .long __dabt_invalid @ f 1130 1131/* 1132 * Prefetch abort dispatcher 1133 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1134 */ 1135 vector_stub pabt, ABT_MODE, 4 1136 1137 .long __pabt_usr @ 0 (USR_26 / USR_32) 1138 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1139 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1140 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1141 .long __pabt_invalid @ 4 1142 .long __pabt_invalid @ 5 1143 .long __pabt_invalid @ 6 1144 .long __pabt_invalid @ 7 1145 .long __pabt_invalid @ 8 1146 .long __pabt_invalid @ 9 1147 .long __pabt_invalid @ a 1148 .long __pabt_invalid @ b 1149 .long __pabt_invalid @ c 1150 .long __pabt_invalid @ d 1151 .long __pabt_invalid @ e 1152 .long __pabt_invalid @ f 1153 1154/* 1155 * Undef instr entry dispatcher 1156 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1157 */ 1158 vector_stub und, UND_MODE 1159 1160 .long __und_usr @ 0 (USR_26 / USR_32) 1161 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1162 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1163 .long __und_svc @ 3 (SVC_26 / SVC_32) 1164 .long __und_invalid @ 4 1165 .long __und_invalid @ 5 1166 .long __und_invalid @ 6 1167 .long __und_invalid @ 7 1168 .long __und_invalid @ 8 1169 .long __und_invalid @ 9 1170 .long __und_invalid @ a 1171 .long __und_invalid @ b 1172 .long __und_invalid @ c 1173 .long __und_invalid @ d 1174 .long __und_invalid @ e 1175 .long __und_invalid @ f 1176 1177 .align 5 1178 1179/*============================================================================= 1180 * Address exception handler 1181 *----------------------------------------------------------------------------- 1182 * These aren't too critical. 1183 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1184 */ 1185 1186vector_addrexcptn: 1187 b vector_addrexcptn 1188 1189/*============================================================================= 1190 * FIQ "NMI" handler 1191 *----------------------------------------------------------------------------- 1192 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1193 * systems. 1194 */ 1195 vector_stub fiq, FIQ_MODE, 4 1196 1197 .long __fiq_usr @ 0 (USR_26 / USR_32) 1198 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1199 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1200 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1201 .long __fiq_svc @ 4 1202 .long __fiq_svc @ 5 1203 .long __fiq_svc @ 6 1204 .long __fiq_abt @ 7 1205 .long __fiq_svc @ 8 1206 .long __fiq_svc @ 9 1207 .long __fiq_svc @ a 1208 .long __fiq_svc @ b 1209 .long __fiq_svc @ c 1210 .long __fiq_svc @ d 1211 .long __fiq_svc @ e 1212 .long __fiq_svc @ f 1213 1214 .globl vector_fiq_offset 1215 .equ vector_fiq_offset, vector_fiq 1216 1217 .section .vectors, "ax", %progbits 1218__vectors_start: 1219 W(b) vector_rst 1220 W(b) vector_und 1221 W(ldr) pc, __vectors_start + 0x1000 1222 W(b) vector_pabt 1223 W(b) vector_dabt 1224 W(b) vector_addrexcptn 1225 W(b) vector_irq 1226 W(b) vector_fiq 1227 1228 .data 1229 1230 .globl cr_alignment 1231cr_alignment: 1232 .space 4 1233 1234#ifdef CONFIG_MULTI_IRQ_HANDLER 1235 .globl handle_arch_irq 1236handle_arch_irq: 1237 .space 4 1238#endif 1239