1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/assembler.h> 19#include <asm/memory.h> 20#include <asm/glue-df.h> 21#include <asm/glue-pf.h> 22#include <asm/vfpmacros.h> 23#ifndef CONFIG_MULTI_IRQ_HANDLER 24#include <mach/entry-macro.S> 25#endif 26#include <asm/thread_notify.h> 27#include <asm/unwind.h> 28#include <asm/unistd.h> 29#include <asm/tls.h> 30#include <asm/system_info.h> 31 32#include "entry-header.S" 33#include <asm/entry-macro-multi.S> 34 35/* 36 * Interrupt handling. 37 */ 38 .macro irq_handler 39#ifdef CONFIG_MULTI_IRQ_HANDLER 40 ldr r1, =handle_arch_irq 41 mov r0, sp 42 adr lr, BSYM(9997f) 43 ldr pc, [r1] 44#else 45 arch_irq_handler_default 46#endif 479997: 48 .endm 49 50 .macro pabt_helper 51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 52#ifdef MULTI_PABORT 53 ldr ip, .LCprocfns 54 mov lr, pc 55 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 56#else 57 bl CPU_PABORT_HANDLER 58#endif 59 .endm 60 61 .macro dabt_helper 62 63 @ 64 @ Call the processor-specific abort handler: 65 @ 66 @ r2 - pt_regs 67 @ r4 - aborted context pc 68 @ r5 - aborted context psr 69 @ 70 @ The abort handler must return the aborted address in r0, and 71 @ the fault status register in r1. r9 must be preserved. 72 @ 73#ifdef MULTI_DABORT 74 ldr ip, .LCprocfns 75 mov lr, pc 76 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 77#else 78 bl CPU_DABORT_HANDLER 79#endif 80 .endm 81 82#ifdef CONFIG_KPROBES 83 .section .kprobes.text,"ax",%progbits 84#else 85 .text 86#endif 87 88/* 89 * Invalid mode handlers 90 */ 91 .macro inv_entry, reason 92 sub sp, sp, #S_FRAME_SIZE 93 ARM( stmib sp, {r1 - lr} ) 94 THUMB( stmia sp, {r0 - r12} ) 95 THUMB( str sp, [sp, #S_SP] ) 96 THUMB( str lr, [sp, #S_LR] ) 97 mov r1, #\reason 98 .endm 99 100__pabt_invalid: 101 inv_entry BAD_PREFETCH 102 b common_invalid 103ENDPROC(__pabt_invalid) 104 105__dabt_invalid: 106 inv_entry BAD_DATA 107 b common_invalid 108ENDPROC(__dabt_invalid) 109 110__irq_invalid: 111 inv_entry BAD_IRQ 112 b common_invalid 113ENDPROC(__irq_invalid) 114 115__und_invalid: 116 inv_entry BAD_UNDEFINSTR 117 118 @ 119 @ XXX fall through to common_invalid 120 @ 121 122@ 123@ common_invalid - generic code for failed exception (re-entrant version of handlers) 124@ 125common_invalid: 126 zero_fp 127 128 ldmia r0, {r4 - r6} 129 add r0, sp, #S_PC @ here for interlock avoidance 130 mov r7, #-1 @ "" "" "" "" 131 str r4, [sp] @ save preserved r0 132 stmia r0, {r5 - r7} @ lr_<exception>, 133 @ cpsr_<exception>, "old_r0" 134 135 mov r0, sp 136 b bad_mode 137ENDPROC(__und_invalid) 138 139/* 140 * SVC mode handlers 141 */ 142 143#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 144#define SPFIX(code...) code 145#else 146#define SPFIX(code...) 147#endif 148 149 .macro svc_entry, stack_hole=0 150 UNWIND(.fnstart ) 151 UNWIND(.save {r0 - pc} ) 152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 153#ifdef CONFIG_THUMB2_KERNEL 154 SPFIX( str r0, [sp] ) @ temporarily saved 155 SPFIX( mov r0, sp ) 156 SPFIX( tst r0, #4 ) @ test original stack alignment 157 SPFIX( ldr r0, [sp] ) @ restored 158#else 159 SPFIX( tst sp, #4 ) 160#endif 161 SPFIX( subeq sp, sp, #4 ) 162 stmia sp, {r1 - r12} 163 164 ldmia r0, {r3 - r5} 165 add r7, sp, #S_SP - 4 @ here for interlock avoidance 166 mov r6, #-1 @ "" "" "" "" 167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) 168 SPFIX( addeq r2, r2, #4 ) 169 str r3, [sp, #-4]! @ save the "real" r0 copied 170 @ from the exception stack 171 172 mov r3, lr 173 174 @ 175 @ We are now ready to fill in the remaining blanks on the stack: 176 @ 177 @ r2 - sp_svc 178 @ r3 - lr_svc 179 @ r4 - lr_<exception>, already fixed up for correct return/restart 180 @ r5 - spsr_<exception> 181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 182 @ 183 stmia r7, {r2 - r6} 184 185#ifdef CONFIG_TRACE_IRQFLAGS 186 bl trace_hardirqs_off 187#endif 188 .endm 189 190 .align 5 191__dabt_svc: 192 svc_entry 193 mov r2, sp 194 dabt_helper 195 196 @ 197 @ IRQs off again before pulling preserved data off the stack 198 @ 199 disable_irq_notrace 200 201#ifdef CONFIG_TRACE_IRQFLAGS 202 tst r5, #PSR_I_BIT 203 bleq trace_hardirqs_on 204 tst r5, #PSR_I_BIT 205 blne trace_hardirqs_off 206#endif 207 svc_exit r5 @ return from exception 208 UNWIND(.fnend ) 209ENDPROC(__dabt_svc) 210 211 .align 5 212__irq_svc: 213 svc_entry 214 irq_handler 215 216#ifdef CONFIG_PREEMPT 217 get_thread_info tsk 218 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 219 ldr r0, [tsk, #TI_FLAGS] @ get flags 220 teq r8, #0 @ if preempt count != 0 221 movne r0, #0 @ force flags to 0 222 tst r0, #_TIF_NEED_RESCHED 223 blne svc_preempt 224#endif 225 226#ifdef CONFIG_TRACE_IRQFLAGS 227 @ The parent context IRQs must have been enabled to get here in 228 @ the first place, so there's no point checking the PSR I bit. 229 bl trace_hardirqs_on 230#endif 231 svc_exit r5 @ return from exception 232 UNWIND(.fnend ) 233ENDPROC(__irq_svc) 234 235 .ltorg 236 237#ifdef CONFIG_PREEMPT 238svc_preempt: 239 mov r8, lr 2401: bl preempt_schedule_irq @ irq en/disable is done inside 241 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 242 tst r0, #_TIF_NEED_RESCHED 243 moveq pc, r8 @ go again 244 b 1b 245#endif 246 247 .align 5 248__und_svc: 249#ifdef CONFIG_KPROBES 250 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 251 @ it obviously needs free stack space which then will belong to 252 @ the saved context. 253 svc_entry 64 254#else 255 svc_entry 256#endif 257 @ 258 @ call emulation code, which returns using r9 if it has emulated 259 @ the instruction, or the more conventional lr if we are to treat 260 @ this as a real undefined instruction 261 @ 262 @ r0 - instruction 263 @ 264#ifndef CONFIG_THUMB2_KERNEL 265 ldr r0, [r4, #-4] 266#else 267 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 268 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 269 ldrhhs r9, [r4] @ bottom 16 bits 270 orrhs r0, r9, r0, lsl #16 271#endif 272 adr r9, BSYM(1f) 273 mov r2, r4 274 bl call_fpe 275 276 mov r0, sp @ struct pt_regs *regs 277 bl do_undefinstr 278 279 @ 280 @ IRQs off again before pulling preserved data off the stack 281 @ 2821: disable_irq_notrace 283 284 @ 285 @ restore SPSR and restart the instruction 286 @ 287 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 288#ifdef CONFIG_TRACE_IRQFLAGS 289 tst r5, #PSR_I_BIT 290 bleq trace_hardirqs_on 291 tst r5, #PSR_I_BIT 292 blne trace_hardirqs_off 293#endif 294 svc_exit r5 @ return from exception 295 UNWIND(.fnend ) 296ENDPROC(__und_svc) 297 298 .align 5 299__pabt_svc: 300 svc_entry 301 mov r2, sp @ regs 302 pabt_helper 303 304 @ 305 @ IRQs off again before pulling preserved data off the stack 306 @ 307 disable_irq_notrace 308 309#ifdef CONFIG_TRACE_IRQFLAGS 310 tst r5, #PSR_I_BIT 311 bleq trace_hardirqs_on 312 tst r5, #PSR_I_BIT 313 blne trace_hardirqs_off 314#endif 315 svc_exit r5 @ return from exception 316 UNWIND(.fnend ) 317ENDPROC(__pabt_svc) 318 319 .align 5 320.LCcralign: 321 .word cr_alignment 322#ifdef MULTI_DABORT 323.LCprocfns: 324 .word processor 325#endif 326.LCfp: 327 .word fp_enter 328 329/* 330 * User mode handlers 331 * 332 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 333 */ 334 335#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 336#error "sizeof(struct pt_regs) must be a multiple of 8" 337#endif 338 339 .macro usr_entry 340 UNWIND(.fnstart ) 341 UNWIND(.cantunwind ) @ don't unwind the user space 342 sub sp, sp, #S_FRAME_SIZE 343 ARM( stmib sp, {r1 - r12} ) 344 THUMB( stmia sp, {r0 - r12} ) 345 346 ldmia r0, {r3 - r5} 347 add r0, sp, #S_PC @ here for interlock avoidance 348 mov r6, #-1 @ "" "" "" "" 349 350 str r3, [sp] @ save the "real" r0 copied 351 @ from the exception stack 352 353 @ 354 @ We are now ready to fill in the remaining blanks on the stack: 355 @ 356 @ r4 - lr_<exception>, already fixed up for correct return/restart 357 @ r5 - spsr_<exception> 358 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 359 @ 360 @ Also, separately save sp_usr and lr_usr 361 @ 362 stmia r0, {r4 - r6} 363 ARM( stmdb r0, {sp, lr}^ ) 364 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 365 366 @ 367 @ Enable the alignment trap while in kernel mode 368 @ 369 alignment_trap r0 370 371 @ 372 @ Clear FP to mark the first stack frame 373 @ 374 zero_fp 375 376#ifdef CONFIG_IRQSOFF_TRACER 377 bl trace_hardirqs_off 378#endif 379 .endm 380 381 .macro kuser_cmpxchg_check 382#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 383#ifndef CONFIG_MMU 384#warning "NPTL on non MMU needs fixing" 385#else 386 @ Make sure our user space atomic helper is restarted 387 @ if it was interrupted in a critical region. Here we 388 @ perform a quick test inline since it should be false 389 @ 99.9999% of the time. The rest is done out of line. 390 cmp r4, #TASK_SIZE 391 blhs kuser_cmpxchg64_fixup 392#endif 393#endif 394 .endm 395 396 .align 5 397__dabt_usr: 398 usr_entry 399 kuser_cmpxchg_check 400 mov r2, sp 401 dabt_helper 402 b ret_from_exception 403 UNWIND(.fnend ) 404ENDPROC(__dabt_usr) 405 406 .align 5 407__irq_usr: 408 usr_entry 409 kuser_cmpxchg_check 410 irq_handler 411 get_thread_info tsk 412 mov why, #0 413 b ret_to_user_from_irq 414 UNWIND(.fnend ) 415ENDPROC(__irq_usr) 416 417 .ltorg 418 419 .align 5 420__und_usr: 421 usr_entry 422 423 mov r2, r4 424 mov r3, r5 425 426 @ 427 @ fall through to the emulation code, which returns using r9 if 428 @ it has emulated the instruction, or the more conventional lr 429 @ if we are to treat this as a real undefined instruction 430 @ 431 @ r0 - instruction 432 @ 433 adr r9, BSYM(ret_from_exception) 434 adr lr, BSYM(__und_usr_unknown) 435 tst r3, #PSR_T_BIT @ Thumb mode? 436 itet eq @ explicit IT needed for the 1f label 437 subeq r4, r2, #4 @ ARM instr at LR - 4 438 subne r4, r2, #2 @ Thumb instr at LR - 2 4391: ldreqt r0, [r4] 440#ifdef CONFIG_CPU_ENDIAN_BE8 441 reveq r0, r0 @ little endian instruction 442#endif 443 beq call_fpe 444 @ Thumb instruction 445#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 446/* 447 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 448 * can never be supported in a single kernel, this code is not applicable at 449 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 450 * made about .arch directives. 451 */ 452#if __LINUX_ARM_ARCH__ < 7 453/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 454#define NEED_CPU_ARCHITECTURE 455 ldr r5, .LCcpu_architecture 456 ldr r5, [r5] 457 cmp r5, #CPU_ARCH_ARMv7 458 blo __und_usr_unknown 459/* 460 * The following code won't get run unless the running CPU really is v7, so 461 * coding round the lack of ldrht on older arches is pointless. Temporarily 462 * override the assembler target arch with the minimum required instead: 463 */ 464 .arch armv6t2 465#endif 4662: 467 ARM( ldrht r5, [r4], #2 ) 468 THUMB( ldrht r5, [r4] ) 469 THUMB( add r4, r4, #2 ) 470 cmp r5, #0xe800 @ 32bit instruction if xx != 0 471 blo __und_usr_unknown 4723: ldrht r0, [r4] 473 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 474 orr r0, r0, r5, lsl #16 475 476#if __LINUX_ARM_ARCH__ < 7 477/* If the target arch was overridden, change it back: */ 478#ifdef CONFIG_CPU_32v6K 479 .arch armv6k 480#else 481 .arch armv6 482#endif 483#endif /* __LINUX_ARM_ARCH__ < 7 */ 484#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 485 b __und_usr_unknown 486#endif 487 UNWIND(.fnend ) 488ENDPROC(__und_usr) 489 490 @ 491 @ fallthrough to call_fpe 492 @ 493 494/* 495 * The out of line fixup for the ldrt above. 496 */ 497 .pushsection .fixup, "ax" 498 .align 2 4994: mov pc, r9 500 .popsection 501 .pushsection __ex_table,"a" 502 .long 1b, 4b 503#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 504 .long 2b, 4b 505 .long 3b, 4b 506#endif 507 .popsection 508 509/* 510 * Check whether the instruction is a co-processor instruction. 511 * If yes, we need to call the relevant co-processor handler. 512 * 513 * Note that we don't do a full check here for the co-processor 514 * instructions; all instructions with bit 27 set are well 515 * defined. The only instructions that should fault are the 516 * co-processor instructions. However, we have to watch out 517 * for the ARM6/ARM7 SWI bug. 518 * 519 * NEON is a special case that has to be handled here. Not all 520 * NEON instructions are co-processor instructions, so we have 521 * to make a special case of checking for them. Plus, there's 522 * five groups of them, so we have a table of mask/opcode pairs 523 * to check against, and if any match then we branch off into the 524 * NEON handler code. 525 * 526 * Emulators may wish to make use of the following registers: 527 * r0 = instruction opcode. 528 * r2 = PC+4 529 * r9 = normal "successful" return address 530 * r10 = this threads thread_info structure. 531 * lr = unrecognised instruction return address 532 */ 533 @ 534 @ Fall-through from Thumb-2 __und_usr 535 @ 536#ifdef CONFIG_NEON 537 adr r6, .LCneon_thumb_opcodes 538 b 2f 539#endif 540call_fpe: 541#ifdef CONFIG_NEON 542 adr r6, .LCneon_arm_opcodes 5432: 544 ldr r7, [r6], #4 @ mask value 545 cmp r7, #0 @ end mask? 546 beq 1f 547 and r8, r0, r7 548 ldr r7, [r6], #4 @ opcode bits matching in mask 549 cmp r8, r7 @ NEON instruction? 550 bne 2b 551 get_thread_info r10 552 mov r7, #1 553 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 554 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 555 b do_vfp @ let VFP handler handle this 5561: 557#endif 558 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 559 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 560 moveq pc, lr 561 get_thread_info r10 @ get current thread 562 and r8, r0, #0x00000f00 @ mask out CP number 563 THUMB( lsr r8, r8, #8 ) 564 mov r7, #1 565 add r6, r10, #TI_USED_CP 566 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 567 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 568#ifdef CONFIG_IWMMXT 569 @ Test if we need to give access to iWMMXt coprocessors 570 ldr r5, [r10, #TI_FLAGS] 571 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 572 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 573 bcs iwmmxt_task_enable 574#endif 575 ARM( add pc, pc, r8, lsr #6 ) 576 THUMB( lsl r8, r8, #2 ) 577 THUMB( add pc, r8 ) 578 nop 579 580 movw_pc lr @ CP#0 581 W(b) do_fpe @ CP#1 (FPE) 582 W(b) do_fpe @ CP#2 (FPE) 583 movw_pc lr @ CP#3 584#ifdef CONFIG_CRUNCH 585 b crunch_task_enable @ CP#4 (MaverickCrunch) 586 b crunch_task_enable @ CP#5 (MaverickCrunch) 587 b crunch_task_enable @ CP#6 (MaverickCrunch) 588#else 589 movw_pc lr @ CP#4 590 movw_pc lr @ CP#5 591 movw_pc lr @ CP#6 592#endif 593 movw_pc lr @ CP#7 594 movw_pc lr @ CP#8 595 movw_pc lr @ CP#9 596#ifdef CONFIG_VFP 597 W(b) do_vfp @ CP#10 (VFP) 598 W(b) do_vfp @ CP#11 (VFP) 599#else 600 movw_pc lr @ CP#10 (VFP) 601 movw_pc lr @ CP#11 (VFP) 602#endif 603 movw_pc lr @ CP#12 604 movw_pc lr @ CP#13 605 movw_pc lr @ CP#14 (Debug) 606 movw_pc lr @ CP#15 (Control) 607 608#ifdef NEED_CPU_ARCHITECTURE 609 .align 2 610.LCcpu_architecture: 611 .word __cpu_architecture 612#endif 613 614#ifdef CONFIG_NEON 615 .align 6 616 617.LCneon_arm_opcodes: 618 .word 0xfe000000 @ mask 619 .word 0xf2000000 @ opcode 620 621 .word 0xff100000 @ mask 622 .word 0xf4000000 @ opcode 623 624 .word 0x00000000 @ mask 625 .word 0x00000000 @ opcode 626 627.LCneon_thumb_opcodes: 628 .word 0xef000000 @ mask 629 .word 0xef000000 @ opcode 630 631 .word 0xff100000 @ mask 632 .word 0xf9000000 @ opcode 633 634 .word 0x00000000 @ mask 635 .word 0x00000000 @ opcode 636#endif 637 638do_fpe: 639 enable_irq 640 ldr r4, .LCfp 641 add r10, r10, #TI_FPSTATE @ r10 = workspace 642 ldr pc, [r4] @ Call FP module USR entry point 643 644/* 645 * The FP module is called with these registers set: 646 * r0 = instruction 647 * r2 = PC+4 648 * r9 = normal "successful" return address 649 * r10 = FP workspace 650 * lr = unrecognised FP instruction return address 651 */ 652 653 .pushsection .data 654ENTRY(fp_enter) 655 .word no_fp 656 .popsection 657 658ENTRY(no_fp) 659 mov pc, lr 660ENDPROC(no_fp) 661 662__und_usr_unknown: 663 enable_irq 664 mov r0, sp 665 adr lr, BSYM(ret_from_exception) 666 b do_undefinstr 667ENDPROC(__und_usr_unknown) 668 669 .align 5 670__pabt_usr: 671 usr_entry 672 mov r2, sp @ regs 673 pabt_helper 674 UNWIND(.fnend ) 675 /* fall through */ 676/* 677 * This is the return code to user mode for abort handlers 678 */ 679ENTRY(ret_from_exception) 680 UNWIND(.fnstart ) 681 UNWIND(.cantunwind ) 682 get_thread_info tsk 683 mov why, #0 684 b ret_to_user 685 UNWIND(.fnend ) 686ENDPROC(__pabt_usr) 687ENDPROC(ret_from_exception) 688 689/* 690 * Register switch for ARMv3 and ARMv4 processors 691 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 692 * previous and next are guaranteed not to be the same. 693 */ 694ENTRY(__switch_to) 695 UNWIND(.fnstart ) 696 UNWIND(.cantunwind ) 697 add ip, r1, #TI_CPU_SAVE 698 ldr r3, [r2, #TI_TP_VALUE] 699 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 700 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 701 THUMB( str sp, [ip], #4 ) 702 THUMB( str lr, [ip], #4 ) 703#ifdef CONFIG_CPU_USE_DOMAINS 704 ldr r6, [r2, #TI_CPU_DOMAIN] 705#endif 706 set_tls r3, r4, r5 707#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 708 ldr r7, [r2, #TI_TASK] 709 ldr r8, =__stack_chk_guard 710 ldr r7, [r7, #TSK_STACK_CANARY] 711#endif 712#ifdef CONFIG_CPU_USE_DOMAINS 713 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 714#endif 715 mov r5, r0 716 add r4, r2, #TI_CPU_SAVE 717 ldr r0, =thread_notify_head 718 mov r1, #THREAD_NOTIFY_SWITCH 719 bl atomic_notifier_call_chain 720#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 721 str r7, [r8] 722#endif 723 THUMB( mov ip, r4 ) 724 mov r0, r5 725 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 726 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 727 THUMB( ldr sp, [ip], #4 ) 728 THUMB( ldr pc, [ip] ) 729 UNWIND(.fnend ) 730ENDPROC(__switch_to) 731 732 __INIT 733 734/* 735 * User helpers. 736 * 737 * Each segment is 32-byte aligned and will be moved to the top of the high 738 * vector page. New segments (if ever needed) must be added in front of 739 * existing ones. This mechanism should be used only for things that are 740 * really small and justified, and not be abused freely. 741 * 742 * See Documentation/arm/kernel_user_helpers.txt for formal definitions. 743 */ 744 THUMB( .arm ) 745 746 .macro usr_ret, reg 747#ifdef CONFIG_ARM_THUMB 748 bx \reg 749#else 750 mov pc, \reg 751#endif 752 .endm 753 754 .align 5 755 .globl __kuser_helper_start 756__kuser_helper_start: 757 758/* 759 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 760 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 761 */ 762 763__kuser_cmpxchg64: @ 0xffff0f60 764 765#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 766 767 /* 768 * Poor you. No fast solution possible... 769 * The kernel itself must perform the operation. 770 * A special ghost syscall is used for that (see traps.c). 771 */ 772 stmfd sp!, {r7, lr} 773 ldr r7, 1f @ it's 20 bits 774 swi __ARM_NR_cmpxchg64 775 ldmfd sp!, {r7, pc} 7761: .word __ARM_NR_cmpxchg64 777 778#elif defined(CONFIG_CPU_32v6K) 779 780 stmfd sp!, {r4, r5, r6, r7} 781 ldrd r4, r5, [r0] @ load old val 782 ldrd r6, r7, [r1] @ load new val 783 smp_dmb arm 7841: ldrexd r0, r1, [r2] @ load current val 785 eors r3, r0, r4 @ compare with oldval (1) 786 eoreqs r3, r1, r5 @ compare with oldval (2) 787 strexdeq r3, r6, r7, [r2] @ store newval if eq 788 teqeq r3, #1 @ success? 789 beq 1b @ if no then retry 790 smp_dmb arm 791 rsbs r0, r3, #0 @ set returned val and C flag 792 ldmfd sp!, {r4, r5, r6, r7} 793 usr_ret lr 794 795#elif !defined(CONFIG_SMP) 796 797#ifdef CONFIG_MMU 798 799 /* 800 * The only thing that can break atomicity in this cmpxchg64 801 * implementation is either an IRQ or a data abort exception 802 * causing another process/thread to be scheduled in the middle of 803 * the critical sequence. The same strategy as for cmpxchg is used. 804 */ 805 stmfd sp!, {r4, r5, r6, lr} 806 ldmia r0, {r4, r5} @ load old val 807 ldmia r1, {r6, lr} @ load new val 8081: ldmia r2, {r0, r1} @ load current val 809 eors r3, r0, r4 @ compare with oldval (1) 810 eoreqs r3, r1, r5 @ compare with oldval (2) 8112: stmeqia r2, {r6, lr} @ store newval if eq 812 rsbs r0, r3, #0 @ set return val and C flag 813 ldmfd sp!, {r4, r5, r6, pc} 814 815 .text 816kuser_cmpxchg64_fixup: 817 @ Called from kuser_cmpxchg_fixup. 818 @ r4 = address of interrupted insn (must be preserved). 819 @ sp = saved regs. r7 and r8 are clobbered. 820 @ 1b = first critical insn, 2b = last critical insn. 821 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 822 mov r7, #0xffff0fff 823 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 824 subs r8, r4, r7 825 rsbcss r8, r8, #(2b - 1b) 826 strcs r7, [sp, #S_PC] 827#if __LINUX_ARM_ARCH__ < 6 828 bcc kuser_cmpxchg32_fixup 829#endif 830 mov pc, lr 831 .previous 832 833#else 834#warning "NPTL on non MMU needs fixing" 835 mov r0, #-1 836 adds r0, r0, #0 837 usr_ret lr 838#endif 839 840#else 841#error "incoherent kernel configuration" 842#endif 843 844 /* pad to next slot */ 845 .rept (16 - (. - __kuser_cmpxchg64)/4) 846 .word 0 847 .endr 848 849 .align 5 850 851__kuser_memory_barrier: @ 0xffff0fa0 852 smp_dmb arm 853 usr_ret lr 854 855 .align 5 856 857__kuser_cmpxchg: @ 0xffff0fc0 858 859#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 860 861 /* 862 * Poor you. No fast solution possible... 863 * The kernel itself must perform the operation. 864 * A special ghost syscall is used for that (see traps.c). 865 */ 866 stmfd sp!, {r7, lr} 867 ldr r7, 1f @ it's 20 bits 868 swi __ARM_NR_cmpxchg 869 ldmfd sp!, {r7, pc} 8701: .word __ARM_NR_cmpxchg 871 872#elif __LINUX_ARM_ARCH__ < 6 873 874#ifdef CONFIG_MMU 875 876 /* 877 * The only thing that can break atomicity in this cmpxchg 878 * implementation is either an IRQ or a data abort exception 879 * causing another process/thread to be scheduled in the middle 880 * of the critical sequence. To prevent this, code is added to 881 * the IRQ and data abort exception handlers to set the pc back 882 * to the beginning of the critical section if it is found to be 883 * within that critical section (see kuser_cmpxchg_fixup). 884 */ 8851: ldr r3, [r2] @ load current val 886 subs r3, r3, r0 @ compare with oldval 8872: streq r1, [r2] @ store newval if eq 888 rsbs r0, r3, #0 @ set return val and C flag 889 usr_ret lr 890 891 .text 892kuser_cmpxchg32_fixup: 893 @ Called from kuser_cmpxchg_check macro. 894 @ r4 = address of interrupted insn (must be preserved). 895 @ sp = saved regs. r7 and r8 are clobbered. 896 @ 1b = first critical insn, 2b = last critical insn. 897 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 898 mov r7, #0xffff0fff 899 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 900 subs r8, r4, r7 901 rsbcss r8, r8, #(2b - 1b) 902 strcs r7, [sp, #S_PC] 903 mov pc, lr 904 .previous 905 906#else 907#warning "NPTL on non MMU needs fixing" 908 mov r0, #-1 909 adds r0, r0, #0 910 usr_ret lr 911#endif 912 913#else 914 915 smp_dmb arm 9161: ldrex r3, [r2] 917 subs r3, r3, r0 918 strexeq r3, r1, [r2] 919 teqeq r3, #1 920 beq 1b 921 rsbs r0, r3, #0 922 /* beware -- each __kuser slot must be 8 instructions max */ 923 ALT_SMP(b __kuser_memory_barrier) 924 ALT_UP(usr_ret lr) 925 926#endif 927 928 .align 5 929 930__kuser_get_tls: @ 0xffff0fe0 931 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 932 usr_ret lr 933 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 934 .rep 4 935 .word 0 @ 0xffff0ff0 software TLS value, then 936 .endr @ pad up to __kuser_helper_version 937 938__kuser_helper_version: @ 0xffff0ffc 939 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 940 941 .globl __kuser_helper_end 942__kuser_helper_end: 943 944 THUMB( .thumb ) 945 946/* 947 * Vector stubs. 948 * 949 * This code is copied to 0xffff0200 so we can use branches in the 950 * vectors, rather than ldr's. Note that this code must not 951 * exceed 0x300 bytes. 952 * 953 * Common stub entry macro: 954 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 955 * 956 * SP points to a minimal amount of processor-private memory, the address 957 * of which is copied into r0 for the mode specific abort handler. 958 */ 959 .macro vector_stub, name, mode, correction=0 960 .align 5 961 962vector_\name: 963 .if \correction 964 sub lr, lr, #\correction 965 .endif 966 967 @ 968 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 969 @ (parent CPSR) 970 @ 971 stmia sp, {r0, lr} @ save r0, lr 972 mrs lr, spsr 973 str lr, [sp, #8] @ save spsr 974 975 @ 976 @ Prepare for SVC32 mode. IRQs remain disabled. 977 @ 978 mrs r0, cpsr 979 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 980 msr spsr_cxsf, r0 981 982 @ 983 @ the branch table must immediately follow this code 984 @ 985 and lr, lr, #0x0f 986 THUMB( adr r0, 1f ) 987 THUMB( ldr lr, [r0, lr, lsl #2] ) 988 mov r0, sp 989 ARM( ldr lr, [pc, lr, lsl #2] ) 990 movs pc, lr @ branch to handler in SVC mode 991ENDPROC(vector_\name) 992 993 .align 2 994 @ handler addresses follow this label 9951: 996 .endm 997 998 .globl __stubs_start 999__stubs_start: 1000/* 1001 * Interrupt dispatcher 1002 */ 1003 vector_stub irq, IRQ_MODE, 4 1004 1005 .long __irq_usr @ 0 (USR_26 / USR_32) 1006 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1007 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1008 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1009 .long __irq_invalid @ 4 1010 .long __irq_invalid @ 5 1011 .long __irq_invalid @ 6 1012 .long __irq_invalid @ 7 1013 .long __irq_invalid @ 8 1014 .long __irq_invalid @ 9 1015 .long __irq_invalid @ a 1016 .long __irq_invalid @ b 1017 .long __irq_invalid @ c 1018 .long __irq_invalid @ d 1019 .long __irq_invalid @ e 1020 .long __irq_invalid @ f 1021 1022/* 1023 * Data abort dispatcher 1024 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1025 */ 1026 vector_stub dabt, ABT_MODE, 8 1027 1028 .long __dabt_usr @ 0 (USR_26 / USR_32) 1029 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1030 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1031 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1032 .long __dabt_invalid @ 4 1033 .long __dabt_invalid @ 5 1034 .long __dabt_invalid @ 6 1035 .long __dabt_invalid @ 7 1036 .long __dabt_invalid @ 8 1037 .long __dabt_invalid @ 9 1038 .long __dabt_invalid @ a 1039 .long __dabt_invalid @ b 1040 .long __dabt_invalid @ c 1041 .long __dabt_invalid @ d 1042 .long __dabt_invalid @ e 1043 .long __dabt_invalid @ f 1044 1045/* 1046 * Prefetch abort dispatcher 1047 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1048 */ 1049 vector_stub pabt, ABT_MODE, 4 1050 1051 .long __pabt_usr @ 0 (USR_26 / USR_32) 1052 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1053 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1054 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1055 .long __pabt_invalid @ 4 1056 .long __pabt_invalid @ 5 1057 .long __pabt_invalid @ 6 1058 .long __pabt_invalid @ 7 1059 .long __pabt_invalid @ 8 1060 .long __pabt_invalid @ 9 1061 .long __pabt_invalid @ a 1062 .long __pabt_invalid @ b 1063 .long __pabt_invalid @ c 1064 .long __pabt_invalid @ d 1065 .long __pabt_invalid @ e 1066 .long __pabt_invalid @ f 1067 1068/* 1069 * Undef instr entry dispatcher 1070 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1071 */ 1072 vector_stub und, UND_MODE 1073 1074 .long __und_usr @ 0 (USR_26 / USR_32) 1075 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1076 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1077 .long __und_svc @ 3 (SVC_26 / SVC_32) 1078 .long __und_invalid @ 4 1079 .long __und_invalid @ 5 1080 .long __und_invalid @ 6 1081 .long __und_invalid @ 7 1082 .long __und_invalid @ 8 1083 .long __und_invalid @ 9 1084 .long __und_invalid @ a 1085 .long __und_invalid @ b 1086 .long __und_invalid @ c 1087 .long __und_invalid @ d 1088 .long __und_invalid @ e 1089 .long __und_invalid @ f 1090 1091 .align 5 1092 1093/*============================================================================= 1094 * Undefined FIQs 1095 *----------------------------------------------------------------------------- 1096 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1097 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1098 * Basically to switch modes, we *HAVE* to clobber one register... brain 1099 * damage alert! I don't think that we can execute any code in here in any 1100 * other mode than FIQ... Ok you can switch to another mode, but you can't 1101 * get out of that mode without clobbering one register. 1102 */ 1103vector_fiq: 1104 subs pc, lr, #4 1105 1106/*============================================================================= 1107 * Address exception handler 1108 *----------------------------------------------------------------------------- 1109 * These aren't too critical. 1110 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1111 */ 1112 1113vector_addrexcptn: 1114 b vector_addrexcptn 1115 1116/* 1117 * We group all the following data together to optimise 1118 * for CPUs with separate I & D caches. 1119 */ 1120 .align 5 1121 1122.LCvswi: 1123 .word vector_swi 1124 1125 .globl __stubs_end 1126__stubs_end: 1127 1128 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1129 1130 .globl __vectors_start 1131__vectors_start: 1132 ARM( swi SYS_ERROR0 ) 1133 THUMB( svc #0 ) 1134 THUMB( nop ) 1135 W(b) vector_und + stubs_offset 1136 W(ldr) pc, .LCvswi + stubs_offset 1137 W(b) vector_pabt + stubs_offset 1138 W(b) vector_dabt + stubs_offset 1139 W(b) vector_addrexcptn + stubs_offset 1140 W(b) vector_irq + stubs_offset 1141 W(b) vector_fiq + stubs_offset 1142 1143 .globl __vectors_end 1144__vectors_end: 1145 1146 .data 1147 1148 .globl cr_alignment 1149 .globl cr_no_alignment 1150cr_alignment: 1151 .space 4 1152cr_no_alignment: 1153 .space 4 1154 1155#ifdef CONFIG_MULTI_IRQ_HANDLER 1156 .globl handle_arch_irq 1157handle_arch_irq: 1158 .space 4 1159#endif 1160