1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/assembler.h> 19#include <asm/memory.h> 20#include <asm/glue-df.h> 21#include <asm/glue-pf.h> 22#include <asm/vfpmacros.h> 23#ifndef CONFIG_MULTI_IRQ_HANDLER 24#include <mach/entry-macro.S> 25#endif 26#include <asm/thread_notify.h> 27#include <asm/unwind.h> 28#include <asm/unistd.h> 29#include <asm/tls.h> 30#include <asm/system_info.h> 31 32#include "entry-header.S" 33#include <asm/entry-macro-multi.S> 34 35/* 36 * Interrupt handling. 37 */ 38 .macro irq_handler 39#ifdef CONFIG_MULTI_IRQ_HANDLER 40 ldr r1, =handle_arch_irq 41 mov r0, sp 42 adr lr, BSYM(9997f) 43 ldr pc, [r1] 44#else 45 arch_irq_handler_default 46#endif 479997: 48 .endm 49 50 .macro pabt_helper 51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 52#ifdef MULTI_PABORT 53 ldr ip, .LCprocfns 54 mov lr, pc 55 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 56#else 57 bl CPU_PABORT_HANDLER 58#endif 59 .endm 60 61 .macro dabt_helper 62 63 @ 64 @ Call the processor-specific abort handler: 65 @ 66 @ r2 - pt_regs 67 @ r4 - aborted context pc 68 @ r5 - aborted context psr 69 @ 70 @ The abort handler must return the aborted address in r0, and 71 @ the fault status register in r1. r9 must be preserved. 72 @ 73#ifdef MULTI_DABORT 74 ldr ip, .LCprocfns 75 mov lr, pc 76 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 77#else 78 bl CPU_DABORT_HANDLER 79#endif 80 .endm 81 82#ifdef CONFIG_KPROBES 83 .section .kprobes.text,"ax",%progbits 84#else 85 .text 86#endif 87 88/* 89 * Invalid mode handlers 90 */ 91 .macro inv_entry, reason 92 sub sp, sp, #S_FRAME_SIZE 93 ARM( stmib sp, {r1 - lr} ) 94 THUMB( stmia sp, {r0 - r12} ) 95 THUMB( str sp, [sp, #S_SP] ) 96 THUMB( str lr, [sp, #S_LR] ) 97 mov r1, #\reason 98 .endm 99 100__pabt_invalid: 101 inv_entry BAD_PREFETCH 102 b common_invalid 103ENDPROC(__pabt_invalid) 104 105__dabt_invalid: 106 inv_entry BAD_DATA 107 b common_invalid 108ENDPROC(__dabt_invalid) 109 110__irq_invalid: 111 inv_entry BAD_IRQ 112 b common_invalid 113ENDPROC(__irq_invalid) 114 115__und_invalid: 116 inv_entry BAD_UNDEFINSTR 117 118 @ 119 @ XXX fall through to common_invalid 120 @ 121 122@ 123@ common_invalid - generic code for failed exception (re-entrant version of handlers) 124@ 125common_invalid: 126 zero_fp 127 128 ldmia r0, {r4 - r6} 129 add r0, sp, #S_PC @ here for interlock avoidance 130 mov r7, #-1 @ "" "" "" "" 131 str r4, [sp] @ save preserved r0 132 stmia r0, {r5 - r7} @ lr_<exception>, 133 @ cpsr_<exception>, "old_r0" 134 135 mov r0, sp 136 b bad_mode 137ENDPROC(__und_invalid) 138 139/* 140 * SVC mode handlers 141 */ 142 143#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 144#define SPFIX(code...) code 145#else 146#define SPFIX(code...) 147#endif 148 149 .macro svc_entry, stack_hole=0, trace=1 150 UNWIND(.fnstart ) 151 UNWIND(.save {r0 - pc} ) 152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 153#ifdef CONFIG_THUMB2_KERNEL 154 SPFIX( str r0, [sp] ) @ temporarily saved 155 SPFIX( mov r0, sp ) 156 SPFIX( tst r0, #4 ) @ test original stack alignment 157 SPFIX( ldr r0, [sp] ) @ restored 158#else 159 SPFIX( tst sp, #4 ) 160#endif 161 SPFIX( subeq sp, sp, #4 ) 162 stmia sp, {r1 - r12} 163 164 ldmia r0, {r3 - r5} 165 add r7, sp, #S_SP - 4 @ here for interlock avoidance 166 mov r6, #-1 @ "" "" "" "" 167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) 168 SPFIX( addeq r2, r2, #4 ) 169 str r3, [sp, #-4]! @ save the "real" r0 copied 170 @ from the exception stack 171 172 mov r3, lr 173 174 @ 175 @ We are now ready to fill in the remaining blanks on the stack: 176 @ 177 @ r2 - sp_svc 178 @ r3 - lr_svc 179 @ r4 - lr_<exception>, already fixed up for correct return/restart 180 @ r5 - spsr_<exception> 181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 182 @ 183 stmia r7, {r2 - r6} 184 185 .if \trace 186#ifdef CONFIG_TRACE_IRQFLAGS 187 bl trace_hardirqs_off 188#endif 189 .endif 190 .endm 191 192 .align 5 193__dabt_svc: 194 svc_entry 195 mov r2, sp 196 dabt_helper 197 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 198 svc_exit r5 @ return from exception 199 UNWIND(.fnend ) 200ENDPROC(__dabt_svc) 201 202 .align 5 203__irq_svc: 204 svc_entry 205 irq_handler 206 207#ifdef CONFIG_PREEMPT 208 get_thread_info tsk 209 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 210 ldr r0, [tsk, #TI_FLAGS] @ get flags 211 teq r8, #0 @ if preempt count != 0 212 movne r0, #0 @ force flags to 0 213 tst r0, #_TIF_NEED_RESCHED 214 blne svc_preempt 215#endif 216 217 svc_exit r5, irq = 1 @ return from exception 218 UNWIND(.fnend ) 219ENDPROC(__irq_svc) 220 221 .ltorg 222 223#ifdef CONFIG_PREEMPT 224svc_preempt: 225 mov r8, lr 2261: bl preempt_schedule_irq @ irq en/disable is done inside 227 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 228 tst r0, #_TIF_NEED_RESCHED 229 reteq r8 @ go again 230 b 1b 231#endif 232 233__und_fault: 234 @ Correct the PC such that it is pointing at the instruction 235 @ which caused the fault. If the faulting instruction was ARM 236 @ the PC will be pointing at the next instruction, and have to 237 @ subtract 4. Otherwise, it is Thumb, and the PC will be 238 @ pointing at the second half of the Thumb instruction. We 239 @ have to subtract 2. 240 ldr r2, [r0, #S_PC] 241 sub r2, r2, r1 242 str r2, [r0, #S_PC] 243 b do_undefinstr 244ENDPROC(__und_fault) 245 246 .align 5 247__und_svc: 248#ifdef CONFIG_KPROBES 249 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 250 @ it obviously needs free stack space which then will belong to 251 @ the saved context. 252 svc_entry 64 253#else 254 svc_entry 255#endif 256 @ 257 @ call emulation code, which returns using r9 if it has emulated 258 @ the instruction, or the more conventional lr if we are to treat 259 @ this as a real undefined instruction 260 @ 261 @ r0 - instruction 262 @ 263#ifndef CONFIG_THUMB2_KERNEL 264 ldr r0, [r4, #-4] 265#else 266 mov r1, #2 267 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 268 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 269 blo __und_svc_fault 270 ldrh r9, [r4] @ bottom 16 bits 271 add r4, r4, #2 272 str r4, [sp, #S_PC] 273 orr r0, r9, r0, lsl #16 274#endif 275 adr r9, BSYM(__und_svc_finish) 276 mov r2, r4 277 bl call_fpe 278 279 mov r1, #4 @ PC correction to apply 280__und_svc_fault: 281 mov r0, sp @ struct pt_regs *regs 282 bl __und_fault 283 284__und_svc_finish: 285 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 286 svc_exit r5 @ return from exception 287 UNWIND(.fnend ) 288ENDPROC(__und_svc) 289 290 .align 5 291__pabt_svc: 292 svc_entry 293 mov r2, sp @ regs 294 pabt_helper 295 svc_exit r5 @ return from exception 296 UNWIND(.fnend ) 297ENDPROC(__pabt_svc) 298 299 .align 5 300__fiq_svc: 301 svc_entry trace=0 302 mov r0, sp @ struct pt_regs *regs 303 bl handle_fiq_as_nmi 304 svc_exit_via_fiq 305 UNWIND(.fnend ) 306ENDPROC(__fiq_svc) 307 308 .align 5 309.LCcralign: 310 .word cr_alignment 311#ifdef MULTI_DABORT 312.LCprocfns: 313 .word processor 314#endif 315.LCfp: 316 .word fp_enter 317 318/* 319 * Abort mode handlers 320 */ 321 322@ 323@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 324@ and reuses the same macros. However in abort mode we must also 325@ save/restore lr_abt and spsr_abt to make nested aborts safe. 326@ 327 .align 5 328__fiq_abt: 329 svc_entry trace=0 330 331 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 332 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 333 THUMB( msr cpsr_c, r0 ) 334 mov r1, lr @ Save lr_abt 335 mrs r2, spsr @ Save spsr_abt, abort is now safe 336 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 337 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 338 THUMB( msr cpsr_c, r0 ) 339 stmfd sp!, {r1 - r2} 340 341 add r0, sp, #8 @ struct pt_regs *regs 342 bl handle_fiq_as_nmi 343 344 ldmfd sp!, {r1 - r2} 345 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 346 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 347 THUMB( msr cpsr_c, r0 ) 348 mov lr, r1 @ Restore lr_abt, abort is unsafe 349 msr spsr_cxsf, r2 @ Restore spsr_abt 350 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 351 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 352 THUMB( msr cpsr_c, r0 ) 353 354 svc_exit_via_fiq 355 UNWIND(.fnend ) 356ENDPROC(__fiq_abt) 357 358/* 359 * User mode handlers 360 * 361 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 362 */ 363 364#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 365#error "sizeof(struct pt_regs) must be a multiple of 8" 366#endif 367 368 .macro usr_entry, trace=1 369 UNWIND(.fnstart ) 370 UNWIND(.cantunwind ) @ don't unwind the user space 371 sub sp, sp, #S_FRAME_SIZE 372 ARM( stmib sp, {r1 - r12} ) 373 THUMB( stmia sp, {r0 - r12} ) 374 375 ldmia r0, {r3 - r5} 376 add r0, sp, #S_PC @ here for interlock avoidance 377 mov r6, #-1 @ "" "" "" "" 378 379 str r3, [sp] @ save the "real" r0 copied 380 @ from the exception stack 381 382 @ 383 @ We are now ready to fill in the remaining blanks on the stack: 384 @ 385 @ r4 - lr_<exception>, already fixed up for correct return/restart 386 @ r5 - spsr_<exception> 387 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 388 @ 389 @ Also, separately save sp_usr and lr_usr 390 @ 391 stmia r0, {r4 - r6} 392 ARM( stmdb r0, {sp, lr}^ ) 393 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 394 395 @ 396 @ Enable the alignment trap while in kernel mode 397 @ 398 alignment_trap r0, .LCcralign 399 400 @ 401 @ Clear FP to mark the first stack frame 402 @ 403 zero_fp 404 405 .if \trace 406#ifdef CONFIG_IRQSOFF_TRACER 407 bl trace_hardirqs_off 408#endif 409 ct_user_exit save = 0 410 .endif 411 .endm 412 413 .macro kuser_cmpxchg_check 414#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \ 415 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 416#ifndef CONFIG_MMU 417#warning "NPTL on non MMU needs fixing" 418#else 419 @ Make sure our user space atomic helper is restarted 420 @ if it was interrupted in a critical region. Here we 421 @ perform a quick test inline since it should be false 422 @ 99.9999% of the time. The rest is done out of line. 423 cmp r4, #TASK_SIZE 424 blhs kuser_cmpxchg64_fixup 425#endif 426#endif 427 .endm 428 429 .align 5 430__dabt_usr: 431 usr_entry 432 kuser_cmpxchg_check 433 mov r2, sp 434 dabt_helper 435 b ret_from_exception 436 UNWIND(.fnend ) 437ENDPROC(__dabt_usr) 438 439 .align 5 440__irq_usr: 441 usr_entry 442 kuser_cmpxchg_check 443 irq_handler 444 get_thread_info tsk 445 mov why, #0 446 b ret_to_user_from_irq 447 UNWIND(.fnend ) 448ENDPROC(__irq_usr) 449 450 .ltorg 451 452 .align 5 453__und_usr: 454 usr_entry 455 456 mov r2, r4 457 mov r3, r5 458 459 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 460 @ faulting instruction depending on Thumb mode. 461 @ r3 = regs->ARM_cpsr 462 @ 463 @ The emulation code returns using r9 if it has emulated the 464 @ instruction, or the more conventional lr if we are to treat 465 @ this as a real undefined instruction 466 @ 467 adr r9, BSYM(ret_from_exception) 468 469 @ IRQs must be enabled before attempting to read the instruction from 470 @ user space since that could cause a page/translation fault if the 471 @ page table was modified by another CPU. 472 enable_irq 473 474 tst r3, #PSR_T_BIT @ Thumb mode? 475 bne __und_usr_thumb 476 sub r4, r2, #4 @ ARM instr at LR - 4 4771: ldrt r0, [r4] 478 ARM_BE8(rev r0, r0) @ little endian instruction 479 480 @ r0 = 32-bit ARM instruction which caused the exception 481 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 482 @ r4 = PC value for the faulting instruction 483 @ lr = 32-bit undefined instruction function 484 adr lr, BSYM(__und_usr_fault_32) 485 b call_fpe 486 487__und_usr_thumb: 488 @ Thumb instruction 489 sub r4, r2, #2 @ First half of thumb instr at LR - 2 490#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 491/* 492 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 493 * can never be supported in a single kernel, this code is not applicable at 494 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 495 * made about .arch directives. 496 */ 497#if __LINUX_ARM_ARCH__ < 7 498/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 499#define NEED_CPU_ARCHITECTURE 500 ldr r5, .LCcpu_architecture 501 ldr r5, [r5] 502 cmp r5, #CPU_ARCH_ARMv7 503 blo __und_usr_fault_16 @ 16bit undefined instruction 504/* 505 * The following code won't get run unless the running CPU really is v7, so 506 * coding round the lack of ldrht on older arches is pointless. Temporarily 507 * override the assembler target arch with the minimum required instead: 508 */ 509 .arch armv6t2 510#endif 5112: ldrht r5, [r4] 512ARM_BE8(rev16 r5, r5) @ little endian instruction 513 cmp r5, #0xe800 @ 32bit instruction if xx != 0 514 blo __und_usr_fault_16 @ 16bit undefined instruction 5153: ldrht r0, [r2] 516ARM_BE8(rev16 r0, r0) @ little endian instruction 517 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 518 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 519 orr r0, r0, r5, lsl #16 520 adr lr, BSYM(__und_usr_fault_32) 521 @ r0 = the two 16-bit Thumb instructions which caused the exception 522 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 523 @ r4 = PC value for the first 16-bit Thumb instruction 524 @ lr = 32bit undefined instruction function 525 526#if __LINUX_ARM_ARCH__ < 7 527/* If the target arch was overridden, change it back: */ 528#ifdef CONFIG_CPU_32v6K 529 .arch armv6k 530#else 531 .arch armv6 532#endif 533#endif /* __LINUX_ARM_ARCH__ < 7 */ 534#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 535 b __und_usr_fault_16 536#endif 537 UNWIND(.fnend) 538ENDPROC(__und_usr) 539 540/* 541 * The out of line fixup for the ldrt instructions above. 542 */ 543 .pushsection .fixup, "ax" 544 .align 2 5454: str r4, [sp, #S_PC] @ retry current instruction 546 ret r9 547 .popsection 548 .pushsection __ex_table,"a" 549 .long 1b, 4b 550#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 551 .long 2b, 4b 552 .long 3b, 4b 553#endif 554 .popsection 555 556/* 557 * Check whether the instruction is a co-processor instruction. 558 * If yes, we need to call the relevant co-processor handler. 559 * 560 * Note that we don't do a full check here for the co-processor 561 * instructions; all instructions with bit 27 set are well 562 * defined. The only instructions that should fault are the 563 * co-processor instructions. However, we have to watch out 564 * for the ARM6/ARM7 SWI bug. 565 * 566 * NEON is a special case that has to be handled here. Not all 567 * NEON instructions are co-processor instructions, so we have 568 * to make a special case of checking for them. Plus, there's 569 * five groups of them, so we have a table of mask/opcode pairs 570 * to check against, and if any match then we branch off into the 571 * NEON handler code. 572 * 573 * Emulators may wish to make use of the following registers: 574 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 575 * r2 = PC value to resume execution after successful emulation 576 * r9 = normal "successful" return address 577 * r10 = this threads thread_info structure 578 * lr = unrecognised instruction return address 579 * IRQs enabled, FIQs enabled. 580 */ 581 @ 582 @ Fall-through from Thumb-2 __und_usr 583 @ 584#ifdef CONFIG_NEON 585 get_thread_info r10 @ get current thread 586 adr r6, .LCneon_thumb_opcodes 587 b 2f 588#endif 589call_fpe: 590 get_thread_info r10 @ get current thread 591#ifdef CONFIG_NEON 592 adr r6, .LCneon_arm_opcodes 5932: ldr r5, [r6], #4 @ mask value 594 ldr r7, [r6], #4 @ opcode bits matching in mask 595 cmp r5, #0 @ end mask? 596 beq 1f 597 and r8, r0, r5 598 cmp r8, r7 @ NEON instruction? 599 bne 2b 600 mov r7, #1 601 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 602 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 603 b do_vfp @ let VFP handler handle this 6041: 605#endif 606 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 607 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 608 reteq lr 609 and r8, r0, #0x00000f00 @ mask out CP number 610 THUMB( lsr r8, r8, #8 ) 611 mov r7, #1 612 add r6, r10, #TI_USED_CP 613 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 614 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 615#ifdef CONFIG_IWMMXT 616 @ Test if we need to give access to iWMMXt coprocessors 617 ldr r5, [r10, #TI_FLAGS] 618 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 619 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 620 bcs iwmmxt_task_enable 621#endif 622 ARM( add pc, pc, r8, lsr #6 ) 623 THUMB( lsl r8, r8, #2 ) 624 THUMB( add pc, r8 ) 625 nop 626 627 ret.w lr @ CP#0 628 W(b) do_fpe @ CP#1 (FPE) 629 W(b) do_fpe @ CP#2 (FPE) 630 ret.w lr @ CP#3 631#ifdef CONFIG_CRUNCH 632 b crunch_task_enable @ CP#4 (MaverickCrunch) 633 b crunch_task_enable @ CP#5 (MaverickCrunch) 634 b crunch_task_enable @ CP#6 (MaverickCrunch) 635#else 636 ret.w lr @ CP#4 637 ret.w lr @ CP#5 638 ret.w lr @ CP#6 639#endif 640 ret.w lr @ CP#7 641 ret.w lr @ CP#8 642 ret.w lr @ CP#9 643#ifdef CONFIG_VFP 644 W(b) do_vfp @ CP#10 (VFP) 645 W(b) do_vfp @ CP#11 (VFP) 646#else 647 ret.w lr @ CP#10 (VFP) 648 ret.w lr @ CP#11 (VFP) 649#endif 650 ret.w lr @ CP#12 651 ret.w lr @ CP#13 652 ret.w lr @ CP#14 (Debug) 653 ret.w lr @ CP#15 (Control) 654 655#ifdef NEED_CPU_ARCHITECTURE 656 .align 2 657.LCcpu_architecture: 658 .word __cpu_architecture 659#endif 660 661#ifdef CONFIG_NEON 662 .align 6 663 664.LCneon_arm_opcodes: 665 .word 0xfe000000 @ mask 666 .word 0xf2000000 @ opcode 667 668 .word 0xff100000 @ mask 669 .word 0xf4000000 @ opcode 670 671 .word 0x00000000 @ mask 672 .word 0x00000000 @ opcode 673 674.LCneon_thumb_opcodes: 675 .word 0xef000000 @ mask 676 .word 0xef000000 @ opcode 677 678 .word 0xff100000 @ mask 679 .word 0xf9000000 @ opcode 680 681 .word 0x00000000 @ mask 682 .word 0x00000000 @ opcode 683#endif 684 685do_fpe: 686 ldr r4, .LCfp 687 add r10, r10, #TI_FPSTATE @ r10 = workspace 688 ldr pc, [r4] @ Call FP module USR entry point 689 690/* 691 * The FP module is called with these registers set: 692 * r0 = instruction 693 * r2 = PC+4 694 * r9 = normal "successful" return address 695 * r10 = FP workspace 696 * lr = unrecognised FP instruction return address 697 */ 698 699 .pushsection .data 700ENTRY(fp_enter) 701 .word no_fp 702 .popsection 703 704ENTRY(no_fp) 705 ret lr 706ENDPROC(no_fp) 707 708__und_usr_fault_32: 709 mov r1, #4 710 b 1f 711__und_usr_fault_16: 712 mov r1, #2 7131: mov r0, sp 714 adr lr, BSYM(ret_from_exception) 715 b __und_fault 716ENDPROC(__und_usr_fault_32) 717ENDPROC(__und_usr_fault_16) 718 719 .align 5 720__pabt_usr: 721 usr_entry 722 mov r2, sp @ regs 723 pabt_helper 724 UNWIND(.fnend ) 725 /* fall through */ 726/* 727 * This is the return code to user mode for abort handlers 728 */ 729ENTRY(ret_from_exception) 730 UNWIND(.fnstart ) 731 UNWIND(.cantunwind ) 732 get_thread_info tsk 733 mov why, #0 734 b ret_to_user 735 UNWIND(.fnend ) 736ENDPROC(__pabt_usr) 737ENDPROC(ret_from_exception) 738 739 .align 5 740__fiq_usr: 741 usr_entry trace=0 742 kuser_cmpxchg_check 743 mov r0, sp @ struct pt_regs *regs 744 bl handle_fiq_as_nmi 745 get_thread_info tsk 746 restore_user_regs fast = 0, offset = 0 747 UNWIND(.fnend ) 748ENDPROC(__fiq_usr) 749 750/* 751 * Register switch for ARMv3 and ARMv4 processors 752 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 753 * previous and next are guaranteed not to be the same. 754 */ 755ENTRY(__switch_to) 756 UNWIND(.fnstart ) 757 UNWIND(.cantunwind ) 758 add ip, r1, #TI_CPU_SAVE 759 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 760 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 761 THUMB( str sp, [ip], #4 ) 762 THUMB( str lr, [ip], #4 ) 763 ldr r4, [r2, #TI_TP_VALUE] 764 ldr r5, [r2, #TI_TP_VALUE + 4] 765#ifdef CONFIG_CPU_USE_DOMAINS 766 ldr r6, [r2, #TI_CPU_DOMAIN] 767#endif 768 switch_tls r1, r4, r5, r3, r7 769#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 770 ldr r7, [r2, #TI_TASK] 771 ldr r8, =__stack_chk_guard 772 ldr r7, [r7, #TSK_STACK_CANARY] 773#endif 774#ifdef CONFIG_CPU_USE_DOMAINS 775 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 776#endif 777 mov r5, r0 778 add r4, r2, #TI_CPU_SAVE 779 ldr r0, =thread_notify_head 780 mov r1, #THREAD_NOTIFY_SWITCH 781 bl atomic_notifier_call_chain 782#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 783 str r7, [r8] 784#endif 785 THUMB( mov ip, r4 ) 786 mov r0, r5 787 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 788 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 789 THUMB( ldr sp, [ip], #4 ) 790 THUMB( ldr pc, [ip] ) 791 UNWIND(.fnend ) 792ENDPROC(__switch_to) 793 794 __INIT 795 796/* 797 * User helpers. 798 * 799 * Each segment is 32-byte aligned and will be moved to the top of the high 800 * vector page. New segments (if ever needed) must be added in front of 801 * existing ones. This mechanism should be used only for things that are 802 * really small and justified, and not be abused freely. 803 * 804 * See Documentation/arm/kernel_user_helpers.txt for formal definitions. 805 */ 806 THUMB( .arm ) 807 808 .macro usr_ret, reg 809#ifdef CONFIG_ARM_THUMB 810 bx \reg 811#else 812 ret \reg 813#endif 814 .endm 815 816 .macro kuser_pad, sym, size 817 .if (. - \sym) & 3 818 .rept 4 - (. - \sym) & 3 819 .byte 0 820 .endr 821 .endif 822 .rept (\size - (. - \sym)) / 4 823 .word 0xe7fddef1 824 .endr 825 .endm 826 827#ifdef CONFIG_KUSER_HELPERS 828 .align 5 829 .globl __kuser_helper_start 830__kuser_helper_start: 831 832/* 833 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 834 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 835 */ 836 837__kuser_cmpxchg64: @ 0xffff0f60 838 839#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 840 841 /* 842 * Poor you. No fast solution possible... 843 * The kernel itself must perform the operation. 844 * A special ghost syscall is used for that (see traps.c). 845 */ 846 stmfd sp!, {r7, lr} 847 ldr r7, 1f @ it's 20 bits 848 swi __ARM_NR_cmpxchg64 849 ldmfd sp!, {r7, pc} 8501: .word __ARM_NR_cmpxchg64 851 852#elif defined(CONFIG_CPU_32v6K) 853 854 stmfd sp!, {r4, r5, r6, r7} 855 ldrd r4, r5, [r0] @ load old val 856 ldrd r6, r7, [r1] @ load new val 857 smp_dmb arm 8581: ldrexd r0, r1, [r2] @ load current val 859 eors r3, r0, r4 @ compare with oldval (1) 860 eoreqs r3, r1, r5 @ compare with oldval (2) 861 strexdeq r3, r6, r7, [r2] @ store newval if eq 862 teqeq r3, #1 @ success? 863 beq 1b @ if no then retry 864 smp_dmb arm 865 rsbs r0, r3, #0 @ set returned val and C flag 866 ldmfd sp!, {r4, r5, r6, r7} 867 usr_ret lr 868 869#elif !defined(CONFIG_SMP) 870 871#ifdef CONFIG_MMU 872 873 /* 874 * The only thing that can break atomicity in this cmpxchg64 875 * implementation is either an IRQ or a data abort exception 876 * causing another process/thread to be scheduled in the middle of 877 * the critical sequence. The same strategy as for cmpxchg is used. 878 */ 879 stmfd sp!, {r4, r5, r6, lr} 880 ldmia r0, {r4, r5} @ load old val 881 ldmia r1, {r6, lr} @ load new val 8821: ldmia r2, {r0, r1} @ load current val 883 eors r3, r0, r4 @ compare with oldval (1) 884 eoreqs r3, r1, r5 @ compare with oldval (2) 8852: stmeqia r2, {r6, lr} @ store newval if eq 886 rsbs r0, r3, #0 @ set return val and C flag 887 ldmfd sp!, {r4, r5, r6, pc} 888 889 .text 890kuser_cmpxchg64_fixup: 891 @ Called from kuser_cmpxchg_fixup. 892 @ r4 = address of interrupted insn (must be preserved). 893 @ sp = saved regs. r7 and r8 are clobbered. 894 @ 1b = first critical insn, 2b = last critical insn. 895 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 896 mov r7, #0xffff0fff 897 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 898 subs r8, r4, r7 899 rsbcss r8, r8, #(2b - 1b) 900 strcs r7, [sp, #S_PC] 901#if __LINUX_ARM_ARCH__ < 6 902 bcc kuser_cmpxchg32_fixup 903#endif 904 ret lr 905 .previous 906 907#else 908#warning "NPTL on non MMU needs fixing" 909 mov r0, #-1 910 adds r0, r0, #0 911 usr_ret lr 912#endif 913 914#else 915#error "incoherent kernel configuration" 916#endif 917 918 kuser_pad __kuser_cmpxchg64, 64 919 920__kuser_memory_barrier: @ 0xffff0fa0 921 smp_dmb arm 922 usr_ret lr 923 924 kuser_pad __kuser_memory_barrier, 32 925 926__kuser_cmpxchg: @ 0xffff0fc0 927 928#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 929 930 /* 931 * Poor you. No fast solution possible... 932 * The kernel itself must perform the operation. 933 * A special ghost syscall is used for that (see traps.c). 934 */ 935 stmfd sp!, {r7, lr} 936 ldr r7, 1f @ it's 20 bits 937 swi __ARM_NR_cmpxchg 938 ldmfd sp!, {r7, pc} 9391: .word __ARM_NR_cmpxchg 940 941#elif __LINUX_ARM_ARCH__ < 6 942 943#ifdef CONFIG_MMU 944 945 /* 946 * The only thing that can break atomicity in this cmpxchg 947 * implementation is either an IRQ or a data abort exception 948 * causing another process/thread to be scheduled in the middle 949 * of the critical sequence. To prevent this, code is added to 950 * the IRQ and data abort exception handlers to set the pc back 951 * to the beginning of the critical section if it is found to be 952 * within that critical section (see kuser_cmpxchg_fixup). 953 */ 9541: ldr r3, [r2] @ load current val 955 subs r3, r3, r0 @ compare with oldval 9562: streq r1, [r2] @ store newval if eq 957 rsbs r0, r3, #0 @ set return val and C flag 958 usr_ret lr 959 960 .text 961kuser_cmpxchg32_fixup: 962 @ Called from kuser_cmpxchg_check macro. 963 @ r4 = address of interrupted insn (must be preserved). 964 @ sp = saved regs. r7 and r8 are clobbered. 965 @ 1b = first critical insn, 2b = last critical insn. 966 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 967 mov r7, #0xffff0fff 968 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 969 subs r8, r4, r7 970 rsbcss r8, r8, #(2b - 1b) 971 strcs r7, [sp, #S_PC] 972 ret lr 973 .previous 974 975#else 976#warning "NPTL on non MMU needs fixing" 977 mov r0, #-1 978 adds r0, r0, #0 979 usr_ret lr 980#endif 981 982#else 983 984 smp_dmb arm 9851: ldrex r3, [r2] 986 subs r3, r3, r0 987 strexeq r3, r1, [r2] 988 teqeq r3, #1 989 beq 1b 990 rsbs r0, r3, #0 991 /* beware -- each __kuser slot must be 8 instructions max */ 992 ALT_SMP(b __kuser_memory_barrier) 993 ALT_UP(usr_ret lr) 994 995#endif 996 997 kuser_pad __kuser_cmpxchg, 32 998 999__kuser_get_tls: @ 0xffff0fe0 1000 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1001 usr_ret lr 1002 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1003 kuser_pad __kuser_get_tls, 16 1004 .rep 3 1005 .word 0 @ 0xffff0ff0 software TLS value, then 1006 .endr @ pad up to __kuser_helper_version 1007 1008__kuser_helper_version: @ 0xffff0ffc 1009 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1010 1011 .globl __kuser_helper_end 1012__kuser_helper_end: 1013 1014#endif 1015 1016 THUMB( .thumb ) 1017 1018/* 1019 * Vector stubs. 1020 * 1021 * This code is copied to 0xffff1000 so we can use branches in the 1022 * vectors, rather than ldr's. Note that this code must not exceed 1023 * a page size. 1024 * 1025 * Common stub entry macro: 1026 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1027 * 1028 * SP points to a minimal amount of processor-private memory, the address 1029 * of which is copied into r0 for the mode specific abort handler. 1030 */ 1031 .macro vector_stub, name, mode, correction=0 1032 .align 5 1033 1034vector_\name: 1035 .if \correction 1036 sub lr, lr, #\correction 1037 .endif 1038 1039 @ 1040 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1041 @ (parent CPSR) 1042 @ 1043 stmia sp, {r0, lr} @ save r0, lr 1044 mrs lr, spsr 1045 str lr, [sp, #8] @ save spsr 1046 1047 @ 1048 @ Prepare for SVC32 mode. IRQs remain disabled. 1049 @ 1050 mrs r0, cpsr 1051 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1052 msr spsr_cxsf, r0 1053 1054 @ 1055 @ the branch table must immediately follow this code 1056 @ 1057 and lr, lr, #0x0f 1058 THUMB( adr r0, 1f ) 1059 THUMB( ldr lr, [r0, lr, lsl #2] ) 1060 mov r0, sp 1061 ARM( ldr lr, [pc, lr, lsl #2] ) 1062 movs pc, lr @ branch to handler in SVC mode 1063ENDPROC(vector_\name) 1064 1065 .align 2 1066 @ handler addresses follow this label 10671: 1068 .endm 1069 1070 .section .stubs, "ax", %progbits 1071__stubs_start: 1072 @ This must be the first word 1073 .word vector_swi 1074 1075vector_rst: 1076 ARM( swi SYS_ERROR0 ) 1077 THUMB( svc #0 ) 1078 THUMB( nop ) 1079 b vector_und 1080 1081/* 1082 * Interrupt dispatcher 1083 */ 1084 vector_stub irq, IRQ_MODE, 4 1085 1086 .long __irq_usr @ 0 (USR_26 / USR_32) 1087 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1088 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1089 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1090 .long __irq_invalid @ 4 1091 .long __irq_invalid @ 5 1092 .long __irq_invalid @ 6 1093 .long __irq_invalid @ 7 1094 .long __irq_invalid @ 8 1095 .long __irq_invalid @ 9 1096 .long __irq_invalid @ a 1097 .long __irq_invalid @ b 1098 .long __irq_invalid @ c 1099 .long __irq_invalid @ d 1100 .long __irq_invalid @ e 1101 .long __irq_invalid @ f 1102 1103/* 1104 * Data abort dispatcher 1105 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1106 */ 1107 vector_stub dabt, ABT_MODE, 8 1108 1109 .long __dabt_usr @ 0 (USR_26 / USR_32) 1110 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1111 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1112 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1113 .long __dabt_invalid @ 4 1114 .long __dabt_invalid @ 5 1115 .long __dabt_invalid @ 6 1116 .long __dabt_invalid @ 7 1117 .long __dabt_invalid @ 8 1118 .long __dabt_invalid @ 9 1119 .long __dabt_invalid @ a 1120 .long __dabt_invalid @ b 1121 .long __dabt_invalid @ c 1122 .long __dabt_invalid @ d 1123 .long __dabt_invalid @ e 1124 .long __dabt_invalid @ f 1125 1126/* 1127 * Prefetch abort dispatcher 1128 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1129 */ 1130 vector_stub pabt, ABT_MODE, 4 1131 1132 .long __pabt_usr @ 0 (USR_26 / USR_32) 1133 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1134 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1135 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1136 .long __pabt_invalid @ 4 1137 .long __pabt_invalid @ 5 1138 .long __pabt_invalid @ 6 1139 .long __pabt_invalid @ 7 1140 .long __pabt_invalid @ 8 1141 .long __pabt_invalid @ 9 1142 .long __pabt_invalid @ a 1143 .long __pabt_invalid @ b 1144 .long __pabt_invalid @ c 1145 .long __pabt_invalid @ d 1146 .long __pabt_invalid @ e 1147 .long __pabt_invalid @ f 1148 1149/* 1150 * Undef instr entry dispatcher 1151 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1152 */ 1153 vector_stub und, UND_MODE 1154 1155 .long __und_usr @ 0 (USR_26 / USR_32) 1156 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1157 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1158 .long __und_svc @ 3 (SVC_26 / SVC_32) 1159 .long __und_invalid @ 4 1160 .long __und_invalid @ 5 1161 .long __und_invalid @ 6 1162 .long __und_invalid @ 7 1163 .long __und_invalid @ 8 1164 .long __und_invalid @ 9 1165 .long __und_invalid @ a 1166 .long __und_invalid @ b 1167 .long __und_invalid @ c 1168 .long __und_invalid @ d 1169 .long __und_invalid @ e 1170 .long __und_invalid @ f 1171 1172 .align 5 1173 1174/*============================================================================= 1175 * Address exception handler 1176 *----------------------------------------------------------------------------- 1177 * These aren't too critical. 1178 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1179 */ 1180 1181vector_addrexcptn: 1182 b vector_addrexcptn 1183 1184/*============================================================================= 1185 * FIQ "NMI" handler 1186 *----------------------------------------------------------------------------- 1187 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1188 * systems. 1189 */ 1190 vector_stub fiq, FIQ_MODE, 4 1191 1192 .long __fiq_usr @ 0 (USR_26 / USR_32) 1193 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1194 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1195 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1196 .long __fiq_svc @ 4 1197 .long __fiq_svc @ 5 1198 .long __fiq_svc @ 6 1199 .long __fiq_abt @ 7 1200 .long __fiq_svc @ 8 1201 .long __fiq_svc @ 9 1202 .long __fiq_svc @ a 1203 .long __fiq_svc @ b 1204 .long __fiq_svc @ c 1205 .long __fiq_svc @ d 1206 .long __fiq_svc @ e 1207 .long __fiq_svc @ f 1208 1209 .globl vector_fiq_offset 1210 .equ vector_fiq_offset, vector_fiq 1211 1212 .section .vectors, "ax", %progbits 1213__vectors_start: 1214 W(b) vector_rst 1215 W(b) vector_und 1216 W(ldr) pc, __vectors_start + 0x1000 1217 W(b) vector_pabt 1218 W(b) vector_dabt 1219 W(b) vector_addrexcptn 1220 W(b) vector_irq 1221 W(b) vector_fiq 1222 1223 .data 1224 1225 .globl cr_alignment 1226cr_alignment: 1227 .space 4 1228 1229#ifdef CONFIG_MULTI_IRQ_HANDLER 1230 .globl handle_arch_irq 1231handle_arch_irq: 1232 .space 4 1233#endif 1234