1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * 9 * Low-level vector interface routines 10 * 11 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 12 * that causes it to save wrong values... Be aware! 13 */ 14 15#include <linux/init.h> 16 17#include <asm/assembler.h> 18#include <asm/memory.h> 19#include <asm/glue-df.h> 20#include <asm/glue-pf.h> 21#include <asm/vfpmacros.h> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24#include <asm/unistd.h> 25#include <asm/tls.h> 26#include <asm/system_info.h> 27#include <asm/uaccess-asm.h> 28 29#include "entry-header.S" 30#include <asm/probes.h> 31 32/* 33 * Interrupt handling. 34 */ 35 .macro irq_handler, from_user:req 36 mov r0, sp 37#ifdef CONFIG_IRQSTACKS 38#ifdef CONFIG_UNWINDER_ARM 39 mov fpreg, sp @ Preserve original SP 40#else 41 mov r7, fp @ Preserve original FP 42 mov r8, sp @ Preserve original SP 43#endif 44 ldr_this_cpu sp, irq_stack_ptr, r2, r3 45 .if \from_user == 0 46UNWIND( .setfp fpreg, sp ) 47 @ 48 @ If we took the interrupt while running in the kernel, we may already 49 @ be using the IRQ stack, so revert to the original value in that case. 50 @ 51 subs r2, sp, r0 @ SP above bottom of IRQ stack? 52 rsbscs r2, r2, #THREAD_SIZE @ ... and below the top? 53#ifdef CONFIG_VMAP_STACK 54 ldr_va r2, high_memory, cc @ End of the linear region 55 cmpcc r2, r0 @ Stack pointer was below it? 56#endif 57 movcs sp, r0 @ If so, revert to incoming SP 58 59#ifndef CONFIG_UNWINDER_ARM 60 @ 61 @ Inform the frame pointer unwinder where the next frame lives 62 @ 63 movcc lr, pc @ Make LR point into .entry.text so 64 @ that we will get a dump of the 65 @ exception stack for this frame. 66#ifdef CONFIG_CC_IS_GCC 67 movcc ip, r0 @ Store the old SP in the frame record. 68 stmdbcc sp!, {fp, ip, lr, pc} @ Push frame record 69 addcc fp, sp, #12 70#else 71 stmdbcc sp!, {fp, lr} @ Push frame record 72 movcc fp, sp 73#endif // CONFIG_CC_IS_GCC 74#endif // CONFIG_UNWINDER_ARM 75 .endif 76#endif // CONFIG_IRQSTACKS 77 78 bl generic_handle_arch_irq 79 80#ifdef CONFIG_IRQSTACKS 81#ifdef CONFIG_UNWINDER_ARM 82 mov sp, fpreg @ Restore original SP 83#else 84 mov fp, r7 @ Restore original FP 85 mov sp, r8 @ Restore original SP 86#endif // CONFIG_UNWINDER_ARM 87#endif // CONFIG_IRQSTACKS 88 .endm 89 90 .macro pabt_helper 91 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 92#ifdef MULTI_PABORT 93 ldr ip, .LCprocfns 94 mov lr, pc 95 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 96#else 97 bl CPU_PABORT_HANDLER 98#endif 99 .endm 100 101 .macro dabt_helper 102 103 @ 104 @ Call the processor-specific abort handler: 105 @ 106 @ r2 - pt_regs 107 @ r4 - aborted context pc 108 @ r5 - aborted context psr 109 @ 110 @ The abort handler must return the aborted address in r0, and 111 @ the fault status register in r1. r9 must be preserved. 112 @ 113#ifdef MULTI_DABORT 114 ldr ip, .LCprocfns 115 mov lr, pc 116 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 117#else 118 bl CPU_DABORT_HANDLER 119#endif 120 .endm 121 122 .section .entry.text,"ax",%progbits 123 124/* 125 * Invalid mode handlers 126 */ 127 .macro inv_entry, reason 128 sub sp, sp, #PT_REGS_SIZE 129 ARM( stmib sp, {r1 - lr} ) 130 THUMB( stmia sp, {r0 - r12} ) 131 THUMB( str sp, [sp, #S_SP] ) 132 THUMB( str lr, [sp, #S_LR] ) 133 mov r1, #\reason 134 .endm 135 136__pabt_invalid: 137 inv_entry BAD_PREFETCH 138 b common_invalid 139ENDPROC(__pabt_invalid) 140 141__dabt_invalid: 142 inv_entry BAD_DATA 143 b common_invalid 144ENDPROC(__dabt_invalid) 145 146__irq_invalid: 147 inv_entry BAD_IRQ 148 b common_invalid 149ENDPROC(__irq_invalid) 150 151__und_invalid: 152 inv_entry BAD_UNDEFINSTR 153 154 @ 155 @ XXX fall through to common_invalid 156 @ 157 158@ 159@ common_invalid - generic code for failed exception (re-entrant version of handlers) 160@ 161common_invalid: 162 zero_fp 163 164 ldmia r0, {r4 - r6} 165 add r0, sp, #S_PC @ here for interlock avoidance 166 mov r7, #-1 @ "" "" "" "" 167 str r4, [sp] @ save preserved r0 168 stmia r0, {r5 - r7} @ lr_<exception>, 169 @ cpsr_<exception>, "old_r0" 170 171 mov r0, sp 172 b bad_mode 173ENDPROC(__und_invalid) 174 175/* 176 * SVC mode handlers 177 */ 178 179#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 180#define SPFIX(code...) code 181#else 182#define SPFIX(code...) 183#endif 184 185 .macro svc_entry, stack_hole=0, trace=1, uaccess=1, overflow_check=1 186 UNWIND(.fnstart ) 187 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole) 188 THUMB( add sp, r1 ) @ get SP in a GPR without 189 THUMB( sub r1, sp, r1 ) @ using a temp register 190 191 .if \overflow_check 192 UNWIND(.save {r0 - pc} ) 193 do_overflow_check (SVC_REGS_SIZE + \stack_hole) 194 .endif 195 196#ifdef CONFIG_THUMB2_KERNEL 197 tst r1, #4 @ test stack pointer alignment 198 sub r1, sp, r1 @ restore original R1 199 sub sp, r1 @ restore original SP 200#else 201 SPFIX( tst sp, #4 ) 202#endif 203 SPFIX( subne sp, sp, #4 ) 204 205 ARM( stmib sp, {r1 - r12} ) 206 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2 207 208 ldmia r0, {r3 - r5} 209 add r7, sp, #S_SP @ here for interlock avoidance 210 mov r6, #-1 @ "" "" "" "" 211 add r2, sp, #(SVC_REGS_SIZE + \stack_hole) 212 SPFIX( addne r2, r2, #4 ) 213 str r3, [sp] @ save the "real" r0 copied 214 @ from the exception stack 215 216 mov r3, lr 217 218 @ 219 @ We are now ready to fill in the remaining blanks on the stack: 220 @ 221 @ r2 - sp_svc 222 @ r3 - lr_svc 223 @ r4 - lr_<exception>, already fixed up for correct return/restart 224 @ r5 - spsr_<exception> 225 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 226 @ 227 stmia r7, {r2 - r6} 228 229 get_thread_info tsk 230 uaccess_entry tsk, r0, r1, r2, \uaccess 231 232 .if \trace 233#ifdef CONFIG_TRACE_IRQFLAGS 234 bl trace_hardirqs_off 235#endif 236 .endif 237 .endm 238 239 .align 5 240__dabt_svc: 241 svc_entry uaccess=0 242 mov r2, sp 243 dabt_helper 244 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 245 svc_exit r5 @ return from exception 246 UNWIND(.fnend ) 247ENDPROC(__dabt_svc) 248 249 .align 5 250__irq_svc: 251 svc_entry 252 irq_handler from_user=0 253 254#ifdef CONFIG_PREEMPTION 255 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 256 ldr r0, [tsk, #TI_FLAGS] @ get flags 257 teq r8, #0 @ if preempt count != 0 258 movne r0, #0 @ force flags to 0 259 tst r0, #_TIF_NEED_RESCHED 260 blne svc_preempt 261#endif 262 263 svc_exit r5, irq = 1 @ return from exception 264 UNWIND(.fnend ) 265ENDPROC(__irq_svc) 266 267 .ltorg 268 269#ifdef CONFIG_PREEMPTION 270svc_preempt: 271 mov r8, lr 2721: bl preempt_schedule_irq @ irq en/disable is done inside 273 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 274 tst r0, #_TIF_NEED_RESCHED 275 reteq r8 @ go again 276 b 1b 277#endif 278 279__und_fault: 280 @ Correct the PC such that it is pointing at the instruction 281 @ which caused the fault. If the faulting instruction was ARM 282 @ the PC will be pointing at the next instruction, and have to 283 @ subtract 4. Otherwise, it is Thumb, and the PC will be 284 @ pointing at the second half of the Thumb instruction. We 285 @ have to subtract 2. 286 ldr r2, [r0, #S_PC] 287 sub r2, r2, r1 288 str r2, [r0, #S_PC] 289 b do_undefinstr 290ENDPROC(__und_fault) 291 292 .align 5 293__und_svc: 294#ifdef CONFIG_KPROBES 295 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 296 @ it obviously needs free stack space which then will belong to 297 @ the saved context. 298 svc_entry MAX_STACK_SIZE 299#else 300 svc_entry 301#endif 302 303 mov r1, #4 @ PC correction to apply 304 THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? 305 THUMB( movne r1, #2 ) @ if so, fix up PC correction 306 mov r0, sp @ struct pt_regs *regs 307 bl __und_fault 308 309__und_svc_finish: 310 get_thread_info tsk 311 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 312 svc_exit r5 @ return from exception 313 UNWIND(.fnend ) 314ENDPROC(__und_svc) 315 316 .align 5 317__pabt_svc: 318 svc_entry 319 mov r2, sp @ regs 320 pabt_helper 321 svc_exit r5 @ return from exception 322 UNWIND(.fnend ) 323ENDPROC(__pabt_svc) 324 325 .align 5 326__fiq_svc: 327 svc_entry trace=0 328 mov r0, sp @ struct pt_regs *regs 329 bl handle_fiq_as_nmi 330 svc_exit_via_fiq 331 UNWIND(.fnend ) 332ENDPROC(__fiq_svc) 333 334 .align 5 335.LCcralign: 336 .word cr_alignment 337#ifdef MULTI_DABORT 338.LCprocfns: 339 .word processor 340#endif 341.LCfp: 342 .word fp_enter 343 344/* 345 * Abort mode handlers 346 */ 347 348@ 349@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode 350@ and reuses the same macros. However in abort mode we must also 351@ save/restore lr_abt and spsr_abt to make nested aborts safe. 352@ 353 .align 5 354__fiq_abt: 355 svc_entry trace=0 356 357 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 358 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 359 THUMB( msr cpsr_c, r0 ) 360 mov r1, lr @ Save lr_abt 361 mrs r2, spsr @ Save spsr_abt, abort is now safe 362 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 363 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 364 THUMB( msr cpsr_c, r0 ) 365 stmfd sp!, {r1 - r2} 366 367 add r0, sp, #8 @ struct pt_regs *regs 368 bl handle_fiq_as_nmi 369 370 ldmfd sp!, {r1 - r2} 371 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 372 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) 373 THUMB( msr cpsr_c, r0 ) 374 mov lr, r1 @ Restore lr_abt, abort is unsafe 375 msr spsr_cxsf, r2 @ Restore spsr_abt 376 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 377 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) 378 THUMB( msr cpsr_c, r0 ) 379 380 svc_exit_via_fiq 381 UNWIND(.fnend ) 382ENDPROC(__fiq_abt) 383 384/* 385 * User mode handlers 386 * 387 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE 388 */ 389 390#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) 391#error "sizeof(struct pt_regs) must be a multiple of 8" 392#endif 393 394 .macro usr_entry, trace=1, uaccess=1 395 UNWIND(.fnstart ) 396 UNWIND(.cantunwind ) @ don't unwind the user space 397 sub sp, sp, #PT_REGS_SIZE 398 ARM( stmib sp, {r1 - r12} ) 399 THUMB( stmia sp, {r0 - r12} ) 400 401 ATRAP( mrc p15, 0, r7, c1, c0, 0) 402 ATRAP( ldr r8, .LCcralign) 403 404 ldmia r0, {r3 - r5} 405 add r0, sp, #S_PC @ here for interlock avoidance 406 mov r6, #-1 @ "" "" "" "" 407 408 str r3, [sp] @ save the "real" r0 copied 409 @ from the exception stack 410 411 ATRAP( ldr r8, [r8, #0]) 412 413 @ 414 @ We are now ready to fill in the remaining blanks on the stack: 415 @ 416 @ r4 - lr_<exception>, already fixed up for correct return/restart 417 @ r5 - spsr_<exception> 418 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 419 @ 420 @ Also, separately save sp_usr and lr_usr 421 @ 422 stmia r0, {r4 - r6} 423 ARM( stmdb r0, {sp, lr}^ ) 424 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 425 426 .if \uaccess 427 uaccess_disable ip 428 .endif 429 430 @ Enable the alignment trap while in kernel mode 431 ATRAP( teq r8, r7) 432 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 433 434 reload_current r7, r8 435 436 @ 437 @ Clear FP to mark the first stack frame 438 @ 439 zero_fp 440 441 .if \trace 442#ifdef CONFIG_TRACE_IRQFLAGS 443 bl trace_hardirqs_off 444#endif 445 ct_user_exit save = 0 446 .endif 447 .endm 448 449 .macro kuser_cmpxchg_check 450#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) 451#ifndef CONFIG_MMU 452#warning "NPTL on non MMU needs fixing" 453#else 454 @ Make sure our user space atomic helper is restarted 455 @ if it was interrupted in a critical region. Here we 456 @ perform a quick test inline since it should be false 457 @ 99.9999% of the time. The rest is done out of line. 458 ldr r0, =TASK_SIZE 459 cmp r4, r0 460 blhs kuser_cmpxchg64_fixup 461#endif 462#endif 463 .endm 464 465 .align 5 466__dabt_usr: 467 usr_entry uaccess=0 468 kuser_cmpxchg_check 469 mov r2, sp 470 dabt_helper 471 b ret_from_exception 472 UNWIND(.fnend ) 473ENDPROC(__dabt_usr) 474 475 .align 5 476__irq_usr: 477 usr_entry 478 kuser_cmpxchg_check 479 irq_handler from_user=1 480 get_thread_info tsk 481 mov why, #0 482 b ret_to_user_from_irq 483 UNWIND(.fnend ) 484ENDPROC(__irq_usr) 485 486 .ltorg 487 488 .align 5 489__und_usr: 490 usr_entry uaccess=0 491 492 mov r2, r4 493 mov r3, r5 494 495 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 496 @ faulting instruction depending on Thumb mode. 497 @ r3 = regs->ARM_cpsr 498 @ 499 @ The emulation code returns using r9 if it has emulated the 500 @ instruction, or the more conventional lr if we are to treat 501 @ this as a real undefined instruction 502 @ 503 badr r9, ret_from_exception 504 505 @ IRQs must be enabled before attempting to read the instruction from 506 @ user space since that could cause a page/translation fault if the 507 @ page table was modified by another CPU. 508 enable_irq 509 510 tst r3, #PSR_T_BIT @ Thumb mode? 511 bne __und_usr_thumb 512 sub r4, r2, #4 @ ARM instr at LR - 4 5131: ldrt r0, [r4] 514 ARM_BE8(rev r0, r0) @ little endian instruction 515 516 uaccess_disable ip 517 518 @ r0 = 32-bit ARM instruction which caused the exception 519 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 520 @ r4 = PC value for the faulting instruction 521 @ lr = 32-bit undefined instruction function 522 badr lr, __und_usr_fault_32 523 b call_fpe 524 525__und_usr_thumb: 526 @ Thumb instruction 527 sub r4, r2, #2 @ First half of thumb instr at LR - 2 528#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 529/* 530 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 531 * can never be supported in a single kernel, this code is not applicable at 532 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 533 * made about .arch directives. 534 */ 535#if __LINUX_ARM_ARCH__ < 7 536/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 537#define NEED_CPU_ARCHITECTURE 538 ldr r5, .LCcpu_architecture 539 ldr r5, [r5] 540 cmp r5, #CPU_ARCH_ARMv7 541 blo __und_usr_fault_16 @ 16bit undefined instruction 542/* 543 * The following code won't get run unless the running CPU really is v7, so 544 * coding round the lack of ldrht on older arches is pointless. Temporarily 545 * override the assembler target arch with the minimum required instead: 546 */ 547 .arch armv6t2 548#endif 5492: ldrht r5, [r4] 550ARM_BE8(rev16 r5, r5) @ little endian instruction 551 cmp r5, #0xe800 @ 32bit instruction if xx != 0 552 blo __und_usr_fault_16_pan @ 16bit undefined instruction 5533: ldrht r0, [r2] 554ARM_BE8(rev16 r0, r0) @ little endian instruction 555 uaccess_disable ip 556 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 557 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 558 orr r0, r0, r5, lsl #16 559 badr lr, __und_usr_fault_32 560 @ r0 = the two 16-bit Thumb instructions which caused the exception 561 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 562 @ r4 = PC value for the first 16-bit Thumb instruction 563 @ lr = 32bit undefined instruction function 564 565#if __LINUX_ARM_ARCH__ < 7 566/* If the target arch was overridden, change it back: */ 567#ifdef CONFIG_CPU_32v6K 568 .arch armv6k 569#else 570 .arch armv6 571#endif 572#endif /* __LINUX_ARM_ARCH__ < 7 */ 573#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 574 b __und_usr_fault_16 575#endif 576 UNWIND(.fnend) 577ENDPROC(__und_usr) 578 579/* 580 * The out of line fixup for the ldrt instructions above. 581 */ 582 .pushsection .text.fixup, "ax" 583 .align 2 5844: str r4, [sp, #S_PC] @ retry current instruction 585 ret r9 586 .popsection 587 .pushsection __ex_table,"a" 588 .long 1b, 4b 589#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 590 .long 2b, 4b 591 .long 3b, 4b 592#endif 593 .popsection 594 595/* 596 * Check whether the instruction is a co-processor instruction. 597 * If yes, we need to call the relevant co-processor handler. 598 * 599 * Note that we don't do a full check here for the co-processor 600 * instructions; all instructions with bit 27 set are well 601 * defined. The only instructions that should fault are the 602 * co-processor instructions. However, we have to watch out 603 * for the ARM6/ARM7 SWI bug. 604 * 605 * NEON is a special case that has to be handled here. Not all 606 * NEON instructions are co-processor instructions, so we have 607 * to make a special case of checking for them. Plus, there's 608 * five groups of them, so we have a table of mask/opcode pairs 609 * to check against, and if any match then we branch off into the 610 * NEON handler code. 611 * 612 * Emulators may wish to make use of the following registers: 613 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 614 * r2 = PC value to resume execution after successful emulation 615 * r9 = normal "successful" return address 616 * r10 = this threads thread_info structure 617 * lr = unrecognised instruction return address 618 * IRQs enabled, FIQs enabled. 619 */ 620 @ 621 @ Fall-through from Thumb-2 __und_usr 622 @ 623#ifdef CONFIG_NEON 624 get_thread_info r10 @ get current thread 625 adr r6, .LCneon_thumb_opcodes 626 b 2f 627#endif 628call_fpe: 629 get_thread_info r10 @ get current thread 630#ifdef CONFIG_NEON 631 adr r6, .LCneon_arm_opcodes 6322: ldr r5, [r6], #4 @ mask value 633 ldr r7, [r6], #4 @ opcode bits matching in mask 634 cmp r5, #0 @ end mask? 635 beq 1f 636 and r8, r0, r5 637 cmp r8, r7 @ NEON instruction? 638 bne 2b 639 mov r7, #1 640 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 641 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 642 b do_vfp @ let VFP handler handle this 6431: 644#endif 645 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 646 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 647 reteq lr 648 and r8, r0, #0x00000f00 @ mask out CP number 649 THUMB( lsr r8, r8, #8 ) 650 mov r7, #1 651 add r6, r10, #TI_USED_CP 652 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 653 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 654#ifdef CONFIG_IWMMXT 655 @ Test if we need to give access to iWMMXt coprocessors 656 ldr r5, [r10, #TI_FLAGS] 657 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 658 movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 659 bcs iwmmxt_task_enable 660#endif 661 ARM( add pc, pc, r8, lsr #6 ) 662 THUMB( lsl r8, r8, #2 ) 663 THUMB( add pc, r8 ) 664 nop 665 666 ret.w lr @ CP#0 667 W(b) do_fpe @ CP#1 (FPE) 668 W(b) do_fpe @ CP#2 (FPE) 669 ret.w lr @ CP#3 670 ret.w lr @ CP#4 671 ret.w lr @ CP#5 672 ret.w lr @ CP#6 673 ret.w lr @ CP#7 674 ret.w lr @ CP#8 675 ret.w lr @ CP#9 676#ifdef CONFIG_VFP 677 W(b) do_vfp @ CP#10 (VFP) 678 W(b) do_vfp @ CP#11 (VFP) 679#else 680 ret.w lr @ CP#10 (VFP) 681 ret.w lr @ CP#11 (VFP) 682#endif 683 ret.w lr @ CP#12 684 ret.w lr @ CP#13 685 ret.w lr @ CP#14 (Debug) 686 ret.w lr @ CP#15 (Control) 687 688#ifdef NEED_CPU_ARCHITECTURE 689 .align 2 690.LCcpu_architecture: 691 .word __cpu_architecture 692#endif 693 694#ifdef CONFIG_NEON 695 .align 6 696 697.LCneon_arm_opcodes: 698 .word 0xfe000000 @ mask 699 .word 0xf2000000 @ opcode 700 701 .word 0xff100000 @ mask 702 .word 0xf4000000 @ opcode 703 704 .word 0x00000000 @ mask 705 .word 0x00000000 @ opcode 706 707.LCneon_thumb_opcodes: 708 .word 0xef000000 @ mask 709 .word 0xef000000 @ opcode 710 711 .word 0xff100000 @ mask 712 .word 0xf9000000 @ opcode 713 714 .word 0x00000000 @ mask 715 .word 0x00000000 @ opcode 716#endif 717 718do_fpe: 719 ldr r4, .LCfp 720 add r10, r10, #TI_FPSTATE @ r10 = workspace 721 ldr pc, [r4] @ Call FP module USR entry point 722 723/* 724 * The FP module is called with these registers set: 725 * r0 = instruction 726 * r2 = PC+4 727 * r9 = normal "successful" return address 728 * r10 = FP workspace 729 * lr = unrecognised FP instruction return address 730 */ 731 732 .pushsection .data 733 .align 2 734ENTRY(fp_enter) 735 .word no_fp 736 .popsection 737 738ENTRY(no_fp) 739 ret lr 740ENDPROC(no_fp) 741 742__und_usr_fault_32: 743 mov r1, #4 744 b 1f 745__und_usr_fault_16_pan: 746 uaccess_disable ip 747__und_usr_fault_16: 748 mov r1, #2 7491: mov r0, sp 750 badr lr, ret_from_exception 751 b __und_fault 752ENDPROC(__und_usr_fault_32) 753ENDPROC(__und_usr_fault_16) 754 755 .align 5 756__pabt_usr: 757 usr_entry 758 mov r2, sp @ regs 759 pabt_helper 760 UNWIND(.fnend ) 761 /* fall through */ 762/* 763 * This is the return code to user mode for abort handlers 764 */ 765ENTRY(ret_from_exception) 766 UNWIND(.fnstart ) 767 UNWIND(.cantunwind ) 768 get_thread_info tsk 769 mov why, #0 770 b ret_to_user 771 UNWIND(.fnend ) 772ENDPROC(__pabt_usr) 773ENDPROC(ret_from_exception) 774 775 .align 5 776__fiq_usr: 777 usr_entry trace=0 778 kuser_cmpxchg_check 779 mov r0, sp @ struct pt_regs *regs 780 bl handle_fiq_as_nmi 781 get_thread_info tsk 782 restore_user_regs fast = 0, offset = 0 783 UNWIND(.fnend ) 784ENDPROC(__fiq_usr) 785 786/* 787 * Register switch for ARMv3 and ARMv4 processors 788 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 789 * previous and next are guaranteed not to be the same. 790 */ 791ENTRY(__switch_to) 792 UNWIND(.fnstart ) 793 UNWIND(.cantunwind ) 794 add ip, r1, #TI_CPU_SAVE 795 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 796 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 797 THUMB( str sp, [ip], #4 ) 798 THUMB( str lr, [ip], #4 ) 799 ldr r4, [r2, #TI_TP_VALUE] 800 ldr r5, [r2, #TI_TP_VALUE + 4] 801#ifdef CONFIG_CPU_USE_DOMAINS 802 mrc p15, 0, r6, c3, c0, 0 @ Get domain register 803 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register 804 ldr r6, [r2, #TI_CPU_DOMAIN] 805#endif 806 switch_tls r1, r4, r5, r3, r7 807#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ 808 !defined(CONFIG_STACKPROTECTOR_PER_TASK) 809 ldr r8, =__stack_chk_guard 810 .if (TSK_STACK_CANARY > IMM12_MASK) 811 add r9, r2, #TSK_STACK_CANARY & ~IMM12_MASK 812 ldr r9, [r9, #TSK_STACK_CANARY & IMM12_MASK] 813 .else 814 ldr r9, [r2, #TSK_STACK_CANARY & IMM12_MASK] 815 .endif 816#endif 817 mov r7, r2 @ Preserve 'next' 818#ifdef CONFIG_CPU_USE_DOMAINS 819 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 820#endif 821 mov r5, r0 822 add r4, r2, #TI_CPU_SAVE 823 ldr r0, =thread_notify_head 824 mov r1, #THREAD_NOTIFY_SWITCH 825 bl atomic_notifier_call_chain 826#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ 827 !defined(CONFIG_STACKPROTECTOR_PER_TASK) 828 str r9, [r8] 829#endif 830 mov r0, r5 831#if !defined(CONFIG_THUMB2_KERNEL) && !defined(CONFIG_VMAP_STACK) 832 set_current r7, r8 833 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 834#else 835 mov r1, r7 836 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously 837#ifdef CONFIG_VMAP_STACK 838 @ 839 @ Do a dummy read from the new stack while running from the old one so 840 @ that we can rely on do_translation_fault() to fix up any stale PMD 841 @ entries covering the vmalloc region. 842 @ 843 ldr r2, [ip] 844#endif 845 846 @ When CONFIG_THREAD_INFO_IN_TASK=n, the update of SP itself is what 847 @ effectuates the task switch, as that is what causes the observable 848 @ values of current and current_thread_info to change. When 849 @ CONFIG_THREAD_INFO_IN_TASK=y, setting current (and therefore 850 @ current_thread_info) is done explicitly, and the update of SP just 851 @ switches us to another stack, with few other side effects. In order 852 @ to prevent this distinction from causing any inconsistencies, let's 853 @ keep the 'set_current' call as close as we can to the update of SP. 854 set_current r1, r2 855 mov sp, ip 856 ret lr 857#endif 858 UNWIND(.fnend ) 859ENDPROC(__switch_to) 860 861#ifdef CONFIG_VMAP_STACK 862 .text 863 .align 2 864__bad_stack: 865 @ 866 @ We've just detected an overflow. We need to load the address of this 867 @ CPU's overflow stack into the stack pointer register. We have only one 868 @ scratch register so let's use a sequence of ADDs including one 869 @ involving the PC, and decorate them with PC-relative group 870 @ relocations. As these are ARM only, switch to ARM mode first. 871 @ 872 @ We enter here with IP clobbered and its value stashed on the mode 873 @ stack. 874 @ 875THUMB( bx pc ) 876THUMB( nop ) 877THUMB( .arm ) 878 ldr_this_cpu_armv6 ip, overflow_stack_ptr 879 880 str sp, [ip, #-4]! @ Preserve original SP value 881 mov sp, ip @ Switch to overflow stack 882 pop {ip} @ Original SP in IP 883 884#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) 885 mov ip, ip @ mov expected by unwinder 886 push {fp, ip, lr, pc} @ GCC flavor frame record 887#else 888 str ip, [sp, #-8]! @ store original SP 889 push {fpreg, lr} @ Clang flavor frame record 890#endif 891UNWIND( ldr ip, [r0, #4] ) @ load exception LR 892UNWIND( str ip, [sp, #12] ) @ store in the frame record 893 ldr ip, [r0, #12] @ reload IP 894 895 @ Store the original GPRs to the new stack. 896 svc_entry uaccess=0, overflow_check=0 897 898UNWIND( .save {sp, pc} ) 899UNWIND( .save {fpreg, lr} ) 900UNWIND( .setfp fpreg, sp ) 901 902 ldr fpreg, [sp, #S_SP] @ Add our frame record 903 @ to the linked list 904#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) 905 ldr r1, [fp, #4] @ reload SP at entry 906 add fp, fp, #12 907#else 908 ldr r1, [fpreg, #8] 909#endif 910 str r1, [sp, #S_SP] @ store in pt_regs 911 912 @ Stash the regs for handle_bad_stack 913 mov r0, sp 914 915 @ Time to die 916 bl handle_bad_stack 917 nop 918UNWIND( .fnend ) 919ENDPROC(__bad_stack) 920#endif 921 922 __INIT 923 924/* 925 * User helpers. 926 * 927 * Each segment is 32-byte aligned and will be moved to the top of the high 928 * vector page. New segments (if ever needed) must be added in front of 929 * existing ones. This mechanism should be used only for things that are 930 * really small and justified, and not be abused freely. 931 * 932 * See Documentation/arm/kernel_user_helpers.rst for formal definitions. 933 */ 934 THUMB( .arm ) 935 936 .macro usr_ret, reg 937#ifdef CONFIG_ARM_THUMB 938 bx \reg 939#else 940 ret \reg 941#endif 942 .endm 943 944 .macro kuser_pad, sym, size 945 .if (. - \sym) & 3 946 .rept 4 - (. - \sym) & 3 947 .byte 0 948 .endr 949 .endif 950 .rept (\size - (. - \sym)) / 4 951 .word 0xe7fddef1 952 .endr 953 .endm 954 955#ifdef CONFIG_KUSER_HELPERS 956 .align 5 957 .globl __kuser_helper_start 958__kuser_helper_start: 959 960/* 961 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 962 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 963 */ 964 965__kuser_cmpxchg64: @ 0xffff0f60 966 967#if defined(CONFIG_CPU_32v6K) 968 969 stmfd sp!, {r4, r5, r6, r7} 970 ldrd r4, r5, [r0] @ load old val 971 ldrd r6, r7, [r1] @ load new val 972 smp_dmb arm 9731: ldrexd r0, r1, [r2] @ load current val 974 eors r3, r0, r4 @ compare with oldval (1) 975 eorseq r3, r1, r5 @ compare with oldval (2) 976 strexdeq r3, r6, r7, [r2] @ store newval if eq 977 teqeq r3, #1 @ success? 978 beq 1b @ if no then retry 979 smp_dmb arm 980 rsbs r0, r3, #0 @ set returned val and C flag 981 ldmfd sp!, {r4, r5, r6, r7} 982 usr_ret lr 983 984#elif !defined(CONFIG_SMP) 985 986#ifdef CONFIG_MMU 987 988 /* 989 * The only thing that can break atomicity in this cmpxchg64 990 * implementation is either an IRQ or a data abort exception 991 * causing another process/thread to be scheduled in the middle of 992 * the critical sequence. The same strategy as for cmpxchg is used. 993 */ 994 stmfd sp!, {r4, r5, r6, lr} 995 ldmia r0, {r4, r5} @ load old val 996 ldmia r1, {r6, lr} @ load new val 9971: ldmia r2, {r0, r1} @ load current val 998 eors r3, r0, r4 @ compare with oldval (1) 999 eorseq r3, r1, r5 @ compare with oldval (2) 10002: stmiaeq r2, {r6, lr} @ store newval if eq 1001 rsbs r0, r3, #0 @ set return val and C flag 1002 ldmfd sp!, {r4, r5, r6, pc} 1003 1004 .text 1005kuser_cmpxchg64_fixup: 1006 @ Called from kuser_cmpxchg_fixup. 1007 @ r4 = address of interrupted insn (must be preserved). 1008 @ sp = saved regs. r7 and r8 are clobbered. 1009 @ 1b = first critical insn, 2b = last critical insn. 1010 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 1011 mov r7, #0xffff0fff 1012 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 1013 subs r8, r4, r7 1014 rsbscs r8, r8, #(2b - 1b) 1015 strcs r7, [sp, #S_PC] 1016#if __LINUX_ARM_ARCH__ < 6 1017 bcc kuser_cmpxchg32_fixup 1018#endif 1019 ret lr 1020 .previous 1021 1022#else 1023#warning "NPTL on non MMU needs fixing" 1024 mov r0, #-1 1025 adds r0, r0, #0 1026 usr_ret lr 1027#endif 1028 1029#else 1030#error "incoherent kernel configuration" 1031#endif 1032 1033 kuser_pad __kuser_cmpxchg64, 64 1034 1035__kuser_memory_barrier: @ 0xffff0fa0 1036 smp_dmb arm 1037 usr_ret lr 1038 1039 kuser_pad __kuser_memory_barrier, 32 1040 1041__kuser_cmpxchg: @ 0xffff0fc0 1042 1043#if __LINUX_ARM_ARCH__ < 6 1044 1045#ifdef CONFIG_MMU 1046 1047 /* 1048 * The only thing that can break atomicity in this cmpxchg 1049 * implementation is either an IRQ or a data abort exception 1050 * causing another process/thread to be scheduled in the middle 1051 * of the critical sequence. To prevent this, code is added to 1052 * the IRQ and data abort exception handlers to set the pc back 1053 * to the beginning of the critical section if it is found to be 1054 * within that critical section (see kuser_cmpxchg_fixup). 1055 */ 10561: ldr r3, [r2] @ load current val 1057 subs r3, r3, r0 @ compare with oldval 10582: streq r1, [r2] @ store newval if eq 1059 rsbs r0, r3, #0 @ set return val and C flag 1060 usr_ret lr 1061 1062 .text 1063kuser_cmpxchg32_fixup: 1064 @ Called from kuser_cmpxchg_check macro. 1065 @ r4 = address of interrupted insn (must be preserved). 1066 @ sp = saved regs. r7 and r8 are clobbered. 1067 @ 1b = first critical insn, 2b = last critical insn. 1068 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 1069 mov r7, #0xffff0fff 1070 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 1071 subs r8, r4, r7 1072 rsbscs r8, r8, #(2b - 1b) 1073 strcs r7, [sp, #S_PC] 1074 ret lr 1075 .previous 1076 1077#else 1078#warning "NPTL on non MMU needs fixing" 1079 mov r0, #-1 1080 adds r0, r0, #0 1081 usr_ret lr 1082#endif 1083 1084#else 1085 1086 smp_dmb arm 10871: ldrex r3, [r2] 1088 subs r3, r3, r0 1089 strexeq r3, r1, [r2] 1090 teqeq r3, #1 1091 beq 1b 1092 rsbs r0, r3, #0 1093 /* beware -- each __kuser slot must be 8 instructions max */ 1094 ALT_SMP(b __kuser_memory_barrier) 1095 ALT_UP(usr_ret lr) 1096 1097#endif 1098 1099 kuser_pad __kuser_cmpxchg, 32 1100 1101__kuser_get_tls: @ 0xffff0fe0 1102 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1103 usr_ret lr 1104 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1105 kuser_pad __kuser_get_tls, 16 1106 .rep 3 1107 .word 0 @ 0xffff0ff0 software TLS value, then 1108 .endr @ pad up to __kuser_helper_version 1109 1110__kuser_helper_version: @ 0xffff0ffc 1111 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1112 1113 .globl __kuser_helper_end 1114__kuser_helper_end: 1115 1116#endif 1117 1118 THUMB( .thumb ) 1119 1120/* 1121 * Vector stubs. 1122 * 1123 * This code is copied to 0xffff1000 so we can use branches in the 1124 * vectors, rather than ldr's. Note that this code must not exceed 1125 * a page size. 1126 * 1127 * Common stub entry macro: 1128 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1129 * 1130 * SP points to a minimal amount of processor-private memory, the address 1131 * of which is copied into r0 for the mode specific abort handler. 1132 */ 1133 .macro vector_stub, name, mode, correction=0 1134 .align 5 1135 1136vector_\name: 1137 .if \correction 1138 sub lr, lr, #\correction 1139 .endif 1140 1141 @ 1142 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1143 @ (parent CPSR) 1144 @ 1145 stmia sp, {r0, lr} @ save r0, lr 1146 mrs lr, spsr 1147 str lr, [sp, #8] @ save spsr 1148 1149 @ 1150 @ Prepare for SVC32 mode. IRQs remain disabled. 1151 @ 1152 mrs r0, cpsr 1153 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1154 msr spsr_cxsf, r0 1155 1156 @ 1157 @ the branch table must immediately follow this code 1158 @ 1159 and lr, lr, #0x0f 1160 THUMB( adr r0, 1f ) 1161 THUMB( ldr lr, [r0, lr, lsl #2] ) 1162 mov r0, sp 1163 ARM( ldr lr, [pc, lr, lsl #2] ) 1164 movs pc, lr @ branch to handler in SVC mode 1165ENDPROC(vector_\name) 1166 1167 .align 2 1168 @ handler addresses follow this label 11691: 1170 .endm 1171 1172 .section .stubs, "ax", %progbits 1173 @ This must be the first word 1174 .word vector_swi 1175 1176vector_rst: 1177 ARM( swi SYS_ERROR0 ) 1178 THUMB( svc #0 ) 1179 THUMB( nop ) 1180 b vector_und 1181 1182/* 1183 * Interrupt dispatcher 1184 */ 1185 vector_stub irq, IRQ_MODE, 4 1186 1187 .long __irq_usr @ 0 (USR_26 / USR_32) 1188 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1189 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1190 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1191 .long __irq_invalid @ 4 1192 .long __irq_invalid @ 5 1193 .long __irq_invalid @ 6 1194 .long __irq_invalid @ 7 1195 .long __irq_invalid @ 8 1196 .long __irq_invalid @ 9 1197 .long __irq_invalid @ a 1198 .long __irq_invalid @ b 1199 .long __irq_invalid @ c 1200 .long __irq_invalid @ d 1201 .long __irq_invalid @ e 1202 .long __irq_invalid @ f 1203 1204/* 1205 * Data abort dispatcher 1206 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1207 */ 1208 vector_stub dabt, ABT_MODE, 8 1209 1210 .long __dabt_usr @ 0 (USR_26 / USR_32) 1211 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1212 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1213 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1214 .long __dabt_invalid @ 4 1215 .long __dabt_invalid @ 5 1216 .long __dabt_invalid @ 6 1217 .long __dabt_invalid @ 7 1218 .long __dabt_invalid @ 8 1219 .long __dabt_invalid @ 9 1220 .long __dabt_invalid @ a 1221 .long __dabt_invalid @ b 1222 .long __dabt_invalid @ c 1223 .long __dabt_invalid @ d 1224 .long __dabt_invalid @ e 1225 .long __dabt_invalid @ f 1226 1227/* 1228 * Prefetch abort dispatcher 1229 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1230 */ 1231 vector_stub pabt, ABT_MODE, 4 1232 1233 .long __pabt_usr @ 0 (USR_26 / USR_32) 1234 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1235 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1236 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1237 .long __pabt_invalid @ 4 1238 .long __pabt_invalid @ 5 1239 .long __pabt_invalid @ 6 1240 .long __pabt_invalid @ 7 1241 .long __pabt_invalid @ 8 1242 .long __pabt_invalid @ 9 1243 .long __pabt_invalid @ a 1244 .long __pabt_invalid @ b 1245 .long __pabt_invalid @ c 1246 .long __pabt_invalid @ d 1247 .long __pabt_invalid @ e 1248 .long __pabt_invalid @ f 1249 1250/* 1251 * Undef instr entry dispatcher 1252 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1253 */ 1254 vector_stub und, UND_MODE 1255 1256 .long __und_usr @ 0 (USR_26 / USR_32) 1257 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1258 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1259 .long __und_svc @ 3 (SVC_26 / SVC_32) 1260 .long __und_invalid @ 4 1261 .long __und_invalid @ 5 1262 .long __und_invalid @ 6 1263 .long __und_invalid @ 7 1264 .long __und_invalid @ 8 1265 .long __und_invalid @ 9 1266 .long __und_invalid @ a 1267 .long __und_invalid @ b 1268 .long __und_invalid @ c 1269 .long __und_invalid @ d 1270 .long __und_invalid @ e 1271 .long __und_invalid @ f 1272 1273 .align 5 1274 1275/*============================================================================= 1276 * Address exception handler 1277 *----------------------------------------------------------------------------- 1278 * These aren't too critical. 1279 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1280 */ 1281 1282vector_addrexcptn: 1283 b vector_addrexcptn 1284 1285/*============================================================================= 1286 * FIQ "NMI" handler 1287 *----------------------------------------------------------------------------- 1288 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 1289 * systems. 1290 */ 1291 vector_stub fiq, FIQ_MODE, 4 1292 1293 .long __fiq_usr @ 0 (USR_26 / USR_32) 1294 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) 1295 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) 1296 .long __fiq_svc @ 3 (SVC_26 / SVC_32) 1297 .long __fiq_svc @ 4 1298 .long __fiq_svc @ 5 1299 .long __fiq_svc @ 6 1300 .long __fiq_abt @ 7 1301 .long __fiq_svc @ 8 1302 .long __fiq_svc @ 9 1303 .long __fiq_svc @ a 1304 .long __fiq_svc @ b 1305 .long __fiq_svc @ c 1306 .long __fiq_svc @ d 1307 .long __fiq_svc @ e 1308 .long __fiq_svc @ f 1309 1310 .globl vector_fiq 1311 1312 .section .vectors, "ax", %progbits 1313.L__vectors_start: 1314 W(b) vector_rst 1315 W(b) vector_und 1316 W(ldr) pc, .L__vectors_start + 0x1000 1317 W(b) vector_pabt 1318 W(b) vector_dabt 1319 W(b) vector_addrexcptn 1320 W(b) vector_irq 1321 W(b) vector_fiq 1322 1323 .data 1324 .align 2 1325 1326 .globl cr_alignment 1327cr_alignment: 1328 .space 4 1329