1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <mach/entry-macro.S> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24 25#include "entry-header.S" 26 27/* 28 * Interrupt handling. Preserves r7, r8, r9 29 */ 30 .macro irq_handler 31 get_irqnr_preamble r5, lr 321: get_irqnr_and_base r0, r6, r5, lr 33 movne r1, sp 34 @ 35 @ routine called with r0 = irq number, r1 = struct pt_regs * 36 @ 37 adrne lr, 1b 38 bne asm_do_IRQ 39 40#ifdef CONFIG_SMP 41 /* 42 * XXX 43 * 44 * this macro assumes that irqstat (r6) and base (r5) are 45 * preserved from get_irqnr_and_base above 46 */ 47 test_for_ipi r0, r6, r5, lr 48 movne r0, sp 49 adrne lr, 1b 50 bne do_IPI 51 52#ifdef CONFIG_LOCAL_TIMERS 53 test_for_ltirq r0, r6, r5, lr 54 movne r0, sp 55 adrne lr, 1b 56 bne do_local_timer 57#endif 58#endif 59 60 .endm 61 62#ifdef CONFIG_KPROBES 63 .section .kprobes.text,"ax",%progbits 64#else 65 .text 66#endif 67 68/* 69 * Invalid mode handlers 70 */ 71 .macro inv_entry, reason 72 sub sp, sp, #S_FRAME_SIZE 73 stmib sp, {r1 - lr} 74 mov r1, #\reason 75 .endm 76 77__pabt_invalid: 78 inv_entry BAD_PREFETCH 79 b common_invalid 80ENDPROC(__pabt_invalid) 81 82__dabt_invalid: 83 inv_entry BAD_DATA 84 b common_invalid 85ENDPROC(__dabt_invalid) 86 87__irq_invalid: 88 inv_entry BAD_IRQ 89 b common_invalid 90ENDPROC(__irq_invalid) 91 92__und_invalid: 93 inv_entry BAD_UNDEFINSTR 94 95 @ 96 @ XXX fall through to common_invalid 97 @ 98 99@ 100@ common_invalid - generic code for failed exception (re-entrant version of handlers) 101@ 102common_invalid: 103 zero_fp 104 105 ldmia r0, {r4 - r6} 106 add r0, sp, #S_PC @ here for interlock avoidance 107 mov r7, #-1 @ "" "" "" "" 108 str r4, [sp] @ save preserved r0 109 stmia r0, {r5 - r7} @ lr_<exception>, 110 @ cpsr_<exception>, "old_r0" 111 112 mov r0, sp 113 b bad_mode 114ENDPROC(__und_invalid) 115 116/* 117 * SVC mode handlers 118 */ 119 120#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 121#define SPFIX(code...) code 122#else 123#define SPFIX(code...) 124#endif 125 126 .macro svc_entry, stack_hole=0 127 UNWIND(.fnstart ) 128 UNWIND(.save {r0 - pc} ) 129 sub sp, sp, #(S_FRAME_SIZE + \stack_hole) 130 SPFIX( tst sp, #4 ) 131 SPFIX( bicne sp, sp, #4 ) 132 stmib sp, {r1 - r12} 133 134 ldmia r0, {r1 - r3} 135 add r5, sp, #S_SP @ here for interlock avoidance 136 mov r4, #-1 @ "" "" "" "" 137 add r0, sp, #(S_FRAME_SIZE + \stack_hole) 138 SPFIX( addne r0, r0, #4 ) 139 str r1, [sp] @ save the "real" r0 copied 140 @ from the exception stack 141 142 mov r1, lr 143 144 @ 145 @ We are now ready to fill in the remaining blanks on the stack: 146 @ 147 @ r0 - sp_svc 148 @ r1 - lr_svc 149 @ r2 - lr_<exception>, already fixed up for correct return/restart 150 @ r3 - spsr_<exception> 151 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 152 @ 153 stmia r5, {r0 - r4} 154 .endm 155 156 .align 5 157__dabt_svc: 158 svc_entry 159 160 @ 161 @ get ready to re-enable interrupts if appropriate 162 @ 163 mrs r9, cpsr 164 tst r3, #PSR_I_BIT 165 biceq r9, r9, #PSR_I_BIT 166 167 @ 168 @ Call the processor-specific abort handler: 169 @ 170 @ r2 - aborted context pc 171 @ r3 - aborted context cpsr 172 @ 173 @ The abort handler must return the aborted address in r0, and 174 @ the fault status register in r1. r9 must be preserved. 175 @ 176#ifdef MULTI_DABORT 177 ldr r4, .LCprocfns 178 mov lr, pc 179 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 180#else 181 bl CPU_DABORT_HANDLER 182#endif 183 184 @ 185 @ set desired IRQ state, then call main handler 186 @ 187 msr cpsr_c, r9 188 mov r2, sp 189 bl do_DataAbort 190 191 @ 192 @ IRQs off again before pulling preserved data off the stack 193 @ 194 disable_irq 195 196 @ 197 @ restore SPSR and restart the instruction 198 @ 199 ldr r0, [sp, #S_PSR] 200 msr spsr_cxsf, r0 201 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 202 UNWIND(.fnend ) 203ENDPROC(__dabt_svc) 204 205 .align 5 206__irq_svc: 207 svc_entry 208 209#ifdef CONFIG_TRACE_IRQFLAGS 210 bl trace_hardirqs_off 211#endif 212#ifdef CONFIG_PREEMPT 213 get_thread_info tsk 214 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 215 add r7, r8, #1 @ increment it 216 str r7, [tsk, #TI_PREEMPT] 217#endif 218 219 irq_handler 220#ifdef CONFIG_PREEMPT 221 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 222 ldr r0, [tsk, #TI_FLAGS] @ get flags 223 teq r8, #0 @ if preempt count != 0 224 movne r0, #0 @ force flags to 0 225 tst r0, #_TIF_NEED_RESCHED 226 blne svc_preempt 227#endif 228 ldr r0, [sp, #S_PSR] @ irqs are already disabled 229 msr spsr_cxsf, r0 230#ifdef CONFIG_TRACE_IRQFLAGS 231 tst r0, #PSR_I_BIT 232 bleq trace_hardirqs_on 233#endif 234 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 235 UNWIND(.fnend ) 236ENDPROC(__irq_svc) 237 238 .ltorg 239 240#ifdef CONFIG_PREEMPT 241svc_preempt: 242 mov r8, lr 2431: bl preempt_schedule_irq @ irq en/disable is done inside 244 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 245 tst r0, #_TIF_NEED_RESCHED 246 moveq pc, r8 @ go again 247 b 1b 248#endif 249 250 .align 5 251__und_svc: 252#ifdef CONFIG_KPROBES 253 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 254 @ it obviously needs free stack space which then will belong to 255 @ the saved context. 256 svc_entry 64 257#else 258 svc_entry 259#endif 260 261 @ 262 @ call emulation code, which returns using r9 if it has emulated 263 @ the instruction, or the more conventional lr if we are to treat 264 @ this as a real undefined instruction 265 @ 266 @ r0 - instruction 267 @ 268 ldr r0, [r2, #-4] 269 adr r9, 1f 270 bl call_fpe 271 272 mov r0, sp @ struct pt_regs *regs 273 bl do_undefinstr 274 275 @ 276 @ IRQs off again before pulling preserved data off the stack 277 @ 2781: disable_irq 279 280 @ 281 @ restore SPSR and restart the instruction 282 @ 283 ldr lr, [sp, #S_PSR] @ Get SVC cpsr 284 msr spsr_cxsf, lr 285 ldmia sp, {r0 - pc}^ @ Restore SVC registers 286 UNWIND(.fnend ) 287ENDPROC(__und_svc) 288 289 .align 5 290__pabt_svc: 291 svc_entry 292 293 @ 294 @ re-enable interrupts if appropriate 295 @ 296 mrs r9, cpsr 297 tst r3, #PSR_I_BIT 298 biceq r9, r9, #PSR_I_BIT 299 300 @ 301 @ set args, then call main handler 302 @ 303 @ r0 - address of faulting instruction 304 @ r1 - pointer to registers on stack 305 @ 306#ifdef MULTI_PABORT 307 mov r0, r2 @ pass address of aborted instruction. 308 ldr r4, .LCprocfns 309 mov lr, pc 310 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 311#else 312 CPU_PABORT_HANDLER(r0, r2) 313#endif 314 msr cpsr_c, r9 @ Maybe enable interrupts 315 mov r1, sp @ regs 316 bl do_PrefetchAbort @ call abort handler 317 318 @ 319 @ IRQs off again before pulling preserved data off the stack 320 @ 321 disable_irq 322 323 @ 324 @ restore SPSR and restart the instruction 325 @ 326 ldr r0, [sp, #S_PSR] 327 msr spsr_cxsf, r0 328 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 329 UNWIND(.fnend ) 330ENDPROC(__pabt_svc) 331 332 .align 5 333.LCcralign: 334 .word cr_alignment 335#ifdef MULTI_DABORT 336.LCprocfns: 337 .word processor 338#endif 339.LCfp: 340 .word fp_enter 341 342/* 343 * User mode handlers 344 * 345 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 346 */ 347 348#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 349#error "sizeof(struct pt_regs) must be a multiple of 8" 350#endif 351 352 .macro usr_entry 353 UNWIND(.fnstart ) 354 UNWIND(.cantunwind ) @ don't unwind the user space 355 sub sp, sp, #S_FRAME_SIZE 356 stmib sp, {r1 - r12} 357 358 ldmia r0, {r1 - r3} 359 add r0, sp, #S_PC @ here for interlock avoidance 360 mov r4, #-1 @ "" "" "" "" 361 362 str r1, [sp] @ save the "real" r0 copied 363 @ from the exception stack 364 365 @ 366 @ We are now ready to fill in the remaining blanks on the stack: 367 @ 368 @ r2 - lr_<exception>, already fixed up for correct return/restart 369 @ r3 - spsr_<exception> 370 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 371 @ 372 @ Also, separately save sp_usr and lr_usr 373 @ 374 stmia r0, {r2 - r4} 375 stmdb r0, {sp, lr}^ 376 377 @ 378 @ Enable the alignment trap while in kernel mode 379 @ 380 alignment_trap r0 381 382 @ 383 @ Clear FP to mark the first stack frame 384 @ 385 zero_fp 386 .endm 387 388 .macro kuser_cmpxchg_check 389#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 390#ifndef CONFIG_MMU 391#warning "NPTL on non MMU needs fixing" 392#else 393 @ Make sure our user space atomic helper is restarted 394 @ if it was interrupted in a critical region. Here we 395 @ perform a quick test inline since it should be false 396 @ 99.9999% of the time. The rest is done out of line. 397 cmp r2, #TASK_SIZE 398 blhs kuser_cmpxchg_fixup 399#endif 400#endif 401 .endm 402 403 .align 5 404__dabt_usr: 405 usr_entry 406 kuser_cmpxchg_check 407 408 @ 409 @ Call the processor-specific abort handler: 410 @ 411 @ r2 - aborted context pc 412 @ r3 - aborted context cpsr 413 @ 414 @ The abort handler must return the aborted address in r0, and 415 @ the fault status register in r1. 416 @ 417#ifdef MULTI_DABORT 418 ldr r4, .LCprocfns 419 mov lr, pc 420 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 421#else 422 bl CPU_DABORT_HANDLER 423#endif 424 425 @ 426 @ IRQs on, then call the main handler 427 @ 428 enable_irq 429 mov r2, sp 430 adr lr, ret_from_exception 431 b do_DataAbort 432 UNWIND(.fnend ) 433ENDPROC(__dabt_usr) 434 435 .align 5 436__irq_usr: 437 usr_entry 438 kuser_cmpxchg_check 439 440#ifdef CONFIG_TRACE_IRQFLAGS 441 bl trace_hardirqs_off 442#endif 443 get_thread_info tsk 444#ifdef CONFIG_PREEMPT 445 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 446 add r7, r8, #1 @ increment it 447 str r7, [tsk, #TI_PREEMPT] 448#endif 449 450 irq_handler 451#ifdef CONFIG_PREEMPT 452 ldr r0, [tsk, #TI_PREEMPT] 453 str r8, [tsk, #TI_PREEMPT] 454 teq r0, r7 455 strne r0, [r0, -r0] 456#endif 457#ifdef CONFIG_TRACE_IRQFLAGS 458 bl trace_hardirqs_on 459#endif 460 461 mov why, #0 462 b ret_to_user 463 UNWIND(.fnend ) 464ENDPROC(__irq_usr) 465 466 .ltorg 467 468 .align 5 469__und_usr: 470 usr_entry 471 472 @ 473 @ fall through to the emulation code, which returns using r9 if 474 @ it has emulated the instruction, or the more conventional lr 475 @ if we are to treat this as a real undefined instruction 476 @ 477 @ r0 - instruction 478 @ 479 adr r9, ret_from_exception 480 adr lr, __und_usr_unknown 481 tst r3, #PSR_T_BIT @ Thumb mode? 482 subeq r4, r2, #4 @ ARM instr at LR - 4 483 subne r4, r2, #2 @ Thumb instr at LR - 2 4841: ldreqt r0, [r4] 485 beq call_fpe 486 @ Thumb instruction 487#if __LINUX_ARM_ARCH__ >= 7 4882: ldrht r5, [r4], #2 489 and r0, r5, #0xf800 @ mask bits 111x x... .... .... 490 cmp r0, #0xe800 @ 32bit instruction if xx != 0 491 blo __und_usr_unknown 4923: ldrht r0, [r4] 493 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 494 orr r0, r0, r5, lsl #16 495#else 496 b __und_usr_unknown 497#endif 498 UNWIND(.fnend ) 499ENDPROC(__und_usr) 500 501 @ 502 @ fallthrough to call_fpe 503 @ 504 505/* 506 * The out of line fixup for the ldrt above. 507 */ 508 .section .fixup, "ax" 5094: mov pc, r9 510 .previous 511 .section __ex_table,"a" 512 .long 1b, 4b 513#if __LINUX_ARM_ARCH__ >= 7 514 .long 2b, 4b 515 .long 3b, 4b 516#endif 517 .previous 518 519/* 520 * Check whether the instruction is a co-processor instruction. 521 * If yes, we need to call the relevant co-processor handler. 522 * 523 * Note that we don't do a full check here for the co-processor 524 * instructions; all instructions with bit 27 set are well 525 * defined. The only instructions that should fault are the 526 * co-processor instructions. However, we have to watch out 527 * for the ARM6/ARM7 SWI bug. 528 * 529 * NEON is a special case that has to be handled here. Not all 530 * NEON instructions are co-processor instructions, so we have 531 * to make a special case of checking for them. Plus, there's 532 * five groups of them, so we have a table of mask/opcode pairs 533 * to check against, and if any match then we branch off into the 534 * NEON handler code. 535 * 536 * Emulators may wish to make use of the following registers: 537 * r0 = instruction opcode. 538 * r2 = PC+4 539 * r9 = normal "successful" return address 540 * r10 = this threads thread_info structure. 541 * lr = unrecognised instruction return address 542 */ 543 @ 544 @ Fall-through from Thumb-2 __und_usr 545 @ 546#ifdef CONFIG_NEON 547 adr r6, .LCneon_thumb_opcodes 548 b 2f 549#endif 550call_fpe: 551#ifdef CONFIG_NEON 552 adr r6, .LCneon_arm_opcodes 5532: 554 ldr r7, [r6], #4 @ mask value 555 cmp r7, #0 @ end mask? 556 beq 1f 557 and r8, r0, r7 558 ldr r7, [r6], #4 @ opcode bits matching in mask 559 cmp r8, r7 @ NEON instruction? 560 bne 2b 561 get_thread_info r10 562 mov r7, #1 563 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 564 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 565 b do_vfp @ let VFP handler handle this 5661: 567#endif 568 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 569 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 570#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 571 and r8, r0, #0x0f000000 @ mask out op-code bits 572 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 573#endif 574 moveq pc, lr 575 get_thread_info r10 @ get current thread 576 and r8, r0, #0x00000f00 @ mask out CP number 577 mov r7, #1 578 add r6, r10, #TI_USED_CP 579 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] 580#ifdef CONFIG_IWMMXT 581 @ Test if we need to give access to iWMMXt coprocessors 582 ldr r5, [r10, #TI_FLAGS] 583 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 584 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 585 bcs iwmmxt_task_enable 586#endif 587 add pc, pc, r8, lsr #6 588 mov r0, r0 589 590 mov pc, lr @ CP#0 591 b do_fpe @ CP#1 (FPE) 592 b do_fpe @ CP#2 (FPE) 593 mov pc, lr @ CP#3 594#ifdef CONFIG_CRUNCH 595 b crunch_task_enable @ CP#4 (MaverickCrunch) 596 b crunch_task_enable @ CP#5 (MaverickCrunch) 597 b crunch_task_enable @ CP#6 (MaverickCrunch) 598#else 599 mov pc, lr @ CP#4 600 mov pc, lr @ CP#5 601 mov pc, lr @ CP#6 602#endif 603 mov pc, lr @ CP#7 604 mov pc, lr @ CP#8 605 mov pc, lr @ CP#9 606#ifdef CONFIG_VFP 607 b do_vfp @ CP#10 (VFP) 608 b do_vfp @ CP#11 (VFP) 609#else 610 mov pc, lr @ CP#10 (VFP) 611 mov pc, lr @ CP#11 (VFP) 612#endif 613 mov pc, lr @ CP#12 614 mov pc, lr @ CP#13 615 mov pc, lr @ CP#14 (Debug) 616 mov pc, lr @ CP#15 (Control) 617 618#ifdef CONFIG_NEON 619 .align 6 620 621.LCneon_arm_opcodes: 622 .word 0xfe000000 @ mask 623 .word 0xf2000000 @ opcode 624 625 .word 0xff100000 @ mask 626 .word 0xf4000000 @ opcode 627 628 .word 0x00000000 @ mask 629 .word 0x00000000 @ opcode 630 631.LCneon_thumb_opcodes: 632 .word 0xef000000 @ mask 633 .word 0xef000000 @ opcode 634 635 .word 0xff100000 @ mask 636 .word 0xf9000000 @ opcode 637 638 .word 0x00000000 @ mask 639 .word 0x00000000 @ opcode 640#endif 641 642do_fpe: 643 enable_irq 644 ldr r4, .LCfp 645 add r10, r10, #TI_FPSTATE @ r10 = workspace 646 ldr pc, [r4] @ Call FP module USR entry point 647 648/* 649 * The FP module is called with these registers set: 650 * r0 = instruction 651 * r2 = PC+4 652 * r9 = normal "successful" return address 653 * r10 = FP workspace 654 * lr = unrecognised FP instruction return address 655 */ 656 657 .data 658ENTRY(fp_enter) 659 .word no_fp 660 .previous 661 662no_fp: mov pc, lr 663 664__und_usr_unknown: 665 enable_irq 666 mov r0, sp 667 adr lr, ret_from_exception 668 b do_undefinstr 669ENDPROC(__und_usr_unknown) 670 671 .align 5 672__pabt_usr: 673 usr_entry 674 675#ifdef MULTI_PABORT 676 mov r0, r2 @ pass address of aborted instruction. 677 ldr r4, .LCprocfns 678 mov lr, pc 679 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 680#else 681 CPU_PABORT_HANDLER(r0, r2) 682#endif 683 enable_irq @ Enable interrupts 684 mov r1, sp @ regs 685 bl do_PrefetchAbort @ call abort handler 686 UNWIND(.fnend ) 687 /* fall through */ 688/* 689 * This is the return code to user mode for abort handlers 690 */ 691ENTRY(ret_from_exception) 692 UNWIND(.fnstart ) 693 UNWIND(.cantunwind ) 694 get_thread_info tsk 695 mov why, #0 696 b ret_to_user 697 UNWIND(.fnend ) 698ENDPROC(__pabt_usr) 699ENDPROC(ret_from_exception) 700 701/* 702 * Register switch for ARMv3 and ARMv4 processors 703 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 704 * previous and next are guaranteed not to be the same. 705 */ 706ENTRY(__switch_to) 707 UNWIND(.fnstart ) 708 UNWIND(.cantunwind ) 709 add ip, r1, #TI_CPU_SAVE 710 ldr r3, [r2, #TI_TP_VALUE] 711 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack 712#ifdef CONFIG_MMU 713 ldr r6, [r2, #TI_CPU_DOMAIN] 714#endif 715#if __LINUX_ARM_ARCH__ >= 6 716#ifdef CONFIG_CPU_32v6K 717 clrex 718#else 719 strex r5, r4, [ip] @ Clear exclusive monitor 720#endif 721#endif 722#if defined(CONFIG_HAS_TLS_REG) 723 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 724#elif !defined(CONFIG_TLS_REG_EMUL) 725 mov r4, #0xffff0fff 726 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 727#endif 728#ifdef CONFIG_MMU 729 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 730#endif 731 mov r5, r0 732 add r4, r2, #TI_CPU_SAVE 733 ldr r0, =thread_notify_head 734 mov r1, #THREAD_NOTIFY_SWITCH 735 bl atomic_notifier_call_chain 736 mov r0, r5 737 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 738 UNWIND(.fnend ) 739ENDPROC(__switch_to) 740 741 __INIT 742 743/* 744 * User helpers. 745 * 746 * These are segment of kernel provided user code reachable from user space 747 * at a fixed address in kernel memory. This is used to provide user space 748 * with some operations which require kernel help because of unimplemented 749 * native feature and/or instructions in many ARM CPUs. The idea is for 750 * this code to be executed directly in user mode for best efficiency but 751 * which is too intimate with the kernel counter part to be left to user 752 * libraries. In fact this code might even differ from one CPU to another 753 * depending on the available instruction set and restrictions like on 754 * SMP systems. In other words, the kernel reserves the right to change 755 * this code as needed without warning. Only the entry points and their 756 * results are guaranteed to be stable. 757 * 758 * Each segment is 32-byte aligned and will be moved to the top of the high 759 * vector page. New segments (if ever needed) must be added in front of 760 * existing ones. This mechanism should be used only for things that are 761 * really small and justified, and not be abused freely. 762 * 763 * User space is expected to implement those things inline when optimizing 764 * for a processor that has the necessary native support, but only if such 765 * resulting binaries are already to be incompatible with earlier ARM 766 * processors due to the use of unsupported instructions other than what 767 * is provided here. In other words don't make binaries unable to run on 768 * earlier processors just for the sake of not using these kernel helpers 769 * if your compiled code is not going to use the new instructions for other 770 * purpose. 771 */ 772 773 .macro usr_ret, reg 774#ifdef CONFIG_ARM_THUMB 775 bx \reg 776#else 777 mov pc, \reg 778#endif 779 .endm 780 781 .align 5 782 .globl __kuser_helper_start 783__kuser_helper_start: 784 785/* 786 * Reference prototype: 787 * 788 * void __kernel_memory_barrier(void) 789 * 790 * Input: 791 * 792 * lr = return address 793 * 794 * Output: 795 * 796 * none 797 * 798 * Clobbered: 799 * 800 * none 801 * 802 * Definition and user space usage example: 803 * 804 * typedef void (__kernel_dmb_t)(void); 805 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 806 * 807 * Apply any needed memory barrier to preserve consistency with data modified 808 * manually and __kuser_cmpxchg usage. 809 * 810 * This could be used as follows: 811 * 812 * #define __kernel_dmb() \ 813 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 814 * : : : "r0", "lr","cc" ) 815 */ 816 817__kuser_memory_barrier: @ 0xffff0fa0 818 smp_dmb 819 usr_ret lr 820 821 .align 5 822 823/* 824 * Reference prototype: 825 * 826 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 827 * 828 * Input: 829 * 830 * r0 = oldval 831 * r1 = newval 832 * r2 = ptr 833 * lr = return address 834 * 835 * Output: 836 * 837 * r0 = returned value (zero or non-zero) 838 * C flag = set if r0 == 0, clear if r0 != 0 839 * 840 * Clobbered: 841 * 842 * r3, ip, flags 843 * 844 * Definition and user space usage example: 845 * 846 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 847 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 848 * 849 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 850 * Return zero if *ptr was changed or non-zero if no exchange happened. 851 * The C flag is also set if *ptr was changed to allow for assembly 852 * optimization in the calling code. 853 * 854 * Notes: 855 * 856 * - This routine already includes memory barriers as needed. 857 * 858 * For example, a user space atomic_add implementation could look like this: 859 * 860 * #define atomic_add(ptr, val) \ 861 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 862 * register unsigned int __result asm("r1"); \ 863 * asm volatile ( \ 864 * "1: @ atomic_add\n\t" \ 865 * "ldr r0, [r2]\n\t" \ 866 * "mov r3, #0xffff0fff\n\t" \ 867 * "add lr, pc, #4\n\t" \ 868 * "add r1, r0, %2\n\t" \ 869 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 870 * "bcc 1b" \ 871 * : "=&r" (__result) \ 872 * : "r" (__ptr), "rIL" (val) \ 873 * : "r0","r3","ip","lr","cc","memory" ); \ 874 * __result; }) 875 */ 876 877__kuser_cmpxchg: @ 0xffff0fc0 878 879#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 880 881 /* 882 * Poor you. No fast solution possible... 883 * The kernel itself must perform the operation. 884 * A special ghost syscall is used for that (see traps.c). 885 */ 886 stmfd sp!, {r7, lr} 887 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 888 orr r7, r7, #0xf0 889 swi #0x9ffff0 890 ldmfd sp!, {r7, pc} 891 892#elif __LINUX_ARM_ARCH__ < 6 893 894#ifdef CONFIG_MMU 895 896 /* 897 * The only thing that can break atomicity in this cmpxchg 898 * implementation is either an IRQ or a data abort exception 899 * causing another process/thread to be scheduled in the middle 900 * of the critical sequence. To prevent this, code is added to 901 * the IRQ and data abort exception handlers to set the pc back 902 * to the beginning of the critical section if it is found to be 903 * within that critical section (see kuser_cmpxchg_fixup). 904 */ 9051: ldr r3, [r2] @ load current val 906 subs r3, r3, r0 @ compare with oldval 9072: streq r1, [r2] @ store newval if eq 908 rsbs r0, r3, #0 @ set return val and C flag 909 usr_ret lr 910 911 .text 912kuser_cmpxchg_fixup: 913 @ Called from kuser_cmpxchg_check macro. 914 @ r2 = address of interrupted insn (must be preserved). 915 @ sp = saved regs. r7 and r8 are clobbered. 916 @ 1b = first critical insn, 2b = last critical insn. 917 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. 918 mov r7, #0xffff0fff 919 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 920 subs r8, r2, r7 921 rsbcss r8, r8, #(2b - 1b) 922 strcs r7, [sp, #S_PC] 923 mov pc, lr 924 .previous 925 926#else 927#warning "NPTL on non MMU needs fixing" 928 mov r0, #-1 929 adds r0, r0, #0 930 usr_ret lr 931#endif 932 933#else 934 935#ifdef CONFIG_SMP 936 mcr p15, 0, r0, c7, c10, 5 @ dmb 937#endif 9381: ldrex r3, [r2] 939 subs r3, r3, r0 940 strexeq r3, r1, [r2] 941 teqeq r3, #1 942 beq 1b 943 rsbs r0, r3, #0 944 /* beware -- each __kuser slot must be 8 instructions max */ 945#ifdef CONFIG_SMP 946 b __kuser_memory_barrier 947#else 948 usr_ret lr 949#endif 950 951#endif 952 953 .align 5 954 955/* 956 * Reference prototype: 957 * 958 * int __kernel_get_tls(void) 959 * 960 * Input: 961 * 962 * lr = return address 963 * 964 * Output: 965 * 966 * r0 = TLS value 967 * 968 * Clobbered: 969 * 970 * none 971 * 972 * Definition and user space usage example: 973 * 974 * typedef int (__kernel_get_tls_t)(void); 975 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 976 * 977 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 978 * 979 * This could be used as follows: 980 * 981 * #define __kernel_get_tls() \ 982 * ({ register unsigned int __val asm("r0"); \ 983 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 984 * : "=r" (__val) : : "lr","cc" ); \ 985 * __val; }) 986 */ 987 988__kuser_get_tls: @ 0xffff0fe0 989 990#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 991 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 992#else 993 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 994#endif 995 usr_ret lr 996 997 .rep 5 998 .word 0 @ pad up to __kuser_helper_version 999 .endr 1000 1001/* 1002 * Reference declaration: 1003 * 1004 * extern unsigned int __kernel_helper_version; 1005 * 1006 * Definition and user space usage example: 1007 * 1008 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 1009 * 1010 * User space may read this to determine the curent number of helpers 1011 * available. 1012 */ 1013 1014__kuser_helper_version: @ 0xffff0ffc 1015 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1016 1017 .globl __kuser_helper_end 1018__kuser_helper_end: 1019 1020 1021/* 1022 * Vector stubs. 1023 * 1024 * This code is copied to 0xffff0200 so we can use branches in the 1025 * vectors, rather than ldr's. Note that this code must not 1026 * exceed 0x300 bytes. 1027 * 1028 * Common stub entry macro: 1029 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1030 * 1031 * SP points to a minimal amount of processor-private memory, the address 1032 * of which is copied into r0 for the mode specific abort handler. 1033 */ 1034 .macro vector_stub, name, mode, correction=0 1035 .align 5 1036 1037vector_\name: 1038 .if \correction 1039 sub lr, lr, #\correction 1040 .endif 1041 1042 @ 1043 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1044 @ (parent CPSR) 1045 @ 1046 stmia sp, {r0, lr} @ save r0, lr 1047 mrs lr, spsr 1048 str lr, [sp, #8] @ save spsr 1049 1050 @ 1051 @ Prepare for SVC32 mode. IRQs remain disabled. 1052 @ 1053 mrs r0, cpsr 1054 eor r0, r0, #(\mode ^ SVC_MODE) 1055 msr spsr_cxsf, r0 1056 1057 @ 1058 @ the branch table must immediately follow this code 1059 @ 1060 and lr, lr, #0x0f 1061 mov r0, sp 1062 ldr lr, [pc, lr, lsl #2] 1063 movs pc, lr @ branch to handler in SVC mode 1064ENDPROC(vector_\name) 1065 .endm 1066 1067 .globl __stubs_start 1068__stubs_start: 1069/* 1070 * Interrupt dispatcher 1071 */ 1072 vector_stub irq, IRQ_MODE, 4 1073 1074 .long __irq_usr @ 0 (USR_26 / USR_32) 1075 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1076 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1077 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1078 .long __irq_invalid @ 4 1079 .long __irq_invalid @ 5 1080 .long __irq_invalid @ 6 1081 .long __irq_invalid @ 7 1082 .long __irq_invalid @ 8 1083 .long __irq_invalid @ 9 1084 .long __irq_invalid @ a 1085 .long __irq_invalid @ b 1086 .long __irq_invalid @ c 1087 .long __irq_invalid @ d 1088 .long __irq_invalid @ e 1089 .long __irq_invalid @ f 1090 1091/* 1092 * Data abort dispatcher 1093 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1094 */ 1095 vector_stub dabt, ABT_MODE, 8 1096 1097 .long __dabt_usr @ 0 (USR_26 / USR_32) 1098 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1099 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1100 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1101 .long __dabt_invalid @ 4 1102 .long __dabt_invalid @ 5 1103 .long __dabt_invalid @ 6 1104 .long __dabt_invalid @ 7 1105 .long __dabt_invalid @ 8 1106 .long __dabt_invalid @ 9 1107 .long __dabt_invalid @ a 1108 .long __dabt_invalid @ b 1109 .long __dabt_invalid @ c 1110 .long __dabt_invalid @ d 1111 .long __dabt_invalid @ e 1112 .long __dabt_invalid @ f 1113 1114/* 1115 * Prefetch abort dispatcher 1116 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1117 */ 1118 vector_stub pabt, ABT_MODE, 4 1119 1120 .long __pabt_usr @ 0 (USR_26 / USR_32) 1121 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1122 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1123 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1124 .long __pabt_invalid @ 4 1125 .long __pabt_invalid @ 5 1126 .long __pabt_invalid @ 6 1127 .long __pabt_invalid @ 7 1128 .long __pabt_invalid @ 8 1129 .long __pabt_invalid @ 9 1130 .long __pabt_invalid @ a 1131 .long __pabt_invalid @ b 1132 .long __pabt_invalid @ c 1133 .long __pabt_invalid @ d 1134 .long __pabt_invalid @ e 1135 .long __pabt_invalid @ f 1136 1137/* 1138 * Undef instr entry dispatcher 1139 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1140 */ 1141 vector_stub und, UND_MODE 1142 1143 .long __und_usr @ 0 (USR_26 / USR_32) 1144 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1145 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1146 .long __und_svc @ 3 (SVC_26 / SVC_32) 1147 .long __und_invalid @ 4 1148 .long __und_invalid @ 5 1149 .long __und_invalid @ 6 1150 .long __und_invalid @ 7 1151 .long __und_invalid @ 8 1152 .long __und_invalid @ 9 1153 .long __und_invalid @ a 1154 .long __und_invalid @ b 1155 .long __und_invalid @ c 1156 .long __und_invalid @ d 1157 .long __und_invalid @ e 1158 .long __und_invalid @ f 1159 1160 .align 5 1161 1162/*============================================================================= 1163 * Undefined FIQs 1164 *----------------------------------------------------------------------------- 1165 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1166 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1167 * Basically to switch modes, we *HAVE* to clobber one register... brain 1168 * damage alert! I don't think that we can execute any code in here in any 1169 * other mode than FIQ... Ok you can switch to another mode, but you can't 1170 * get out of that mode without clobbering one register. 1171 */ 1172vector_fiq: 1173 disable_fiq 1174 subs pc, lr, #4 1175 1176/*============================================================================= 1177 * Address exception handler 1178 *----------------------------------------------------------------------------- 1179 * These aren't too critical. 1180 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1181 */ 1182 1183vector_addrexcptn: 1184 b vector_addrexcptn 1185 1186/* 1187 * We group all the following data together to optimise 1188 * for CPUs with separate I & D caches. 1189 */ 1190 .align 5 1191 1192.LCvswi: 1193 .word vector_swi 1194 1195 .globl __stubs_end 1196__stubs_end: 1197 1198 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1199 1200 .globl __vectors_start 1201__vectors_start: 1202 swi SYS_ERROR0 1203 b vector_und + stubs_offset 1204 ldr pc, .LCvswi + stubs_offset 1205 b vector_pabt + stubs_offset 1206 b vector_dabt + stubs_offset 1207 b vector_addrexcptn + stubs_offset 1208 b vector_irq + stubs_offset 1209 b vector_fiq + stubs_offset 1210 1211 .globl __vectors_end 1212__vectors_end: 1213 1214 .data 1215 1216 .globl cr_alignment 1217 .globl cr_no_alignment 1218cr_alignment: 1219 .space 4 1220cr_no_alignment: 1221 .space 4 1222