1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes 15 * it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <asm/arch/entry-macro.S> 22#include <asm/thread_notify.h> 23 24#include "entry-header.S" 25 26/* 27 * Interrupt handling. Preserves r7, r8, r9 28 */ 29 .macro irq_handler 301: get_irqnr_and_base r0, r6, r5, lr 31 movne r1, sp 32 @ 33 @ routine called with r0 = irq number, r1 = struct pt_regs * 34 @ 35 adrne lr, 1b 36 bne asm_do_IRQ 37 38#ifdef CONFIG_SMP 39 /* 40 * XXX 41 * 42 * this macro assumes that irqstat (r6) and base (r5) are 43 * preserved from get_irqnr_and_base above 44 */ 45 test_for_ipi r0, r6, r5, lr 46 movne r0, sp 47 adrne lr, 1b 48 bne do_IPI 49 50#ifdef CONFIG_LOCAL_TIMERS 51 test_for_ltirq r0, r6, r5, lr 52 movne r0, sp 53 adrne lr, 1b 54 bne do_local_timer 55#endif 56#endif 57 58 .endm 59 60/* 61 * Invalid mode handlers 62 */ 63 .macro inv_entry, reason 64 sub sp, sp, #S_FRAME_SIZE 65 stmib sp, {r1 - lr} 66 mov r1, #\reason 67 .endm 68 69__pabt_invalid: 70 inv_entry BAD_PREFETCH 71 b common_invalid 72 73__dabt_invalid: 74 inv_entry BAD_DATA 75 b common_invalid 76 77__irq_invalid: 78 inv_entry BAD_IRQ 79 b common_invalid 80 81__und_invalid: 82 inv_entry BAD_UNDEFINSTR 83 84 @ 85 @ XXX fall through to common_invalid 86 @ 87 88@ 89@ common_invalid - generic code for failed exception (re-entrant version of handlers) 90@ 91common_invalid: 92 zero_fp 93 94 ldmia r0, {r4 - r6} 95 add r0, sp, #S_PC @ here for interlock avoidance 96 mov r7, #-1 @ "" "" "" "" 97 str r4, [sp] @ save preserved r0 98 stmia r0, {r5 - r7} @ lr_<exception>, 99 @ cpsr_<exception>, "old_r0" 100 101 mov r0, sp 102 and r2, r6, #0x1f 103 b bad_mode 104 105/* 106 * SVC mode handlers 107 */ 108 109#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 110#define SPFIX(code...) code 111#else 112#define SPFIX(code...) 113#endif 114 115 .macro svc_entry 116 sub sp, sp, #S_FRAME_SIZE 117 SPFIX( tst sp, #4 ) 118 SPFIX( bicne sp, sp, #4 ) 119 stmib sp, {r1 - r12} 120 121 ldmia r0, {r1 - r3} 122 add r5, sp, #S_SP @ here for interlock avoidance 123 mov r4, #-1 @ "" "" "" "" 124 add r0, sp, #S_FRAME_SIZE @ "" "" "" "" 125 SPFIX( addne r0, r0, #4 ) 126 str r1, [sp] @ save the "real" r0 copied 127 @ from the exception stack 128 129 mov r1, lr 130 131 @ 132 @ We are now ready to fill in the remaining blanks on the stack: 133 @ 134 @ r0 - sp_svc 135 @ r1 - lr_svc 136 @ r2 - lr_<exception>, already fixed up for correct return/restart 137 @ r3 - spsr_<exception> 138 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 139 @ 140 stmia r5, {r0 - r4} 141 .endm 142 143 .align 5 144__dabt_svc: 145 svc_entry 146 147 @ 148 @ get ready to re-enable interrupts if appropriate 149 @ 150 mrs r9, cpsr 151 tst r3, #PSR_I_BIT 152 biceq r9, r9, #PSR_I_BIT 153 154 @ 155 @ Call the processor-specific abort handler: 156 @ 157 @ r2 - aborted context pc 158 @ r3 - aborted context cpsr 159 @ 160 @ The abort handler must return the aborted address in r0, and 161 @ the fault status register in r1. r9 must be preserved. 162 @ 163#ifdef MULTI_ABORT 164 ldr r4, .LCprocfns 165 mov lr, pc 166 ldr pc, [r4] 167#else 168 bl CPU_ABORT_HANDLER 169#endif 170 171 @ 172 @ set desired IRQ state, then call main handler 173 @ 174 msr cpsr_c, r9 175 mov r2, sp 176 bl do_DataAbort 177 178 @ 179 @ IRQs off again before pulling preserved data off the stack 180 @ 181 disable_irq 182 183 @ 184 @ restore SPSR and restart the instruction 185 @ 186 ldr r0, [sp, #S_PSR] 187 msr spsr_cxsf, r0 188 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 189 190 .align 5 191__irq_svc: 192 svc_entry 193 194#ifdef CONFIG_TRACE_IRQFLAGS 195 bl trace_hardirqs_off 196#endif 197#ifdef CONFIG_PREEMPT 198 get_thread_info tsk 199 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 200 add r7, r8, #1 @ increment it 201 str r7, [tsk, #TI_PREEMPT] 202#endif 203 204 irq_handler 205#ifdef CONFIG_PREEMPT 206 ldr r0, [tsk, #TI_FLAGS] @ get flags 207 tst r0, #_TIF_NEED_RESCHED 208 blne svc_preempt 209preempt_return: 210 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value 211 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 212 teq r0, r7 213 strne r0, [r0, -r0] @ bug() 214#endif 215 ldr r0, [sp, #S_PSR] @ irqs are already disabled 216 msr spsr_cxsf, r0 217#ifdef CONFIG_TRACE_IRQFLAGS 218 tst r0, #PSR_I_BIT 219 bleq trace_hardirqs_on 220#endif 221 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 222 223 .ltorg 224 225#ifdef CONFIG_PREEMPT 226svc_preempt: 227 teq r8, #0 @ was preempt count = 0 228 ldreq r6, .LCirq_stat 229 movne pc, lr @ no 230 ldr r0, [r6, #4] @ local_irq_count 231 ldr r1, [r6, #8] @ local_bh_count 232 adds r0, r0, r1 233 movne pc, lr 234 mov r7, #0 @ preempt_schedule_irq 235 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 2361: bl preempt_schedule_irq @ irq en/disable is done inside 237 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 238 tst r0, #_TIF_NEED_RESCHED 239 beq preempt_return @ go again 240 b 1b 241#endif 242 243 .align 5 244__und_svc: 245 svc_entry 246 247 @ 248 @ call emulation code, which returns using r9 if it has emulated 249 @ the instruction, or the more conventional lr if we are to treat 250 @ this as a real undefined instruction 251 @ 252 @ r0 - instruction 253 @ 254 ldr r0, [r2, #-4] 255 adr r9, 1f 256 bl call_fpe 257 258 mov r0, sp @ struct pt_regs *regs 259 bl do_undefinstr 260 261 @ 262 @ IRQs off again before pulling preserved data off the stack 263 @ 2641: disable_irq 265 266 @ 267 @ restore SPSR and restart the instruction 268 @ 269 ldr lr, [sp, #S_PSR] @ Get SVC cpsr 270 msr spsr_cxsf, lr 271 ldmia sp, {r0 - pc}^ @ Restore SVC registers 272 273 .align 5 274__pabt_svc: 275 svc_entry 276 277 @ 278 @ re-enable interrupts if appropriate 279 @ 280 mrs r9, cpsr 281 tst r3, #PSR_I_BIT 282 biceq r9, r9, #PSR_I_BIT 283 msr cpsr_c, r9 284 285 @ 286 @ set args, then call main handler 287 @ 288 @ r0 - address of faulting instruction 289 @ r1 - pointer to registers on stack 290 @ 291 mov r0, r2 @ address (pc) 292 mov r1, sp @ regs 293 bl do_PrefetchAbort @ call abort handler 294 295 @ 296 @ IRQs off again before pulling preserved data off the stack 297 @ 298 disable_irq 299 300 @ 301 @ restore SPSR and restart the instruction 302 @ 303 ldr r0, [sp, #S_PSR] 304 msr spsr_cxsf, r0 305 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 306 307 .align 5 308.LCcralign: 309 .word cr_alignment 310#ifdef MULTI_ABORT 311.LCprocfns: 312 .word processor 313#endif 314.LCfp: 315 .word fp_enter 316#ifdef CONFIG_PREEMPT 317.LCirq_stat: 318 .word irq_stat 319#endif 320 321/* 322 * User mode handlers 323 * 324 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 325 */ 326 327#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 328#error "sizeof(struct pt_regs) must be a multiple of 8" 329#endif 330 331 .macro usr_entry 332 sub sp, sp, #S_FRAME_SIZE 333 stmib sp, {r1 - r12} 334 335 ldmia r0, {r1 - r3} 336 add r0, sp, #S_PC @ here for interlock avoidance 337 mov r4, #-1 @ "" "" "" "" 338 339 str r1, [sp] @ save the "real" r0 copied 340 @ from the exception stack 341 342#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 343#ifndef CONFIG_MMU 344#warning "NPTL on non MMU needs fixing" 345#else 346 @ make sure our user space atomic helper is aborted 347 cmp r2, #TASK_SIZE 348 bichs r3, r3, #PSR_Z_BIT 349#endif 350#endif 351 352 @ 353 @ We are now ready to fill in the remaining blanks on the stack: 354 @ 355 @ r2 - lr_<exception>, already fixed up for correct return/restart 356 @ r3 - spsr_<exception> 357 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 358 @ 359 @ Also, separately save sp_usr and lr_usr 360 @ 361 stmia r0, {r2 - r4} 362 stmdb r0, {sp, lr}^ 363 364 @ 365 @ Enable the alignment trap while in kernel mode 366 @ 367 alignment_trap r0 368 369 @ 370 @ Clear FP to mark the first stack frame 371 @ 372 zero_fp 373 .endm 374 375 .align 5 376__dabt_usr: 377 usr_entry 378 379 @ 380 @ Call the processor-specific abort handler: 381 @ 382 @ r2 - aborted context pc 383 @ r3 - aborted context cpsr 384 @ 385 @ The abort handler must return the aborted address in r0, and 386 @ the fault status register in r1. 387 @ 388#ifdef MULTI_ABORT 389 ldr r4, .LCprocfns 390 mov lr, pc 391 ldr pc, [r4] 392#else 393 bl CPU_ABORT_HANDLER 394#endif 395 396 @ 397 @ IRQs on, then call the main handler 398 @ 399 enable_irq 400 mov r2, sp 401 adr lr, ret_from_exception 402 b do_DataAbort 403 404 .align 5 405__irq_usr: 406 usr_entry 407 408#ifdef CONFIG_TRACE_IRQFLAGS 409 bl trace_hardirqs_off 410#endif 411 get_thread_info tsk 412#ifdef CONFIG_PREEMPT 413 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 414 add r7, r8, #1 @ increment it 415 str r7, [tsk, #TI_PREEMPT] 416#endif 417 418 irq_handler 419#ifdef CONFIG_PREEMPT 420 ldr r0, [tsk, #TI_PREEMPT] 421 str r8, [tsk, #TI_PREEMPT] 422 teq r0, r7 423 strne r0, [r0, -r0] 424#endif 425#ifdef CONFIG_TRACE_IRQFLAGS 426 bl trace_hardirqs_on 427#endif 428 429 mov why, #0 430 b ret_to_user 431 432 .ltorg 433 434 .align 5 435__und_usr: 436 usr_entry 437 438 tst r3, #PSR_T_BIT @ Thumb mode? 439 bne fpundefinstr @ ignore FP 440 sub r4, r2, #4 441 442 @ 443 @ fall through to the emulation code, which returns using r9 if 444 @ it has emulated the instruction, or the more conventional lr 445 @ if we are to treat this as a real undefined instruction 446 @ 447 @ r0 - instruction 448 @ 4491: ldrt r0, [r4] 450 adr r9, ret_from_exception 451 adr lr, fpundefinstr 452 @ 453 @ fallthrough to call_fpe 454 @ 455 456/* 457 * The out of line fixup for the ldrt above. 458 */ 459 .section .fixup, "ax" 4602: mov pc, r9 461 .previous 462 .section __ex_table,"a" 463 .long 1b, 2b 464 .previous 465 466/* 467 * Check whether the instruction is a co-processor instruction. 468 * If yes, we need to call the relevant co-processor handler. 469 * 470 * Note that we don't do a full check here for the co-processor 471 * instructions; all instructions with bit 27 set are well 472 * defined. The only instructions that should fault are the 473 * co-processor instructions. However, we have to watch out 474 * for the ARM6/ARM7 SWI bug. 475 * 476 * Emulators may wish to make use of the following registers: 477 * r0 = instruction opcode. 478 * r2 = PC+4 479 * r10 = this threads thread_info structure. 480 */ 481call_fpe: 482 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 483#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 484 and r8, r0, #0x0f000000 @ mask out op-code bits 485 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 486#endif 487 moveq pc, lr 488 get_thread_info r10 @ get current thread 489 and r8, r0, #0x00000f00 @ mask out CP number 490 mov r7, #1 491 add r6, r10, #TI_USED_CP 492 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] 493#ifdef CONFIG_IWMMXT 494 @ Test if we need to give access to iWMMXt coprocessors 495 ldr r5, [r10, #TI_FLAGS] 496 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 497 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 498 bcs iwmmxt_task_enable 499#endif 500 add pc, pc, r8, lsr #6 501 mov r0, r0 502 503 mov pc, lr @ CP#0 504 b do_fpe @ CP#1 (FPE) 505 b do_fpe @ CP#2 (FPE) 506 mov pc, lr @ CP#3 507#ifdef CONFIG_CRUNCH 508 b crunch_task_enable @ CP#4 (MaverickCrunch) 509 b crunch_task_enable @ CP#5 (MaverickCrunch) 510 b crunch_task_enable @ CP#6 (MaverickCrunch) 511#else 512 mov pc, lr @ CP#4 513 mov pc, lr @ CP#5 514 mov pc, lr @ CP#6 515#endif 516 mov pc, lr @ CP#7 517 mov pc, lr @ CP#8 518 mov pc, lr @ CP#9 519#ifdef CONFIG_VFP 520 b do_vfp @ CP#10 (VFP) 521 b do_vfp @ CP#11 (VFP) 522#else 523 mov pc, lr @ CP#10 (VFP) 524 mov pc, lr @ CP#11 (VFP) 525#endif 526 mov pc, lr @ CP#12 527 mov pc, lr @ CP#13 528 mov pc, lr @ CP#14 (Debug) 529 mov pc, lr @ CP#15 (Control) 530 531do_fpe: 532 enable_irq 533 ldr r4, .LCfp 534 add r10, r10, #TI_FPSTATE @ r10 = workspace 535 ldr pc, [r4] @ Call FP module USR entry point 536 537/* 538 * The FP module is called with these registers set: 539 * r0 = instruction 540 * r2 = PC+4 541 * r9 = normal "successful" return address 542 * r10 = FP workspace 543 * lr = unrecognised FP instruction return address 544 */ 545 546 .data 547ENTRY(fp_enter) 548 .word fpundefinstr 549 .text 550 551fpundefinstr: 552 mov r0, sp 553 adr lr, ret_from_exception 554 b do_undefinstr 555 556 .align 5 557__pabt_usr: 558 usr_entry 559 560 enable_irq @ Enable interrupts 561 mov r0, r2 @ address (pc) 562 mov r1, sp @ regs 563 bl do_PrefetchAbort @ call abort handler 564 /* fall through */ 565/* 566 * This is the return code to user mode for abort handlers 567 */ 568ENTRY(ret_from_exception) 569 get_thread_info tsk 570 mov why, #0 571 b ret_to_user 572 573/* 574 * Register switch for ARMv3 and ARMv4 processors 575 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 576 * previous and next are guaranteed not to be the same. 577 */ 578ENTRY(__switch_to) 579 add ip, r1, #TI_CPU_SAVE 580 ldr r3, [r2, #TI_TP_VALUE] 581 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack 582#ifdef CONFIG_MMU 583 ldr r6, [r2, #TI_CPU_DOMAIN] 584#endif 585#if __LINUX_ARM_ARCH__ >= 6 586#ifdef CONFIG_CPU_32v6K 587 clrex 588#else 589 strex r5, r4, [ip] @ Clear exclusive monitor 590#endif 591#endif 592#if defined(CONFIG_HAS_TLS_REG) 593 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 594#elif !defined(CONFIG_TLS_REG_EMUL) 595 mov r4, #0xffff0fff 596 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 597#endif 598#ifdef CONFIG_MMU 599 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 600#endif 601 mov r5, r0 602 add r4, r2, #TI_CPU_SAVE 603 ldr r0, =thread_notify_head 604 mov r1, #THREAD_NOTIFY_SWITCH 605 bl atomic_notifier_call_chain 606 mov r0, r5 607 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 608 609 __INIT 610 611/* 612 * User helpers. 613 * 614 * These are segment of kernel provided user code reachable from user space 615 * at a fixed address in kernel memory. This is used to provide user space 616 * with some operations which require kernel help because of unimplemented 617 * native feature and/or instructions in many ARM CPUs. The idea is for 618 * this code to be executed directly in user mode for best efficiency but 619 * which is too intimate with the kernel counter part to be left to user 620 * libraries. In fact this code might even differ from one CPU to another 621 * depending on the available instruction set and restrictions like on 622 * SMP systems. In other words, the kernel reserves the right to change 623 * this code as needed without warning. Only the entry points and their 624 * results are guaranteed to be stable. 625 * 626 * Each segment is 32-byte aligned and will be moved to the top of the high 627 * vector page. New segments (if ever needed) must be added in front of 628 * existing ones. This mechanism should be used only for things that are 629 * really small and justified, and not be abused freely. 630 * 631 * User space is expected to implement those things inline when optimizing 632 * for a processor that has the necessary native support, but only if such 633 * resulting binaries are already to be incompatible with earlier ARM 634 * processors due to the use of unsupported instructions other than what 635 * is provided here. In other words don't make binaries unable to run on 636 * earlier processors just for the sake of not using these kernel helpers 637 * if your compiled code is not going to use the new instructions for other 638 * purpose. 639 */ 640 641 .macro usr_ret, reg 642#ifdef CONFIG_ARM_THUMB 643 bx \reg 644#else 645 mov pc, \reg 646#endif 647 .endm 648 649 .align 5 650 .globl __kuser_helper_start 651__kuser_helper_start: 652 653/* 654 * Reference prototype: 655 * 656 * void __kernel_memory_barrier(void) 657 * 658 * Input: 659 * 660 * lr = return address 661 * 662 * Output: 663 * 664 * none 665 * 666 * Clobbered: 667 * 668 * the Z flag might be lost 669 * 670 * Definition and user space usage example: 671 * 672 * typedef void (__kernel_dmb_t)(void); 673 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 674 * 675 * Apply any needed memory barrier to preserve consistency with data modified 676 * manually and __kuser_cmpxchg usage. 677 * 678 * This could be used as follows: 679 * 680 * #define __kernel_dmb() \ 681 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 682 * : : : "r0", "lr","cc" ) 683 */ 684 685__kuser_memory_barrier: @ 0xffff0fa0 686 687#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) 688 mcr p15, 0, r0, c7, c10, 5 @ dmb 689#endif 690 usr_ret lr 691 692 .align 5 693 694/* 695 * Reference prototype: 696 * 697 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 698 * 699 * Input: 700 * 701 * r0 = oldval 702 * r1 = newval 703 * r2 = ptr 704 * lr = return address 705 * 706 * Output: 707 * 708 * r0 = returned value (zero or non-zero) 709 * C flag = set if r0 == 0, clear if r0 != 0 710 * 711 * Clobbered: 712 * 713 * r3, ip, flags 714 * 715 * Definition and user space usage example: 716 * 717 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 718 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 719 * 720 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 721 * Return zero if *ptr was changed or non-zero if no exchange happened. 722 * The C flag is also set if *ptr was changed to allow for assembly 723 * optimization in the calling code. 724 * 725 * Notes: 726 * 727 * - This routine already includes memory barriers as needed. 728 * 729 * - A failure might be transient, i.e. it is possible, although unlikely, 730 * that "failure" be returned even if *ptr == oldval. 731 * 732 * For example, a user space atomic_add implementation could look like this: 733 * 734 * #define atomic_add(ptr, val) \ 735 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 736 * register unsigned int __result asm("r1"); \ 737 * asm volatile ( \ 738 * "1: @ atomic_add\n\t" \ 739 * "ldr r0, [r2]\n\t" \ 740 * "mov r3, #0xffff0fff\n\t" \ 741 * "add lr, pc, #4\n\t" \ 742 * "add r1, r0, %2\n\t" \ 743 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 744 * "bcc 1b" \ 745 * : "=&r" (__result) \ 746 * : "r" (__ptr), "rIL" (val) \ 747 * : "r0","r3","ip","lr","cc","memory" ); \ 748 * __result; }) 749 */ 750 751__kuser_cmpxchg: @ 0xffff0fc0 752 753#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 754 755 /* 756 * Poor you. No fast solution possible... 757 * The kernel itself must perform the operation. 758 * A special ghost syscall is used for that (see traps.c). 759 */ 760 stmfd sp!, {r7, lr} 761 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 762 orr r7, r7, #0xf0 763 swi #0x9ffff0 764 ldmfd sp!, {r7, pc} 765 766#elif __LINUX_ARM_ARCH__ < 6 767 768 /* 769 * Theory of operation: 770 * 771 * We set the Z flag before loading oldval. If ever an exception 772 * occurs we can not be sure the loaded value will still be the same 773 * when the exception returns, therefore the user exception handler 774 * will clear the Z flag whenever the interrupted user code was 775 * actually from the kernel address space (see the usr_entry macro). 776 * 777 * The post-increment on the str is used to prevent a race with an 778 * exception happening just after the str instruction which would 779 * clear the Z flag although the exchange was done. 780 */ 781#ifdef CONFIG_MMU 782 teq ip, ip @ set Z flag 783 ldr ip, [r2] @ load current val 784 add r3, r2, #1 @ prepare store ptr 785 teqeq ip, r0 @ compare with oldval if still allowed 786 streq r1, [r3, #-1]! @ store newval if still allowed 787 subs r0, r2, r3 @ if r2 == r3 the str occured 788#else 789#warning "NPTL on non MMU needs fixing" 790 mov r0, #-1 791 adds r0, r0, #0 792#endif 793 usr_ret lr 794 795#else 796 797#ifdef CONFIG_SMP 798 mcr p15, 0, r0, c7, c10, 5 @ dmb 799#endif 800 ldrex r3, [r2] 801 subs r3, r3, r0 802 strexeq r3, r1, [r2] 803 rsbs r0, r3, #0 804#ifdef CONFIG_SMP 805 mcr p15, 0, r0, c7, c10, 5 @ dmb 806#endif 807 usr_ret lr 808 809#endif 810 811 .align 5 812 813/* 814 * Reference prototype: 815 * 816 * int __kernel_get_tls(void) 817 * 818 * Input: 819 * 820 * lr = return address 821 * 822 * Output: 823 * 824 * r0 = TLS value 825 * 826 * Clobbered: 827 * 828 * the Z flag might be lost 829 * 830 * Definition and user space usage example: 831 * 832 * typedef int (__kernel_get_tls_t)(void); 833 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 834 * 835 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 836 * 837 * This could be used as follows: 838 * 839 * #define __kernel_get_tls() \ 840 * ({ register unsigned int __val asm("r0"); \ 841 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 842 * : "=r" (__val) : : "lr","cc" ); \ 843 * __val; }) 844 */ 845 846__kuser_get_tls: @ 0xffff0fe0 847 848#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 849 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 850#else 851 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 852#endif 853 usr_ret lr 854 855 .rep 5 856 .word 0 @ pad up to __kuser_helper_version 857 .endr 858 859/* 860 * Reference declaration: 861 * 862 * extern unsigned int __kernel_helper_version; 863 * 864 * Definition and user space usage example: 865 * 866 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 867 * 868 * User space may read this to determine the curent number of helpers 869 * available. 870 */ 871 872__kuser_helper_version: @ 0xffff0ffc 873 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 874 875 .globl __kuser_helper_end 876__kuser_helper_end: 877 878 879/* 880 * Vector stubs. 881 * 882 * This code is copied to 0xffff0200 so we can use branches in the 883 * vectors, rather than ldr's. Note that this code must not 884 * exceed 0x300 bytes. 885 * 886 * Common stub entry macro: 887 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 888 * 889 * SP points to a minimal amount of processor-private memory, the address 890 * of which is copied into r0 for the mode specific abort handler. 891 */ 892 .macro vector_stub, name, mode, correction=0 893 .align 5 894 895vector_\name: 896 .if \correction 897 sub lr, lr, #\correction 898 .endif 899 900 @ 901 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 902 @ (parent CPSR) 903 @ 904 stmia sp, {r0, lr} @ save r0, lr 905 mrs lr, spsr 906 str lr, [sp, #8] @ save spsr 907 908 @ 909 @ Prepare for SVC32 mode. IRQs remain disabled. 910 @ 911 mrs r0, cpsr 912 eor r0, r0, #(\mode ^ SVC_MODE) 913 msr spsr_cxsf, r0 914 915 @ 916 @ the branch table must immediately follow this code 917 @ 918 and lr, lr, #0x0f 919 mov r0, sp 920 ldr lr, [pc, lr, lsl #2] 921 movs pc, lr @ branch to handler in SVC mode 922 .endm 923 924 .globl __stubs_start 925__stubs_start: 926/* 927 * Interrupt dispatcher 928 */ 929 vector_stub irq, IRQ_MODE, 4 930 931 .long __irq_usr @ 0 (USR_26 / USR_32) 932 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 933 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 934 .long __irq_svc @ 3 (SVC_26 / SVC_32) 935 .long __irq_invalid @ 4 936 .long __irq_invalid @ 5 937 .long __irq_invalid @ 6 938 .long __irq_invalid @ 7 939 .long __irq_invalid @ 8 940 .long __irq_invalid @ 9 941 .long __irq_invalid @ a 942 .long __irq_invalid @ b 943 .long __irq_invalid @ c 944 .long __irq_invalid @ d 945 .long __irq_invalid @ e 946 .long __irq_invalid @ f 947 948/* 949 * Data abort dispatcher 950 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 951 */ 952 vector_stub dabt, ABT_MODE, 8 953 954 .long __dabt_usr @ 0 (USR_26 / USR_32) 955 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 956 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 957 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 958 .long __dabt_invalid @ 4 959 .long __dabt_invalid @ 5 960 .long __dabt_invalid @ 6 961 .long __dabt_invalid @ 7 962 .long __dabt_invalid @ 8 963 .long __dabt_invalid @ 9 964 .long __dabt_invalid @ a 965 .long __dabt_invalid @ b 966 .long __dabt_invalid @ c 967 .long __dabt_invalid @ d 968 .long __dabt_invalid @ e 969 .long __dabt_invalid @ f 970 971/* 972 * Prefetch abort dispatcher 973 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 974 */ 975 vector_stub pabt, ABT_MODE, 4 976 977 .long __pabt_usr @ 0 (USR_26 / USR_32) 978 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 979 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 980 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 981 .long __pabt_invalid @ 4 982 .long __pabt_invalid @ 5 983 .long __pabt_invalid @ 6 984 .long __pabt_invalid @ 7 985 .long __pabt_invalid @ 8 986 .long __pabt_invalid @ 9 987 .long __pabt_invalid @ a 988 .long __pabt_invalid @ b 989 .long __pabt_invalid @ c 990 .long __pabt_invalid @ d 991 .long __pabt_invalid @ e 992 .long __pabt_invalid @ f 993 994/* 995 * Undef instr entry dispatcher 996 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 997 */ 998 vector_stub und, UND_MODE 999 1000 .long __und_usr @ 0 (USR_26 / USR_32) 1001 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1002 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1003 .long __und_svc @ 3 (SVC_26 / SVC_32) 1004 .long __und_invalid @ 4 1005 .long __und_invalid @ 5 1006 .long __und_invalid @ 6 1007 .long __und_invalid @ 7 1008 .long __und_invalid @ 8 1009 .long __und_invalid @ 9 1010 .long __und_invalid @ a 1011 .long __und_invalid @ b 1012 .long __und_invalid @ c 1013 .long __und_invalid @ d 1014 .long __und_invalid @ e 1015 .long __und_invalid @ f 1016 1017 .align 5 1018 1019/*============================================================================= 1020 * Undefined FIQs 1021 *----------------------------------------------------------------------------- 1022 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1023 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1024 * Basically to switch modes, we *HAVE* to clobber one register... brain 1025 * damage alert! I don't think that we can execute any code in here in any 1026 * other mode than FIQ... Ok you can switch to another mode, but you can't 1027 * get out of that mode without clobbering one register. 1028 */ 1029vector_fiq: 1030 disable_fiq 1031 subs pc, lr, #4 1032 1033/*============================================================================= 1034 * Address exception handler 1035 *----------------------------------------------------------------------------- 1036 * These aren't too critical. 1037 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1038 */ 1039 1040vector_addrexcptn: 1041 b vector_addrexcptn 1042 1043/* 1044 * We group all the following data together to optimise 1045 * for CPUs with separate I & D caches. 1046 */ 1047 .align 5 1048 1049.LCvswi: 1050 .word vector_swi 1051 1052 .globl __stubs_end 1053__stubs_end: 1054 1055 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1056 1057 .globl __vectors_start 1058__vectors_start: 1059 swi SYS_ERROR0 1060 b vector_und + stubs_offset 1061 ldr pc, .LCvswi + stubs_offset 1062 b vector_pabt + stubs_offset 1063 b vector_dabt + stubs_offset 1064 b vector_addrexcptn + stubs_offset 1065 b vector_irq + stubs_offset 1066 b vector_fiq + stubs_offset 1067 1068 .globl __vectors_end 1069__vectors_end: 1070 1071 .data 1072 1073 .globl cr_alignment 1074 .globl cr_no_alignment 1075cr_alignment: 1076 .space 4 1077cr_no_alignment: 1078 .space 4 1079