1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <mach/entry-macro.S> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24 25#include "entry-header.S" 26 27/* 28 * Interrupt handling. Preserves r7, r8, r9 29 */ 30 .macro irq_handler 31 get_irqnr_preamble r5, lr 321: get_irqnr_and_base r0, r6, r5, lr 33 movne r1, sp 34 @ 35 @ routine called with r0 = irq number, r1 = struct pt_regs * 36 @ 37 adrne lr, BSYM(1b) 38 bne asm_do_IRQ 39 40#ifdef CONFIG_SMP 41 /* 42 * XXX 43 * 44 * this macro assumes that irqstat (r6) and base (r5) are 45 * preserved from get_irqnr_and_base above 46 */ 47 test_for_ipi r0, r6, r5, lr 48 movne r0, sp 49 adrne lr, BSYM(1b) 50 bne do_IPI 51 52#ifdef CONFIG_LOCAL_TIMERS 53 test_for_ltirq r0, r6, r5, lr 54 movne r0, sp 55 adrne lr, BSYM(1b) 56 bne do_local_timer 57#endif 58#endif 59 60 .endm 61 62#ifdef CONFIG_KPROBES 63 .section .kprobes.text,"ax",%progbits 64#else 65 .text 66#endif 67 68/* 69 * Invalid mode handlers 70 */ 71 .macro inv_entry, reason 72 sub sp, sp, #S_FRAME_SIZE 73 ARM( stmib sp, {r1 - lr} ) 74 THUMB( stmia sp, {r0 - r12} ) 75 THUMB( str sp, [sp, #S_SP] ) 76 THUMB( str lr, [sp, #S_LR] ) 77 mov r1, #\reason 78 .endm 79 80__pabt_invalid: 81 inv_entry BAD_PREFETCH 82 b common_invalid 83ENDPROC(__pabt_invalid) 84 85__dabt_invalid: 86 inv_entry BAD_DATA 87 b common_invalid 88ENDPROC(__dabt_invalid) 89 90__irq_invalid: 91 inv_entry BAD_IRQ 92 b common_invalid 93ENDPROC(__irq_invalid) 94 95__und_invalid: 96 inv_entry BAD_UNDEFINSTR 97 98 @ 99 @ XXX fall through to common_invalid 100 @ 101 102@ 103@ common_invalid - generic code for failed exception (re-entrant version of handlers) 104@ 105common_invalid: 106 zero_fp 107 108 ldmia r0, {r4 - r6} 109 add r0, sp, #S_PC @ here for interlock avoidance 110 mov r7, #-1 @ "" "" "" "" 111 str r4, [sp] @ save preserved r0 112 stmia r0, {r5 - r7} @ lr_<exception>, 113 @ cpsr_<exception>, "old_r0" 114 115 mov r0, sp 116 b bad_mode 117ENDPROC(__und_invalid) 118 119/* 120 * SVC mode handlers 121 */ 122 123#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 124#define SPFIX(code...) code 125#else 126#define SPFIX(code...) 127#endif 128 129 .macro svc_entry, stack_hole=0 130 UNWIND(.fnstart ) 131 UNWIND(.save {r0 - pc} ) 132 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 133#ifdef CONFIG_THUMB2_KERNEL 134 SPFIX( str r0, [sp] ) @ temporarily saved 135 SPFIX( mov r0, sp ) 136 SPFIX( tst r0, #4 ) @ test original stack alignment 137 SPFIX( ldr r0, [sp] ) @ restored 138#else 139 SPFIX( tst sp, #4 ) 140#endif 141 SPFIX( subeq sp, sp, #4 ) 142 stmia sp, {r1 - r12} 143 144 ldmia r0, {r1 - r3} 145 add r5, sp, #S_SP - 4 @ here for interlock avoidance 146 mov r4, #-1 @ "" "" "" "" 147 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4) 148 SPFIX( addeq r0, r0, #4 ) 149 str r1, [sp, #-4]! @ save the "real" r0 copied 150 @ from the exception stack 151 152 mov r1, lr 153 154 @ 155 @ We are now ready to fill in the remaining blanks on the stack: 156 @ 157 @ r0 - sp_svc 158 @ r1 - lr_svc 159 @ r2 - lr_<exception>, already fixed up for correct return/restart 160 @ r3 - spsr_<exception> 161 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 162 @ 163 stmia r5, {r0 - r4} 164 165 asm_trace_hardirqs_off 166 .endm 167 168 .align 5 169__dabt_svc: 170 svc_entry 171 172 @ 173 @ get ready to re-enable interrupts if appropriate 174 @ 175 mrs r9, cpsr 176 tst r3, #PSR_I_BIT 177 biceq r9, r9, #PSR_I_BIT 178 179 @ 180 @ Call the processor-specific abort handler: 181 @ 182 @ r2 - aborted context pc 183 @ r3 - aborted context cpsr 184 @ 185 @ The abort handler must return the aborted address in r0, and 186 @ the fault status register in r1. r9 must be preserved. 187 @ 188#ifdef MULTI_DABORT 189 ldr r4, .LCprocfns 190 mov lr, pc 191 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 192#else 193 bl CPU_DABORT_HANDLER 194#endif 195 196 @ 197 @ set desired IRQ state, then call main handler 198 @ 199 msr cpsr_c, r9 200 mov r2, sp 201 bl do_DataAbort 202 203 @ 204 @ IRQs off again before pulling preserved data off the stack 205 @ 206 disable_irq 207 208 @ 209 @ restore SPSR and restart the instruction 210 @ 211 ldr r2, [sp, #S_PSR] 212 svc_exit r2 @ return from exception 213 UNWIND(.fnend ) 214ENDPROC(__dabt_svc) 215 216 .align 5 217__irq_svc: 218 svc_entry 219 220#ifdef CONFIG_PREEMPT 221 get_thread_info tsk 222 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 223 add r7, r8, #1 @ increment it 224 str r7, [tsk, #TI_PREEMPT] 225#endif 226 227 irq_handler 228#ifdef CONFIG_PREEMPT 229 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 230 ldr r0, [tsk, #TI_FLAGS] @ get flags 231 teq r8, #0 @ if preempt count != 0 232 movne r0, #0 @ force flags to 0 233 tst r0, #_TIF_NEED_RESCHED 234 blne svc_preempt 235#endif 236 ldr r4, [sp, #S_PSR] @ irqs are already disabled 237#ifdef CONFIG_TRACE_IRQFLAGS 238 tst r4, #PSR_I_BIT 239 bleq trace_hardirqs_on 240#endif 241 svc_exit r4 @ return from exception 242 UNWIND(.fnend ) 243ENDPROC(__irq_svc) 244 245 .ltorg 246 247#ifdef CONFIG_PREEMPT 248svc_preempt: 249 mov r8, lr 2501: bl preempt_schedule_irq @ irq en/disable is done inside 251 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 252 tst r0, #_TIF_NEED_RESCHED 253 moveq pc, r8 @ go again 254 b 1b 255#endif 256 257 .align 5 258__und_svc: 259#ifdef CONFIG_KPROBES 260 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 261 @ it obviously needs free stack space which then will belong to 262 @ the saved context. 263 svc_entry 64 264#else 265 svc_entry 266#endif 267 268 @ 269 @ call emulation code, which returns using r9 if it has emulated 270 @ the instruction, or the more conventional lr if we are to treat 271 @ this as a real undefined instruction 272 @ 273 @ r0 - instruction 274 @ 275#ifndef CONFIG_THUMB2_KERNEL 276 ldr r0, [r2, #-4] 277#else 278 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2 279 and r9, r0, #0xf800 280 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 281 ldrhhs r9, [r2] @ bottom 16 bits 282 orrhs r0, r9, r0, lsl #16 283#endif 284 adr r9, BSYM(1f) 285 bl call_fpe 286 287 mov r0, sp @ struct pt_regs *regs 288 bl do_undefinstr 289 290 @ 291 @ IRQs off again before pulling preserved data off the stack 292 @ 2931: disable_irq 294 295 @ 296 @ restore SPSR and restart the instruction 297 @ 298 ldr r2, [sp, #S_PSR] @ Get SVC cpsr 299 svc_exit r2 @ return from exception 300 UNWIND(.fnend ) 301ENDPROC(__und_svc) 302 303 .align 5 304__pabt_svc: 305 svc_entry 306 307 @ 308 @ re-enable interrupts if appropriate 309 @ 310 mrs r9, cpsr 311 tst r3, #PSR_I_BIT 312 biceq r9, r9, #PSR_I_BIT 313 314 @ 315 @ set args, then call main handler 316 @ 317 @ r0 - address of faulting instruction 318 @ r1 - pointer to registers on stack 319 @ 320#ifdef MULTI_PABORT 321 mov r0, r2 @ pass address of aborted instruction. 322 ldr r4, .LCprocfns 323 mov lr, pc 324 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 325#else 326 CPU_PABORT_HANDLER(r0, r2) 327#endif 328 msr cpsr_c, r9 @ Maybe enable interrupts 329 mov r1, sp @ regs 330 bl do_PrefetchAbort @ call abort handler 331 332 @ 333 @ IRQs off again before pulling preserved data off the stack 334 @ 335 disable_irq 336 337 @ 338 @ restore SPSR and restart the instruction 339 @ 340 ldr r2, [sp, #S_PSR] 341 svc_exit r2 @ return from exception 342 UNWIND(.fnend ) 343ENDPROC(__pabt_svc) 344 345 .align 5 346.LCcralign: 347 .word cr_alignment 348#ifdef MULTI_DABORT 349.LCprocfns: 350 .word processor 351#endif 352.LCfp: 353 .word fp_enter 354 355/* 356 * User mode handlers 357 * 358 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 359 */ 360 361#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 362#error "sizeof(struct pt_regs) must be a multiple of 8" 363#endif 364 365 .macro usr_entry 366 UNWIND(.fnstart ) 367 UNWIND(.cantunwind ) @ don't unwind the user space 368 sub sp, sp, #S_FRAME_SIZE 369 ARM( stmib sp, {r1 - r12} ) 370 THUMB( stmia sp, {r0 - r12} ) 371 372 ldmia r0, {r1 - r3} 373 add r0, sp, #S_PC @ here for interlock avoidance 374 mov r4, #-1 @ "" "" "" "" 375 376 str r1, [sp] @ save the "real" r0 copied 377 @ from the exception stack 378 379 @ 380 @ We are now ready to fill in the remaining blanks on the stack: 381 @ 382 @ r2 - lr_<exception>, already fixed up for correct return/restart 383 @ r3 - spsr_<exception> 384 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 385 @ 386 @ Also, separately save sp_usr and lr_usr 387 @ 388 stmia r0, {r2 - r4} 389 ARM( stmdb r0, {sp, lr}^ ) 390 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 391 392 @ 393 @ Enable the alignment trap while in kernel mode 394 @ 395 alignment_trap r0 396 397 @ 398 @ Clear FP to mark the first stack frame 399 @ 400 zero_fp 401 402 asm_trace_hardirqs_off 403 .endm 404 405 .macro kuser_cmpxchg_check 406#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 407#ifndef CONFIG_MMU 408#warning "NPTL on non MMU needs fixing" 409#else 410 @ Make sure our user space atomic helper is restarted 411 @ if it was interrupted in a critical region. Here we 412 @ perform a quick test inline since it should be false 413 @ 99.9999% of the time. The rest is done out of line. 414 cmp r2, #TASK_SIZE 415 blhs kuser_cmpxchg_fixup 416#endif 417#endif 418 .endm 419 420 .align 5 421__dabt_usr: 422 usr_entry 423 kuser_cmpxchg_check 424 425 @ 426 @ Call the processor-specific abort handler: 427 @ 428 @ r2 - aborted context pc 429 @ r3 - aborted context cpsr 430 @ 431 @ The abort handler must return the aborted address in r0, and 432 @ the fault status register in r1. 433 @ 434#ifdef MULTI_DABORT 435 ldr r4, .LCprocfns 436 mov lr, pc 437 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 438#else 439 bl CPU_DABORT_HANDLER 440#endif 441 442 @ 443 @ IRQs on, then call the main handler 444 @ 445 enable_irq 446 mov r2, sp 447 adr lr, BSYM(ret_from_exception) 448 b do_DataAbort 449 UNWIND(.fnend ) 450ENDPROC(__dabt_usr) 451 452 .align 5 453__irq_usr: 454 usr_entry 455 kuser_cmpxchg_check 456 457 get_thread_info tsk 458#ifdef CONFIG_PREEMPT 459 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 460 add r7, r8, #1 @ increment it 461 str r7, [tsk, #TI_PREEMPT] 462#endif 463 464 irq_handler 465#ifdef CONFIG_PREEMPT 466 ldr r0, [tsk, #TI_PREEMPT] 467 str r8, [tsk, #TI_PREEMPT] 468 teq r0, r7 469 ARM( strne r0, [r0, -r0] ) 470 THUMB( movne r0, #0 ) 471 THUMB( strne r0, [r0] ) 472#endif 473#ifdef CONFIG_TRACE_IRQFLAGS 474 bl trace_hardirqs_on 475#endif 476 477 mov why, #0 478 b ret_to_user 479 UNWIND(.fnend ) 480ENDPROC(__irq_usr) 481 482 .ltorg 483 484 .align 5 485__und_usr: 486 usr_entry 487 488 @ 489 @ fall through to the emulation code, which returns using r9 if 490 @ it has emulated the instruction, or the more conventional lr 491 @ if we are to treat this as a real undefined instruction 492 @ 493 @ r0 - instruction 494 @ 495 adr r9, BSYM(ret_from_exception) 496 adr lr, BSYM(__und_usr_unknown) 497 tst r3, #PSR_T_BIT @ Thumb mode? 498 itet eq @ explicit IT needed for the 1f label 499 subeq r4, r2, #4 @ ARM instr at LR - 4 500 subne r4, r2, #2 @ Thumb instr at LR - 2 5011: ldreqt r0, [r4] 502#ifdef CONFIG_CPU_ENDIAN_BE8 503 reveq r0, r0 @ little endian instruction 504#endif 505 beq call_fpe 506 @ Thumb instruction 507#if __LINUX_ARM_ARCH__ >= 7 5082: 509 ARM( ldrht r5, [r4], #2 ) 510 THUMB( ldrht r5, [r4] ) 511 THUMB( add r4, r4, #2 ) 512 and r0, r5, #0xf800 @ mask bits 111x x... .... .... 513 cmp r0, #0xe800 @ 32bit instruction if xx != 0 514 blo __und_usr_unknown 5153: ldrht r0, [r4] 516 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 517 orr r0, r0, r5, lsl #16 518#else 519 b __und_usr_unknown 520#endif 521 UNWIND(.fnend ) 522ENDPROC(__und_usr) 523 524 @ 525 @ fallthrough to call_fpe 526 @ 527 528/* 529 * The out of line fixup for the ldrt above. 530 */ 531 .section .fixup, "ax" 5324: mov pc, r9 533 .previous 534 .section __ex_table,"a" 535 .long 1b, 4b 536#if __LINUX_ARM_ARCH__ >= 7 537 .long 2b, 4b 538 .long 3b, 4b 539#endif 540 .previous 541 542/* 543 * Check whether the instruction is a co-processor instruction. 544 * If yes, we need to call the relevant co-processor handler. 545 * 546 * Note that we don't do a full check here for the co-processor 547 * instructions; all instructions with bit 27 set are well 548 * defined. The only instructions that should fault are the 549 * co-processor instructions. However, we have to watch out 550 * for the ARM6/ARM7 SWI bug. 551 * 552 * NEON is a special case that has to be handled here. Not all 553 * NEON instructions are co-processor instructions, so we have 554 * to make a special case of checking for them. Plus, there's 555 * five groups of them, so we have a table of mask/opcode pairs 556 * to check against, and if any match then we branch off into the 557 * NEON handler code. 558 * 559 * Emulators may wish to make use of the following registers: 560 * r0 = instruction opcode. 561 * r2 = PC+4 562 * r9 = normal "successful" return address 563 * r10 = this threads thread_info structure. 564 * lr = unrecognised instruction return address 565 */ 566 @ 567 @ Fall-through from Thumb-2 __und_usr 568 @ 569#ifdef CONFIG_NEON 570 adr r6, .LCneon_thumb_opcodes 571 b 2f 572#endif 573call_fpe: 574#ifdef CONFIG_NEON 575 adr r6, .LCneon_arm_opcodes 5762: 577 ldr r7, [r6], #4 @ mask value 578 cmp r7, #0 @ end mask? 579 beq 1f 580 and r8, r0, r7 581 ldr r7, [r6], #4 @ opcode bits matching in mask 582 cmp r8, r7 @ NEON instruction? 583 bne 2b 584 get_thread_info r10 585 mov r7, #1 586 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 587 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 588 b do_vfp @ let VFP handler handle this 5891: 590#endif 591 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 592 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 593#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 594 and r8, r0, #0x0f000000 @ mask out op-code bits 595 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 596#endif 597 moveq pc, lr 598 get_thread_info r10 @ get current thread 599 and r8, r0, #0x00000f00 @ mask out CP number 600 THUMB( lsr r8, r8, #8 ) 601 mov r7, #1 602 add r6, r10, #TI_USED_CP 603 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 604 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 605#ifdef CONFIG_IWMMXT 606 @ Test if we need to give access to iWMMXt coprocessors 607 ldr r5, [r10, #TI_FLAGS] 608 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 609 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 610 bcs iwmmxt_task_enable 611#endif 612 ARM( add pc, pc, r8, lsr #6 ) 613 THUMB( lsl r8, r8, #2 ) 614 THUMB( add pc, r8 ) 615 nop 616 617 W(mov) pc, lr @ CP#0 618 W(b) do_fpe @ CP#1 (FPE) 619 W(b) do_fpe @ CP#2 (FPE) 620 W(mov) pc, lr @ CP#3 621#ifdef CONFIG_CRUNCH 622 b crunch_task_enable @ CP#4 (MaverickCrunch) 623 b crunch_task_enable @ CP#5 (MaverickCrunch) 624 b crunch_task_enable @ CP#6 (MaverickCrunch) 625#else 626 W(mov) pc, lr @ CP#4 627 W(mov) pc, lr @ CP#5 628 W(mov) pc, lr @ CP#6 629#endif 630 W(mov) pc, lr @ CP#7 631 W(mov) pc, lr @ CP#8 632 W(mov) pc, lr @ CP#9 633#ifdef CONFIG_VFP 634 W(b) do_vfp @ CP#10 (VFP) 635 W(b) do_vfp @ CP#11 (VFP) 636#else 637 W(mov) pc, lr @ CP#10 (VFP) 638 W(mov) pc, lr @ CP#11 (VFP) 639#endif 640 W(mov) pc, lr @ CP#12 641 W(mov) pc, lr @ CP#13 642 W(mov) pc, lr @ CP#14 (Debug) 643 W(mov) pc, lr @ CP#15 (Control) 644 645#ifdef CONFIG_NEON 646 .align 6 647 648.LCneon_arm_opcodes: 649 .word 0xfe000000 @ mask 650 .word 0xf2000000 @ opcode 651 652 .word 0xff100000 @ mask 653 .word 0xf4000000 @ opcode 654 655 .word 0x00000000 @ mask 656 .word 0x00000000 @ opcode 657 658.LCneon_thumb_opcodes: 659 .word 0xef000000 @ mask 660 .word 0xef000000 @ opcode 661 662 .word 0xff100000 @ mask 663 .word 0xf9000000 @ opcode 664 665 .word 0x00000000 @ mask 666 .word 0x00000000 @ opcode 667#endif 668 669do_fpe: 670 enable_irq 671 ldr r4, .LCfp 672 add r10, r10, #TI_FPSTATE @ r10 = workspace 673 ldr pc, [r4] @ Call FP module USR entry point 674 675/* 676 * The FP module is called with these registers set: 677 * r0 = instruction 678 * r2 = PC+4 679 * r9 = normal "successful" return address 680 * r10 = FP workspace 681 * lr = unrecognised FP instruction return address 682 */ 683 684 .data 685ENTRY(fp_enter) 686 .word no_fp 687 .previous 688 689ENTRY(no_fp) 690 mov pc, lr 691ENDPROC(no_fp) 692 693__und_usr_unknown: 694 enable_irq 695 mov r0, sp 696 adr lr, BSYM(ret_from_exception) 697 b do_undefinstr 698ENDPROC(__und_usr_unknown) 699 700 .align 5 701__pabt_usr: 702 usr_entry 703 704#ifdef MULTI_PABORT 705 mov r0, r2 @ pass address of aborted instruction. 706 ldr r4, .LCprocfns 707 mov lr, pc 708 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 709#else 710 CPU_PABORT_HANDLER(r0, r2) 711#endif 712 enable_irq @ Enable interrupts 713 mov r1, sp @ regs 714 bl do_PrefetchAbort @ call abort handler 715 UNWIND(.fnend ) 716 /* fall through */ 717/* 718 * This is the return code to user mode for abort handlers 719 */ 720ENTRY(ret_from_exception) 721 UNWIND(.fnstart ) 722 UNWIND(.cantunwind ) 723 get_thread_info tsk 724 mov why, #0 725 b ret_to_user 726 UNWIND(.fnend ) 727ENDPROC(__pabt_usr) 728ENDPROC(ret_from_exception) 729 730/* 731 * Register switch for ARMv3 and ARMv4 processors 732 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 733 * previous and next are guaranteed not to be the same. 734 */ 735ENTRY(__switch_to) 736 UNWIND(.fnstart ) 737 UNWIND(.cantunwind ) 738 add ip, r1, #TI_CPU_SAVE 739 ldr r3, [r2, #TI_TP_VALUE] 740 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 741 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 742 THUMB( str sp, [ip], #4 ) 743 THUMB( str lr, [ip], #4 ) 744#ifdef CONFIG_MMU 745 ldr r6, [r2, #TI_CPU_DOMAIN] 746#endif 747#if defined(CONFIG_HAS_TLS_REG) 748 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 749#elif !defined(CONFIG_TLS_REG_EMUL) 750 mov r4, #0xffff0fff 751 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 752#endif 753#ifdef CONFIG_MMU 754 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 755#endif 756 mov r5, r0 757 add r4, r2, #TI_CPU_SAVE 758 ldr r0, =thread_notify_head 759 mov r1, #THREAD_NOTIFY_SWITCH 760 bl atomic_notifier_call_chain 761 THUMB( mov ip, r4 ) 762 mov r0, r5 763 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 764 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 765 THUMB( ldr sp, [ip], #4 ) 766 THUMB( ldr pc, [ip] ) 767 UNWIND(.fnend ) 768ENDPROC(__switch_to) 769 770 __INIT 771 772/* 773 * User helpers. 774 * 775 * These are segment of kernel provided user code reachable from user space 776 * at a fixed address in kernel memory. This is used to provide user space 777 * with some operations which require kernel help because of unimplemented 778 * native feature and/or instructions in many ARM CPUs. The idea is for 779 * this code to be executed directly in user mode for best efficiency but 780 * which is too intimate with the kernel counter part to be left to user 781 * libraries. In fact this code might even differ from one CPU to another 782 * depending on the available instruction set and restrictions like on 783 * SMP systems. In other words, the kernel reserves the right to change 784 * this code as needed without warning. Only the entry points and their 785 * results are guaranteed to be stable. 786 * 787 * Each segment is 32-byte aligned and will be moved to the top of the high 788 * vector page. New segments (if ever needed) must be added in front of 789 * existing ones. This mechanism should be used only for things that are 790 * really small and justified, and not be abused freely. 791 * 792 * User space is expected to implement those things inline when optimizing 793 * for a processor that has the necessary native support, but only if such 794 * resulting binaries are already to be incompatible with earlier ARM 795 * processors due to the use of unsupported instructions other than what 796 * is provided here. In other words don't make binaries unable to run on 797 * earlier processors just for the sake of not using these kernel helpers 798 * if your compiled code is not going to use the new instructions for other 799 * purpose. 800 */ 801 THUMB( .arm ) 802 803 .macro usr_ret, reg 804#ifdef CONFIG_ARM_THUMB 805 bx \reg 806#else 807 mov pc, \reg 808#endif 809 .endm 810 811 .align 5 812 .globl __kuser_helper_start 813__kuser_helper_start: 814 815/* 816 * Reference prototype: 817 * 818 * void __kernel_memory_barrier(void) 819 * 820 * Input: 821 * 822 * lr = return address 823 * 824 * Output: 825 * 826 * none 827 * 828 * Clobbered: 829 * 830 * none 831 * 832 * Definition and user space usage example: 833 * 834 * typedef void (__kernel_dmb_t)(void); 835 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 836 * 837 * Apply any needed memory barrier to preserve consistency with data modified 838 * manually and __kuser_cmpxchg usage. 839 * 840 * This could be used as follows: 841 * 842 * #define __kernel_dmb() \ 843 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 844 * : : : "r0", "lr","cc" ) 845 */ 846 847__kuser_memory_barrier: @ 0xffff0fa0 848 smp_dmb 849 usr_ret lr 850 851 .align 5 852 853/* 854 * Reference prototype: 855 * 856 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 857 * 858 * Input: 859 * 860 * r0 = oldval 861 * r1 = newval 862 * r2 = ptr 863 * lr = return address 864 * 865 * Output: 866 * 867 * r0 = returned value (zero or non-zero) 868 * C flag = set if r0 == 0, clear if r0 != 0 869 * 870 * Clobbered: 871 * 872 * r3, ip, flags 873 * 874 * Definition and user space usage example: 875 * 876 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 877 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 878 * 879 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 880 * Return zero if *ptr was changed or non-zero if no exchange happened. 881 * The C flag is also set if *ptr was changed to allow for assembly 882 * optimization in the calling code. 883 * 884 * Notes: 885 * 886 * - This routine already includes memory barriers as needed. 887 * 888 * For example, a user space atomic_add implementation could look like this: 889 * 890 * #define atomic_add(ptr, val) \ 891 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 892 * register unsigned int __result asm("r1"); \ 893 * asm volatile ( \ 894 * "1: @ atomic_add\n\t" \ 895 * "ldr r0, [r2]\n\t" \ 896 * "mov r3, #0xffff0fff\n\t" \ 897 * "add lr, pc, #4\n\t" \ 898 * "add r1, r0, %2\n\t" \ 899 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 900 * "bcc 1b" \ 901 * : "=&r" (__result) \ 902 * : "r" (__ptr), "rIL" (val) \ 903 * : "r0","r3","ip","lr","cc","memory" ); \ 904 * __result; }) 905 */ 906 907__kuser_cmpxchg: @ 0xffff0fc0 908 909#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 910 911 /* 912 * Poor you. No fast solution possible... 913 * The kernel itself must perform the operation. 914 * A special ghost syscall is used for that (see traps.c). 915 */ 916 stmfd sp!, {r7, lr} 917 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 918 orr r7, r7, #0xf0 919 swi #0x9ffff0 920 ldmfd sp!, {r7, pc} 921 922#elif __LINUX_ARM_ARCH__ < 6 923 924#ifdef CONFIG_MMU 925 926 /* 927 * The only thing that can break atomicity in this cmpxchg 928 * implementation is either an IRQ or a data abort exception 929 * causing another process/thread to be scheduled in the middle 930 * of the critical sequence. To prevent this, code is added to 931 * the IRQ and data abort exception handlers to set the pc back 932 * to the beginning of the critical section if it is found to be 933 * within that critical section (see kuser_cmpxchg_fixup). 934 */ 9351: ldr r3, [r2] @ load current val 936 subs r3, r3, r0 @ compare with oldval 9372: streq r1, [r2] @ store newval if eq 938 rsbs r0, r3, #0 @ set return val and C flag 939 usr_ret lr 940 941 .text 942kuser_cmpxchg_fixup: 943 @ Called from kuser_cmpxchg_check macro. 944 @ r2 = address of interrupted insn (must be preserved). 945 @ sp = saved regs. r7 and r8 are clobbered. 946 @ 1b = first critical insn, 2b = last critical insn. 947 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. 948 mov r7, #0xffff0fff 949 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 950 subs r8, r2, r7 951 rsbcss r8, r8, #(2b - 1b) 952 strcs r7, [sp, #S_PC] 953 mov pc, lr 954 .previous 955 956#else 957#warning "NPTL on non MMU needs fixing" 958 mov r0, #-1 959 adds r0, r0, #0 960 usr_ret lr 961#endif 962 963#else 964 965#ifdef CONFIG_SMP 966 mcr p15, 0, r0, c7, c10, 5 @ dmb 967#endif 9681: ldrex r3, [r2] 969 subs r3, r3, r0 970 strexeq r3, r1, [r2] 971 teqeq r3, #1 972 beq 1b 973 rsbs r0, r3, #0 974 /* beware -- each __kuser slot must be 8 instructions max */ 975#ifdef CONFIG_SMP 976 b __kuser_memory_barrier 977#else 978 usr_ret lr 979#endif 980 981#endif 982 983 .align 5 984 985/* 986 * Reference prototype: 987 * 988 * int __kernel_get_tls(void) 989 * 990 * Input: 991 * 992 * lr = return address 993 * 994 * Output: 995 * 996 * r0 = TLS value 997 * 998 * Clobbered: 999 * 1000 * none 1001 * 1002 * Definition and user space usage example: 1003 * 1004 * typedef int (__kernel_get_tls_t)(void); 1005 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 1006 * 1007 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 1008 * 1009 * This could be used as follows: 1010 * 1011 * #define __kernel_get_tls() \ 1012 * ({ register unsigned int __val asm("r0"); \ 1013 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 1014 * : "=r" (__val) : : "lr","cc" ); \ 1015 * __val; }) 1016 */ 1017 1018__kuser_get_tls: @ 0xffff0fe0 1019 1020#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 1021 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 1022#else 1023 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 1024#endif 1025 usr_ret lr 1026 1027 .rep 5 1028 .word 0 @ pad up to __kuser_helper_version 1029 .endr 1030 1031/* 1032 * Reference declaration: 1033 * 1034 * extern unsigned int __kernel_helper_version; 1035 * 1036 * Definition and user space usage example: 1037 * 1038 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 1039 * 1040 * User space may read this to determine the curent number of helpers 1041 * available. 1042 */ 1043 1044__kuser_helper_version: @ 0xffff0ffc 1045 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1046 1047 .globl __kuser_helper_end 1048__kuser_helper_end: 1049 1050 THUMB( .thumb ) 1051 1052/* 1053 * Vector stubs. 1054 * 1055 * This code is copied to 0xffff0200 so we can use branches in the 1056 * vectors, rather than ldr's. Note that this code must not 1057 * exceed 0x300 bytes. 1058 * 1059 * Common stub entry macro: 1060 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1061 * 1062 * SP points to a minimal amount of processor-private memory, the address 1063 * of which is copied into r0 for the mode specific abort handler. 1064 */ 1065 .macro vector_stub, name, mode, correction=0 1066 .align 5 1067 1068vector_\name: 1069 .if \correction 1070 sub lr, lr, #\correction 1071 .endif 1072 1073 @ 1074 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1075 @ (parent CPSR) 1076 @ 1077 stmia sp, {r0, lr} @ save r0, lr 1078 mrs lr, spsr 1079 str lr, [sp, #8] @ save spsr 1080 1081 @ 1082 @ Prepare for SVC32 mode. IRQs remain disabled. 1083 @ 1084 mrs r0, cpsr 1085 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1086 msr spsr_cxsf, r0 1087 1088 @ 1089 @ the branch table must immediately follow this code 1090 @ 1091 and lr, lr, #0x0f 1092 THUMB( adr r0, 1f ) 1093 THUMB( ldr lr, [r0, lr, lsl #2] ) 1094 mov r0, sp 1095 ARM( ldr lr, [pc, lr, lsl #2] ) 1096 movs pc, lr @ branch to handler in SVC mode 1097ENDPROC(vector_\name) 1098 1099 .align 2 1100 @ handler addresses follow this label 11011: 1102 .endm 1103 1104 .globl __stubs_start 1105__stubs_start: 1106/* 1107 * Interrupt dispatcher 1108 */ 1109 vector_stub irq, IRQ_MODE, 4 1110 1111 .long __irq_usr @ 0 (USR_26 / USR_32) 1112 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1113 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1114 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1115 .long __irq_invalid @ 4 1116 .long __irq_invalid @ 5 1117 .long __irq_invalid @ 6 1118 .long __irq_invalid @ 7 1119 .long __irq_invalid @ 8 1120 .long __irq_invalid @ 9 1121 .long __irq_invalid @ a 1122 .long __irq_invalid @ b 1123 .long __irq_invalid @ c 1124 .long __irq_invalid @ d 1125 .long __irq_invalid @ e 1126 .long __irq_invalid @ f 1127 1128/* 1129 * Data abort dispatcher 1130 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1131 */ 1132 vector_stub dabt, ABT_MODE, 8 1133 1134 .long __dabt_usr @ 0 (USR_26 / USR_32) 1135 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1136 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1137 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1138 .long __dabt_invalid @ 4 1139 .long __dabt_invalid @ 5 1140 .long __dabt_invalid @ 6 1141 .long __dabt_invalid @ 7 1142 .long __dabt_invalid @ 8 1143 .long __dabt_invalid @ 9 1144 .long __dabt_invalid @ a 1145 .long __dabt_invalid @ b 1146 .long __dabt_invalid @ c 1147 .long __dabt_invalid @ d 1148 .long __dabt_invalid @ e 1149 .long __dabt_invalid @ f 1150 1151/* 1152 * Prefetch abort dispatcher 1153 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1154 */ 1155 vector_stub pabt, ABT_MODE, 4 1156 1157 .long __pabt_usr @ 0 (USR_26 / USR_32) 1158 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1159 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1160 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1161 .long __pabt_invalid @ 4 1162 .long __pabt_invalid @ 5 1163 .long __pabt_invalid @ 6 1164 .long __pabt_invalid @ 7 1165 .long __pabt_invalid @ 8 1166 .long __pabt_invalid @ 9 1167 .long __pabt_invalid @ a 1168 .long __pabt_invalid @ b 1169 .long __pabt_invalid @ c 1170 .long __pabt_invalid @ d 1171 .long __pabt_invalid @ e 1172 .long __pabt_invalid @ f 1173 1174/* 1175 * Undef instr entry dispatcher 1176 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1177 */ 1178 vector_stub und, UND_MODE 1179 1180 .long __und_usr @ 0 (USR_26 / USR_32) 1181 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1182 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1183 .long __und_svc @ 3 (SVC_26 / SVC_32) 1184 .long __und_invalid @ 4 1185 .long __und_invalid @ 5 1186 .long __und_invalid @ 6 1187 .long __und_invalid @ 7 1188 .long __und_invalid @ 8 1189 .long __und_invalid @ 9 1190 .long __und_invalid @ a 1191 .long __und_invalid @ b 1192 .long __und_invalid @ c 1193 .long __und_invalid @ d 1194 .long __und_invalid @ e 1195 .long __und_invalid @ f 1196 1197 .align 5 1198 1199/*============================================================================= 1200 * Undefined FIQs 1201 *----------------------------------------------------------------------------- 1202 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1203 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1204 * Basically to switch modes, we *HAVE* to clobber one register... brain 1205 * damage alert! I don't think that we can execute any code in here in any 1206 * other mode than FIQ... Ok you can switch to another mode, but you can't 1207 * get out of that mode without clobbering one register. 1208 */ 1209vector_fiq: 1210 disable_fiq 1211 subs pc, lr, #4 1212 1213/*============================================================================= 1214 * Address exception handler 1215 *----------------------------------------------------------------------------- 1216 * These aren't too critical. 1217 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1218 */ 1219 1220vector_addrexcptn: 1221 b vector_addrexcptn 1222 1223/* 1224 * We group all the following data together to optimise 1225 * for CPUs with separate I & D caches. 1226 */ 1227 .align 5 1228 1229.LCvswi: 1230 .word vector_swi 1231 1232 .globl __stubs_end 1233__stubs_end: 1234 1235 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1236 1237 .globl __vectors_start 1238__vectors_start: 1239 ARM( swi SYS_ERROR0 ) 1240 THUMB( svc #0 ) 1241 THUMB( nop ) 1242 W(b) vector_und + stubs_offset 1243 W(ldr) pc, .LCvswi + stubs_offset 1244 W(b) vector_pabt + stubs_offset 1245 W(b) vector_dabt + stubs_offset 1246 W(b) vector_addrexcptn + stubs_offset 1247 W(b) vector_irq + stubs_offset 1248 W(b) vector_fiq + stubs_offset 1249 1250 .globl __vectors_end 1251__vectors_end: 1252 1253 .data 1254 1255 .globl cr_alignment 1256 .globl cr_no_alignment 1257cr_alignment: 1258 .space 4 1259cr_no_alignment: 1260 .space 4 1261