1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <mach/entry-macro.S> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24 25#include "entry-header.S" 26 27/* 28 * Interrupt handling. Preserves r7, r8, r9 29 */ 30 .macro irq_handler 31 get_irqnr_preamble r5, lr 321: get_irqnr_and_base r0, r6, r5, lr 33 movne r1, sp 34 @ 35 @ routine called with r0 = irq number, r1 = struct pt_regs * 36 @ 37 adrne lr, 1b 38 bne asm_do_IRQ 39 40#ifdef CONFIG_SMP 41 /* 42 * XXX 43 * 44 * this macro assumes that irqstat (r6) and base (r5) are 45 * preserved from get_irqnr_and_base above 46 */ 47 test_for_ipi r0, r6, r5, lr 48 movne r0, sp 49 adrne lr, 1b 50 bne do_IPI 51 52#ifdef CONFIG_LOCAL_TIMERS 53 test_for_ltirq r0, r6, r5, lr 54 movne r0, sp 55 adrne lr, 1b 56 bne do_local_timer 57#endif 58#endif 59 60 .endm 61 62#ifdef CONFIG_KPROBES 63 .section .kprobes.text,"ax",%progbits 64#else 65 .text 66#endif 67 68/* 69 * Invalid mode handlers 70 */ 71 .macro inv_entry, reason 72 sub sp, sp, #S_FRAME_SIZE 73 stmib sp, {r1 - lr} 74 mov r1, #\reason 75 .endm 76 77__pabt_invalid: 78 inv_entry BAD_PREFETCH 79 b common_invalid 80ENDPROC(__pabt_invalid) 81 82__dabt_invalid: 83 inv_entry BAD_DATA 84 b common_invalid 85ENDPROC(__dabt_invalid) 86 87__irq_invalid: 88 inv_entry BAD_IRQ 89 b common_invalid 90ENDPROC(__irq_invalid) 91 92__und_invalid: 93 inv_entry BAD_UNDEFINSTR 94 95 @ 96 @ XXX fall through to common_invalid 97 @ 98 99@ 100@ common_invalid - generic code for failed exception (re-entrant version of handlers) 101@ 102common_invalid: 103 zero_fp 104 105 ldmia r0, {r4 - r6} 106 add r0, sp, #S_PC @ here for interlock avoidance 107 mov r7, #-1 @ "" "" "" "" 108 str r4, [sp] @ save preserved r0 109 stmia r0, {r5 - r7} @ lr_<exception>, 110 @ cpsr_<exception>, "old_r0" 111 112 mov r0, sp 113 b bad_mode 114ENDPROC(__und_invalid) 115 116/* 117 * SVC mode handlers 118 */ 119 120#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 121#define SPFIX(code...) code 122#else 123#define SPFIX(code...) 124#endif 125 126 .macro svc_entry, stack_hole=0 127 UNWIND(.fnstart ) 128 UNWIND(.save {r0 - pc} ) 129 sub sp, sp, #(S_FRAME_SIZE + \stack_hole) 130 SPFIX( tst sp, #4 ) 131 SPFIX( bicne sp, sp, #4 ) 132 stmib sp, {r1 - r12} 133 134 ldmia r0, {r1 - r3} 135 add r5, sp, #S_SP @ here for interlock avoidance 136 mov r4, #-1 @ "" "" "" "" 137 add r0, sp, #(S_FRAME_SIZE + \stack_hole) 138 SPFIX( addne r0, r0, #4 ) 139 str r1, [sp] @ save the "real" r0 copied 140 @ from the exception stack 141 142 mov r1, lr 143 144 @ 145 @ We are now ready to fill in the remaining blanks on the stack: 146 @ 147 @ r0 - sp_svc 148 @ r1 - lr_svc 149 @ r2 - lr_<exception>, already fixed up for correct return/restart 150 @ r3 - spsr_<exception> 151 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 152 @ 153 stmia r5, {r0 - r4} 154 .endm 155 156 .align 5 157__dabt_svc: 158 svc_entry 159 160 @ 161 @ get ready to re-enable interrupts if appropriate 162 @ 163 mrs r9, cpsr 164 tst r3, #PSR_I_BIT 165 biceq r9, r9, #PSR_I_BIT 166 167 @ 168 @ Call the processor-specific abort handler: 169 @ 170 @ r2 - aborted context pc 171 @ r3 - aborted context cpsr 172 @ 173 @ The abort handler must return the aborted address in r0, and 174 @ the fault status register in r1. r9 must be preserved. 175 @ 176#ifdef MULTI_DABORT 177 ldr r4, .LCprocfns 178 mov lr, pc 179 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 180#else 181 bl CPU_DABORT_HANDLER 182#endif 183 184 @ 185 @ set desired IRQ state, then call main handler 186 @ 187 msr cpsr_c, r9 188 mov r2, sp 189 bl do_DataAbort 190 191 @ 192 @ IRQs off again before pulling preserved data off the stack 193 @ 194 disable_irq 195 196 @ 197 @ restore SPSR and restart the instruction 198 @ 199 ldr r0, [sp, #S_PSR] 200 msr spsr_cxsf, r0 201 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 202 UNWIND(.fnend ) 203ENDPROC(__dabt_svc) 204 205 .align 5 206__irq_svc: 207 svc_entry 208 209#ifdef CONFIG_TRACE_IRQFLAGS 210 bl trace_hardirqs_off 211#endif 212#ifdef CONFIG_PREEMPT 213 get_thread_info tsk 214 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 215 add r7, r8, #1 @ increment it 216 str r7, [tsk, #TI_PREEMPT] 217#endif 218 219 irq_handler 220#ifdef CONFIG_PREEMPT 221 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 222 ldr r0, [tsk, #TI_FLAGS] @ get flags 223 teq r8, #0 @ if preempt count != 0 224 movne r0, #0 @ force flags to 0 225 tst r0, #_TIF_NEED_RESCHED 226 blne svc_preempt 227#endif 228 ldr r0, [sp, #S_PSR] @ irqs are already disabled 229 msr spsr_cxsf, r0 230#ifdef CONFIG_TRACE_IRQFLAGS 231 tst r0, #PSR_I_BIT 232 bleq trace_hardirqs_on 233#endif 234 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 235 UNWIND(.fnend ) 236ENDPROC(__irq_svc) 237 238 .ltorg 239 240#ifdef CONFIG_PREEMPT 241svc_preempt: 242 mov r8, lr 2431: bl preempt_schedule_irq @ irq en/disable is done inside 244 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 245 tst r0, #_TIF_NEED_RESCHED 246 moveq pc, r8 @ go again 247 b 1b 248#endif 249 250 .align 5 251__und_svc: 252#ifdef CONFIG_KPROBES 253 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 254 @ it obviously needs free stack space which then will belong to 255 @ the saved context. 256 svc_entry 64 257#else 258 svc_entry 259#endif 260 261 @ 262 @ call emulation code, which returns using r9 if it has emulated 263 @ the instruction, or the more conventional lr if we are to treat 264 @ this as a real undefined instruction 265 @ 266 @ r0 - instruction 267 @ 268 ldr r0, [r2, #-4] 269 adr r9, 1f 270 bl call_fpe 271 272 mov r0, sp @ struct pt_regs *regs 273 bl do_undefinstr 274 275 @ 276 @ IRQs off again before pulling preserved data off the stack 277 @ 2781: disable_irq 279 280 @ 281 @ restore SPSR and restart the instruction 282 @ 283 ldr lr, [sp, #S_PSR] @ Get SVC cpsr 284 msr spsr_cxsf, lr 285 ldmia sp, {r0 - pc}^ @ Restore SVC registers 286 UNWIND(.fnend ) 287ENDPROC(__und_svc) 288 289 .align 5 290__pabt_svc: 291 svc_entry 292 293 @ 294 @ re-enable interrupts if appropriate 295 @ 296 mrs r9, cpsr 297 tst r3, #PSR_I_BIT 298 biceq r9, r9, #PSR_I_BIT 299 300 @ 301 @ set args, then call main handler 302 @ 303 @ r0 - address of faulting instruction 304 @ r1 - pointer to registers on stack 305 @ 306#ifdef MULTI_PABORT 307 mov r0, r2 @ pass address of aborted instruction. 308 ldr r4, .LCprocfns 309 mov lr, pc 310 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 311#else 312 CPU_PABORT_HANDLER(r0, r2) 313#endif 314 msr cpsr_c, r9 @ Maybe enable interrupts 315 mov r1, sp @ regs 316 bl do_PrefetchAbort @ call abort handler 317 318 @ 319 @ IRQs off again before pulling preserved data off the stack 320 @ 321 disable_irq 322 323 @ 324 @ restore SPSR and restart the instruction 325 @ 326 ldr r0, [sp, #S_PSR] 327 msr spsr_cxsf, r0 328 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 329 UNWIND(.fnend ) 330ENDPROC(__pabt_svc) 331 332 .align 5 333.LCcralign: 334 .word cr_alignment 335#ifdef MULTI_DABORT 336.LCprocfns: 337 .word processor 338#endif 339.LCfp: 340 .word fp_enter 341 342/* 343 * User mode handlers 344 * 345 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 346 */ 347 348#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 349#error "sizeof(struct pt_regs) must be a multiple of 8" 350#endif 351 352 .macro usr_entry 353 UNWIND(.fnstart ) 354 UNWIND(.cantunwind ) @ don't unwind the user space 355 sub sp, sp, #S_FRAME_SIZE 356 stmib sp, {r1 - r12} 357 358 ldmia r0, {r1 - r3} 359 add r0, sp, #S_PC @ here for interlock avoidance 360 mov r4, #-1 @ "" "" "" "" 361 362 str r1, [sp] @ save the "real" r0 copied 363 @ from the exception stack 364 365 @ 366 @ We are now ready to fill in the remaining blanks on the stack: 367 @ 368 @ r2 - lr_<exception>, already fixed up for correct return/restart 369 @ r3 - spsr_<exception> 370 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 371 @ 372 @ Also, separately save sp_usr and lr_usr 373 @ 374 stmia r0, {r2 - r4} 375 stmdb r0, {sp, lr}^ 376 377 @ 378 @ Enable the alignment trap while in kernel mode 379 @ 380 alignment_trap r0 381 382 @ 383 @ Clear FP to mark the first stack frame 384 @ 385 zero_fp 386 .endm 387 388 .macro kuser_cmpxchg_check 389#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 390#ifndef CONFIG_MMU 391#warning "NPTL on non MMU needs fixing" 392#else 393 @ Make sure our user space atomic helper is restarted 394 @ if it was interrupted in a critical region. Here we 395 @ perform a quick test inline since it should be false 396 @ 99.9999% of the time. The rest is done out of line. 397 cmp r2, #TASK_SIZE 398 blhs kuser_cmpxchg_fixup 399#endif 400#endif 401 .endm 402 403 .align 5 404__dabt_usr: 405 usr_entry 406 kuser_cmpxchg_check 407 408 @ 409 @ Call the processor-specific abort handler: 410 @ 411 @ r2 - aborted context pc 412 @ r3 - aborted context cpsr 413 @ 414 @ The abort handler must return the aborted address in r0, and 415 @ the fault status register in r1. 416 @ 417#ifdef MULTI_DABORT 418 ldr r4, .LCprocfns 419 mov lr, pc 420 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 421#else 422 bl CPU_DABORT_HANDLER 423#endif 424 425 @ 426 @ IRQs on, then call the main handler 427 @ 428 enable_irq 429 mov r2, sp 430 adr lr, ret_from_exception 431 b do_DataAbort 432 UNWIND(.fnend ) 433ENDPROC(__dabt_usr) 434 435 .align 5 436__irq_usr: 437 usr_entry 438 kuser_cmpxchg_check 439 440#ifdef CONFIG_TRACE_IRQFLAGS 441 bl trace_hardirqs_off 442#endif 443 get_thread_info tsk 444#ifdef CONFIG_PREEMPT 445 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 446 add r7, r8, #1 @ increment it 447 str r7, [tsk, #TI_PREEMPT] 448#endif 449 450 irq_handler 451#ifdef CONFIG_PREEMPT 452 ldr r0, [tsk, #TI_PREEMPT] 453 str r8, [tsk, #TI_PREEMPT] 454 teq r0, r7 455 strne r0, [r0, -r0] 456#endif 457#ifdef CONFIG_TRACE_IRQFLAGS 458 bl trace_hardirqs_on 459#endif 460 461 mov why, #0 462 b ret_to_user 463 UNWIND(.fnend ) 464ENDPROC(__irq_usr) 465 466 .ltorg 467 468 .align 5 469__und_usr: 470 usr_entry 471 472 @ 473 @ fall through to the emulation code, which returns using r9 if 474 @ it has emulated the instruction, or the more conventional lr 475 @ if we are to treat this as a real undefined instruction 476 @ 477 @ r0 - instruction 478 @ 479 adr r9, ret_from_exception 480 adr lr, __und_usr_unknown 481 tst r3, #PSR_T_BIT @ Thumb mode? 482 subeq r4, r2, #4 @ ARM instr at LR - 4 483 subne r4, r2, #2 @ Thumb instr at LR - 2 4841: ldreqt r0, [r4] 485#ifdef CONFIG_CPU_ENDIAN_BE8 486 reveq r0, r0 @ little endian instruction 487#endif 488 beq call_fpe 489 @ Thumb instruction 490#if __LINUX_ARM_ARCH__ >= 7 4912: ldrht r5, [r4], #2 492 and r0, r5, #0xf800 @ mask bits 111x x... .... .... 493 cmp r0, #0xe800 @ 32bit instruction if xx != 0 494 blo __und_usr_unknown 4953: ldrht r0, [r4] 496 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 497 orr r0, r0, r5, lsl #16 498#else 499 b __und_usr_unknown 500#endif 501 UNWIND(.fnend ) 502ENDPROC(__und_usr) 503 504 @ 505 @ fallthrough to call_fpe 506 @ 507 508/* 509 * The out of line fixup for the ldrt above. 510 */ 511 .section .fixup, "ax" 5124: mov pc, r9 513 .previous 514 .section __ex_table,"a" 515 .long 1b, 4b 516#if __LINUX_ARM_ARCH__ >= 7 517 .long 2b, 4b 518 .long 3b, 4b 519#endif 520 .previous 521 522/* 523 * Check whether the instruction is a co-processor instruction. 524 * If yes, we need to call the relevant co-processor handler. 525 * 526 * Note that we don't do a full check here for the co-processor 527 * instructions; all instructions with bit 27 set are well 528 * defined. The only instructions that should fault are the 529 * co-processor instructions. However, we have to watch out 530 * for the ARM6/ARM7 SWI bug. 531 * 532 * NEON is a special case that has to be handled here. Not all 533 * NEON instructions are co-processor instructions, so we have 534 * to make a special case of checking for them. Plus, there's 535 * five groups of them, so we have a table of mask/opcode pairs 536 * to check against, and if any match then we branch off into the 537 * NEON handler code. 538 * 539 * Emulators may wish to make use of the following registers: 540 * r0 = instruction opcode. 541 * r2 = PC+4 542 * r9 = normal "successful" return address 543 * r10 = this threads thread_info structure. 544 * lr = unrecognised instruction return address 545 */ 546 @ 547 @ Fall-through from Thumb-2 __und_usr 548 @ 549#ifdef CONFIG_NEON 550 adr r6, .LCneon_thumb_opcodes 551 b 2f 552#endif 553call_fpe: 554#ifdef CONFIG_NEON 555 adr r6, .LCneon_arm_opcodes 5562: 557 ldr r7, [r6], #4 @ mask value 558 cmp r7, #0 @ end mask? 559 beq 1f 560 and r8, r0, r7 561 ldr r7, [r6], #4 @ opcode bits matching in mask 562 cmp r8, r7 @ NEON instruction? 563 bne 2b 564 get_thread_info r10 565 mov r7, #1 566 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 567 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 568 b do_vfp @ let VFP handler handle this 5691: 570#endif 571 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 572 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 573#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 574 and r8, r0, #0x0f000000 @ mask out op-code bits 575 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 576#endif 577 moveq pc, lr 578 get_thread_info r10 @ get current thread 579 and r8, r0, #0x00000f00 @ mask out CP number 580 mov r7, #1 581 add r6, r10, #TI_USED_CP 582 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] 583#ifdef CONFIG_IWMMXT 584 @ Test if we need to give access to iWMMXt coprocessors 585 ldr r5, [r10, #TI_FLAGS] 586 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 587 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 588 bcs iwmmxt_task_enable 589#endif 590 add pc, pc, r8, lsr #6 591 mov r0, r0 592 593 mov pc, lr @ CP#0 594 b do_fpe @ CP#1 (FPE) 595 b do_fpe @ CP#2 (FPE) 596 mov pc, lr @ CP#3 597#ifdef CONFIG_CRUNCH 598 b crunch_task_enable @ CP#4 (MaverickCrunch) 599 b crunch_task_enable @ CP#5 (MaverickCrunch) 600 b crunch_task_enable @ CP#6 (MaverickCrunch) 601#else 602 mov pc, lr @ CP#4 603 mov pc, lr @ CP#5 604 mov pc, lr @ CP#6 605#endif 606 mov pc, lr @ CP#7 607 mov pc, lr @ CP#8 608 mov pc, lr @ CP#9 609#ifdef CONFIG_VFP 610 b do_vfp @ CP#10 (VFP) 611 b do_vfp @ CP#11 (VFP) 612#else 613 mov pc, lr @ CP#10 (VFP) 614 mov pc, lr @ CP#11 (VFP) 615#endif 616 mov pc, lr @ CP#12 617 mov pc, lr @ CP#13 618 mov pc, lr @ CP#14 (Debug) 619 mov pc, lr @ CP#15 (Control) 620 621#ifdef CONFIG_NEON 622 .align 6 623 624.LCneon_arm_opcodes: 625 .word 0xfe000000 @ mask 626 .word 0xf2000000 @ opcode 627 628 .word 0xff100000 @ mask 629 .word 0xf4000000 @ opcode 630 631 .word 0x00000000 @ mask 632 .word 0x00000000 @ opcode 633 634.LCneon_thumb_opcodes: 635 .word 0xef000000 @ mask 636 .word 0xef000000 @ opcode 637 638 .word 0xff100000 @ mask 639 .word 0xf9000000 @ opcode 640 641 .word 0x00000000 @ mask 642 .word 0x00000000 @ opcode 643#endif 644 645do_fpe: 646 enable_irq 647 ldr r4, .LCfp 648 add r10, r10, #TI_FPSTATE @ r10 = workspace 649 ldr pc, [r4] @ Call FP module USR entry point 650 651/* 652 * The FP module is called with these registers set: 653 * r0 = instruction 654 * r2 = PC+4 655 * r9 = normal "successful" return address 656 * r10 = FP workspace 657 * lr = unrecognised FP instruction return address 658 */ 659 660 .data 661ENTRY(fp_enter) 662 .word no_fp 663 .previous 664 665no_fp: mov pc, lr 666 667__und_usr_unknown: 668 enable_irq 669 mov r0, sp 670 adr lr, ret_from_exception 671 b do_undefinstr 672ENDPROC(__und_usr_unknown) 673 674 .align 5 675__pabt_usr: 676 usr_entry 677 678#ifdef MULTI_PABORT 679 mov r0, r2 @ pass address of aborted instruction. 680 ldr r4, .LCprocfns 681 mov lr, pc 682 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 683#else 684 CPU_PABORT_HANDLER(r0, r2) 685#endif 686 enable_irq @ Enable interrupts 687 mov r1, sp @ regs 688 bl do_PrefetchAbort @ call abort handler 689 UNWIND(.fnend ) 690 /* fall through */ 691/* 692 * This is the return code to user mode for abort handlers 693 */ 694ENTRY(ret_from_exception) 695 UNWIND(.fnstart ) 696 UNWIND(.cantunwind ) 697 get_thread_info tsk 698 mov why, #0 699 b ret_to_user 700 UNWIND(.fnend ) 701ENDPROC(__pabt_usr) 702ENDPROC(ret_from_exception) 703 704/* 705 * Register switch for ARMv3 and ARMv4 processors 706 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 707 * previous and next are guaranteed not to be the same. 708 */ 709ENTRY(__switch_to) 710 UNWIND(.fnstart ) 711 UNWIND(.cantunwind ) 712 add ip, r1, #TI_CPU_SAVE 713 ldr r3, [r2, #TI_TP_VALUE] 714 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack 715#ifdef CONFIG_MMU 716 ldr r6, [r2, #TI_CPU_DOMAIN] 717#endif 718#if __LINUX_ARM_ARCH__ >= 6 719#ifdef CONFIG_CPU_32v6K 720 clrex 721#else 722 strex r5, r4, [ip] @ Clear exclusive monitor 723#endif 724#endif 725#if defined(CONFIG_HAS_TLS_REG) 726 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 727#elif !defined(CONFIG_TLS_REG_EMUL) 728 mov r4, #0xffff0fff 729 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 730#endif 731#ifdef CONFIG_MMU 732 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 733#endif 734 mov r5, r0 735 add r4, r2, #TI_CPU_SAVE 736 ldr r0, =thread_notify_head 737 mov r1, #THREAD_NOTIFY_SWITCH 738 bl atomic_notifier_call_chain 739 mov r0, r5 740 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 741 UNWIND(.fnend ) 742ENDPROC(__switch_to) 743 744 __INIT 745 746/* 747 * User helpers. 748 * 749 * These are segment of kernel provided user code reachable from user space 750 * at a fixed address in kernel memory. This is used to provide user space 751 * with some operations which require kernel help because of unimplemented 752 * native feature and/or instructions in many ARM CPUs. The idea is for 753 * this code to be executed directly in user mode for best efficiency but 754 * which is too intimate with the kernel counter part to be left to user 755 * libraries. In fact this code might even differ from one CPU to another 756 * depending on the available instruction set and restrictions like on 757 * SMP systems. In other words, the kernel reserves the right to change 758 * this code as needed without warning. Only the entry points and their 759 * results are guaranteed to be stable. 760 * 761 * Each segment is 32-byte aligned and will be moved to the top of the high 762 * vector page. New segments (if ever needed) must be added in front of 763 * existing ones. This mechanism should be used only for things that are 764 * really small and justified, and not be abused freely. 765 * 766 * User space is expected to implement those things inline when optimizing 767 * for a processor that has the necessary native support, but only if such 768 * resulting binaries are already to be incompatible with earlier ARM 769 * processors due to the use of unsupported instructions other than what 770 * is provided here. In other words don't make binaries unable to run on 771 * earlier processors just for the sake of not using these kernel helpers 772 * if your compiled code is not going to use the new instructions for other 773 * purpose. 774 */ 775 776 .macro usr_ret, reg 777#ifdef CONFIG_ARM_THUMB 778 bx \reg 779#else 780 mov pc, \reg 781#endif 782 .endm 783 784 .align 5 785 .globl __kuser_helper_start 786__kuser_helper_start: 787 788/* 789 * Reference prototype: 790 * 791 * void __kernel_memory_barrier(void) 792 * 793 * Input: 794 * 795 * lr = return address 796 * 797 * Output: 798 * 799 * none 800 * 801 * Clobbered: 802 * 803 * none 804 * 805 * Definition and user space usage example: 806 * 807 * typedef void (__kernel_dmb_t)(void); 808 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 809 * 810 * Apply any needed memory barrier to preserve consistency with data modified 811 * manually and __kuser_cmpxchg usage. 812 * 813 * This could be used as follows: 814 * 815 * #define __kernel_dmb() \ 816 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 817 * : : : "r0", "lr","cc" ) 818 */ 819 820__kuser_memory_barrier: @ 0xffff0fa0 821 822#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) 823 mcr p15, 0, r0, c7, c10, 5 @ dmb 824#endif 825 usr_ret lr 826 827 .align 5 828 829/* 830 * Reference prototype: 831 * 832 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 833 * 834 * Input: 835 * 836 * r0 = oldval 837 * r1 = newval 838 * r2 = ptr 839 * lr = return address 840 * 841 * Output: 842 * 843 * r0 = returned value (zero or non-zero) 844 * C flag = set if r0 == 0, clear if r0 != 0 845 * 846 * Clobbered: 847 * 848 * r3, ip, flags 849 * 850 * Definition and user space usage example: 851 * 852 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 853 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 854 * 855 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 856 * Return zero if *ptr was changed or non-zero if no exchange happened. 857 * The C flag is also set if *ptr was changed to allow for assembly 858 * optimization in the calling code. 859 * 860 * Notes: 861 * 862 * - This routine already includes memory barriers as needed. 863 * 864 * For example, a user space atomic_add implementation could look like this: 865 * 866 * #define atomic_add(ptr, val) \ 867 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 868 * register unsigned int __result asm("r1"); \ 869 * asm volatile ( \ 870 * "1: @ atomic_add\n\t" \ 871 * "ldr r0, [r2]\n\t" \ 872 * "mov r3, #0xffff0fff\n\t" \ 873 * "add lr, pc, #4\n\t" \ 874 * "add r1, r0, %2\n\t" \ 875 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 876 * "bcc 1b" \ 877 * : "=&r" (__result) \ 878 * : "r" (__ptr), "rIL" (val) \ 879 * : "r0","r3","ip","lr","cc","memory" ); \ 880 * __result; }) 881 */ 882 883__kuser_cmpxchg: @ 0xffff0fc0 884 885#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 886 887 /* 888 * Poor you. No fast solution possible... 889 * The kernel itself must perform the operation. 890 * A special ghost syscall is used for that (see traps.c). 891 */ 892 stmfd sp!, {r7, lr} 893 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 894 orr r7, r7, #0xf0 895 swi #0x9ffff0 896 ldmfd sp!, {r7, pc} 897 898#elif __LINUX_ARM_ARCH__ < 6 899 900#ifdef CONFIG_MMU 901 902 /* 903 * The only thing that can break atomicity in this cmpxchg 904 * implementation is either an IRQ or a data abort exception 905 * causing another process/thread to be scheduled in the middle 906 * of the critical sequence. To prevent this, code is added to 907 * the IRQ and data abort exception handlers to set the pc back 908 * to the beginning of the critical section if it is found to be 909 * within that critical section (see kuser_cmpxchg_fixup). 910 */ 9111: ldr r3, [r2] @ load current val 912 subs r3, r3, r0 @ compare with oldval 9132: streq r1, [r2] @ store newval if eq 914 rsbs r0, r3, #0 @ set return val and C flag 915 usr_ret lr 916 917 .text 918kuser_cmpxchg_fixup: 919 @ Called from kuser_cmpxchg_check macro. 920 @ r2 = address of interrupted insn (must be preserved). 921 @ sp = saved regs. r7 and r8 are clobbered. 922 @ 1b = first critical insn, 2b = last critical insn. 923 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. 924 mov r7, #0xffff0fff 925 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 926 subs r8, r2, r7 927 rsbcss r8, r8, #(2b - 1b) 928 strcs r7, [sp, #S_PC] 929 mov pc, lr 930 .previous 931 932#else 933#warning "NPTL on non MMU needs fixing" 934 mov r0, #-1 935 adds r0, r0, #0 936 usr_ret lr 937#endif 938 939#else 940 941#ifdef CONFIG_SMP 942 mcr p15, 0, r0, c7, c10, 5 @ dmb 943#endif 9441: ldrex r3, [r2] 945 subs r3, r3, r0 946 strexeq r3, r1, [r2] 947 teqeq r3, #1 948 beq 1b 949 rsbs r0, r3, #0 950 /* beware -- each __kuser slot must be 8 instructions max */ 951#ifdef CONFIG_SMP 952 b __kuser_memory_barrier 953#else 954 usr_ret lr 955#endif 956 957#endif 958 959 .align 5 960 961/* 962 * Reference prototype: 963 * 964 * int __kernel_get_tls(void) 965 * 966 * Input: 967 * 968 * lr = return address 969 * 970 * Output: 971 * 972 * r0 = TLS value 973 * 974 * Clobbered: 975 * 976 * none 977 * 978 * Definition and user space usage example: 979 * 980 * typedef int (__kernel_get_tls_t)(void); 981 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 982 * 983 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 984 * 985 * This could be used as follows: 986 * 987 * #define __kernel_get_tls() \ 988 * ({ register unsigned int __val asm("r0"); \ 989 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 990 * : "=r" (__val) : : "lr","cc" ); \ 991 * __val; }) 992 */ 993 994__kuser_get_tls: @ 0xffff0fe0 995 996#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 997 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 998#else 999 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 1000#endif 1001 usr_ret lr 1002 1003 .rep 5 1004 .word 0 @ pad up to __kuser_helper_version 1005 .endr 1006 1007/* 1008 * Reference declaration: 1009 * 1010 * extern unsigned int __kernel_helper_version; 1011 * 1012 * Definition and user space usage example: 1013 * 1014 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 1015 * 1016 * User space may read this to determine the curent number of helpers 1017 * available. 1018 */ 1019 1020__kuser_helper_version: @ 0xffff0ffc 1021 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1022 1023 .globl __kuser_helper_end 1024__kuser_helper_end: 1025 1026 1027/* 1028 * Vector stubs. 1029 * 1030 * This code is copied to 0xffff0200 so we can use branches in the 1031 * vectors, rather than ldr's. Note that this code must not 1032 * exceed 0x300 bytes. 1033 * 1034 * Common stub entry macro: 1035 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1036 * 1037 * SP points to a minimal amount of processor-private memory, the address 1038 * of which is copied into r0 for the mode specific abort handler. 1039 */ 1040 .macro vector_stub, name, mode, correction=0 1041 .align 5 1042 1043vector_\name: 1044 .if \correction 1045 sub lr, lr, #\correction 1046 .endif 1047 1048 @ 1049 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1050 @ (parent CPSR) 1051 @ 1052 stmia sp, {r0, lr} @ save r0, lr 1053 mrs lr, spsr 1054 str lr, [sp, #8] @ save spsr 1055 1056 @ 1057 @ Prepare for SVC32 mode. IRQs remain disabled. 1058 @ 1059 mrs r0, cpsr 1060 eor r0, r0, #(\mode ^ SVC_MODE) 1061 msr spsr_cxsf, r0 1062 1063 @ 1064 @ the branch table must immediately follow this code 1065 @ 1066 and lr, lr, #0x0f 1067 mov r0, sp 1068 ldr lr, [pc, lr, lsl #2] 1069 movs pc, lr @ branch to handler in SVC mode 1070ENDPROC(vector_\name) 1071 .endm 1072 1073 .globl __stubs_start 1074__stubs_start: 1075/* 1076 * Interrupt dispatcher 1077 */ 1078 vector_stub irq, IRQ_MODE, 4 1079 1080 .long __irq_usr @ 0 (USR_26 / USR_32) 1081 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1082 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1083 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1084 .long __irq_invalid @ 4 1085 .long __irq_invalid @ 5 1086 .long __irq_invalid @ 6 1087 .long __irq_invalid @ 7 1088 .long __irq_invalid @ 8 1089 .long __irq_invalid @ 9 1090 .long __irq_invalid @ a 1091 .long __irq_invalid @ b 1092 .long __irq_invalid @ c 1093 .long __irq_invalid @ d 1094 .long __irq_invalid @ e 1095 .long __irq_invalid @ f 1096 1097/* 1098 * Data abort dispatcher 1099 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1100 */ 1101 vector_stub dabt, ABT_MODE, 8 1102 1103 .long __dabt_usr @ 0 (USR_26 / USR_32) 1104 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1105 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1106 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1107 .long __dabt_invalid @ 4 1108 .long __dabt_invalid @ 5 1109 .long __dabt_invalid @ 6 1110 .long __dabt_invalid @ 7 1111 .long __dabt_invalid @ 8 1112 .long __dabt_invalid @ 9 1113 .long __dabt_invalid @ a 1114 .long __dabt_invalid @ b 1115 .long __dabt_invalid @ c 1116 .long __dabt_invalid @ d 1117 .long __dabt_invalid @ e 1118 .long __dabt_invalid @ f 1119 1120/* 1121 * Prefetch abort dispatcher 1122 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1123 */ 1124 vector_stub pabt, ABT_MODE, 4 1125 1126 .long __pabt_usr @ 0 (USR_26 / USR_32) 1127 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1128 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1129 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1130 .long __pabt_invalid @ 4 1131 .long __pabt_invalid @ 5 1132 .long __pabt_invalid @ 6 1133 .long __pabt_invalid @ 7 1134 .long __pabt_invalid @ 8 1135 .long __pabt_invalid @ 9 1136 .long __pabt_invalid @ a 1137 .long __pabt_invalid @ b 1138 .long __pabt_invalid @ c 1139 .long __pabt_invalid @ d 1140 .long __pabt_invalid @ e 1141 .long __pabt_invalid @ f 1142 1143/* 1144 * Undef instr entry dispatcher 1145 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1146 */ 1147 vector_stub und, UND_MODE 1148 1149 .long __und_usr @ 0 (USR_26 / USR_32) 1150 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1151 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1152 .long __und_svc @ 3 (SVC_26 / SVC_32) 1153 .long __und_invalid @ 4 1154 .long __und_invalid @ 5 1155 .long __und_invalid @ 6 1156 .long __und_invalid @ 7 1157 .long __und_invalid @ 8 1158 .long __und_invalid @ 9 1159 .long __und_invalid @ a 1160 .long __und_invalid @ b 1161 .long __und_invalid @ c 1162 .long __und_invalid @ d 1163 .long __und_invalid @ e 1164 .long __und_invalid @ f 1165 1166 .align 5 1167 1168/*============================================================================= 1169 * Undefined FIQs 1170 *----------------------------------------------------------------------------- 1171 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1172 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1173 * Basically to switch modes, we *HAVE* to clobber one register... brain 1174 * damage alert! I don't think that we can execute any code in here in any 1175 * other mode than FIQ... Ok you can switch to another mode, but you can't 1176 * get out of that mode without clobbering one register. 1177 */ 1178vector_fiq: 1179 disable_fiq 1180 subs pc, lr, #4 1181 1182/*============================================================================= 1183 * Address exception handler 1184 *----------------------------------------------------------------------------- 1185 * These aren't too critical. 1186 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1187 */ 1188 1189vector_addrexcptn: 1190 b vector_addrexcptn 1191 1192/* 1193 * We group all the following data together to optimise 1194 * for CPUs with separate I & D caches. 1195 */ 1196 .align 5 1197 1198.LCvswi: 1199 .word vector_swi 1200 1201 .globl __stubs_end 1202__stubs_end: 1203 1204 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1205 1206 .globl __vectors_start 1207__vectors_start: 1208 swi SYS_ERROR0 1209 b vector_und + stubs_offset 1210 ldr pc, .LCvswi + stubs_offset 1211 b vector_pabt + stubs_offset 1212 b vector_dabt + stubs_offset 1213 b vector_addrexcptn + stubs_offset 1214 b vector_irq + stubs_offset 1215 b vector_fiq + stubs_offset 1216 1217 .globl __vectors_end 1218__vectors_end: 1219 1220 .data 1221 1222 .globl cr_alignment 1223 .globl cr_no_alignment 1224cr_alignment: 1225 .space 4 1226cr_no_alignment: 1227 .space 4 1228