1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/assembler.h> 19#include <asm/memory.h> 20#include <asm/glue-df.h> 21#include <asm/glue-pf.h> 22#include <asm/vfpmacros.h> 23#ifndef CONFIG_MULTI_IRQ_HANDLER 24#include <mach/entry-macro.S> 25#endif 26#include <asm/thread_notify.h> 27#include <asm/unwind.h> 28#include <asm/unistd.h> 29#include <asm/tls.h> 30#include <asm/system_info.h> 31 32#include "entry-header.S" 33#include <asm/entry-macro-multi.S> 34 35/* 36 * Interrupt handling. 37 */ 38 .macro irq_handler 39#ifdef CONFIG_MULTI_IRQ_HANDLER 40 ldr r1, =handle_arch_irq 41 mov r0, sp 42 adr lr, BSYM(9997f) 43 ldr pc, [r1] 44#else 45 arch_irq_handler_default 46#endif 479997: 48 .endm 49 50 .macro pabt_helper 51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 52#ifdef MULTI_PABORT 53 ldr ip, .LCprocfns 54 mov lr, pc 55 ldr pc, [ip, #PROCESSOR_PABT_FUNC] 56#else 57 bl CPU_PABORT_HANDLER 58#endif 59 .endm 60 61 .macro dabt_helper 62 63 @ 64 @ Call the processor-specific abort handler: 65 @ 66 @ r2 - pt_regs 67 @ r4 - aborted context pc 68 @ r5 - aborted context psr 69 @ 70 @ The abort handler must return the aborted address in r0, and 71 @ the fault status register in r1. r9 must be preserved. 72 @ 73#ifdef MULTI_DABORT 74 ldr ip, .LCprocfns 75 mov lr, pc 76 ldr pc, [ip, #PROCESSOR_DABT_FUNC] 77#else 78 bl CPU_DABORT_HANDLER 79#endif 80 .endm 81 82#ifdef CONFIG_KPROBES 83 .section .kprobes.text,"ax",%progbits 84#else 85 .text 86#endif 87 88/* 89 * Invalid mode handlers 90 */ 91 .macro inv_entry, reason 92 sub sp, sp, #S_FRAME_SIZE 93 ARM( stmib sp, {r1 - lr} ) 94 THUMB( stmia sp, {r0 - r12} ) 95 THUMB( str sp, [sp, #S_SP] ) 96 THUMB( str lr, [sp, #S_LR] ) 97 mov r1, #\reason 98 .endm 99 100__pabt_invalid: 101 inv_entry BAD_PREFETCH 102 b common_invalid 103ENDPROC(__pabt_invalid) 104 105__dabt_invalid: 106 inv_entry BAD_DATA 107 b common_invalid 108ENDPROC(__dabt_invalid) 109 110__irq_invalid: 111 inv_entry BAD_IRQ 112 b common_invalid 113ENDPROC(__irq_invalid) 114 115__und_invalid: 116 inv_entry BAD_UNDEFINSTR 117 118 @ 119 @ XXX fall through to common_invalid 120 @ 121 122@ 123@ common_invalid - generic code for failed exception (re-entrant version of handlers) 124@ 125common_invalid: 126 zero_fp 127 128 ldmia r0, {r4 - r6} 129 add r0, sp, #S_PC @ here for interlock avoidance 130 mov r7, #-1 @ "" "" "" "" 131 str r4, [sp] @ save preserved r0 132 stmia r0, {r5 - r7} @ lr_<exception>, 133 @ cpsr_<exception>, "old_r0" 134 135 mov r0, sp 136 b bad_mode 137ENDPROC(__und_invalid) 138 139/* 140 * SVC mode handlers 141 */ 142 143#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 144#define SPFIX(code...) code 145#else 146#define SPFIX(code...) 147#endif 148 149 .macro svc_entry, stack_hole=0 150 UNWIND(.fnstart ) 151 UNWIND(.save {r0 - pc} ) 152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 153#ifdef CONFIG_THUMB2_KERNEL 154 SPFIX( str r0, [sp] ) @ temporarily saved 155 SPFIX( mov r0, sp ) 156 SPFIX( tst r0, #4 ) @ test original stack alignment 157 SPFIX( ldr r0, [sp] ) @ restored 158#else 159 SPFIX( tst sp, #4 ) 160#endif 161 SPFIX( subeq sp, sp, #4 ) 162 stmia sp, {r1 - r12} 163 164 ldmia r0, {r3 - r5} 165 add r7, sp, #S_SP - 4 @ here for interlock avoidance 166 mov r6, #-1 @ "" "" "" "" 167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) 168 SPFIX( addeq r2, r2, #4 ) 169 str r3, [sp, #-4]! @ save the "real" r0 copied 170 @ from the exception stack 171 172 mov r3, lr 173 174 @ 175 @ We are now ready to fill in the remaining blanks on the stack: 176 @ 177 @ r2 - sp_svc 178 @ r3 - lr_svc 179 @ r4 - lr_<exception>, already fixed up for correct return/restart 180 @ r5 - spsr_<exception> 181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 182 @ 183 stmia r7, {r2 - r6} 184 185#ifdef CONFIG_TRACE_IRQFLAGS 186 bl trace_hardirqs_off 187#endif 188 .endm 189 190 .align 5 191__dabt_svc: 192 svc_entry 193 mov r2, sp 194 dabt_helper 195 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR 196 svc_exit r5 @ return from exception 197 UNWIND(.fnend ) 198ENDPROC(__dabt_svc) 199 200 .align 5 201__irq_svc: 202 svc_entry 203 irq_handler 204 205#ifdef CONFIG_PREEMPT 206 get_thread_info tsk 207 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 208 ldr r0, [tsk, #TI_FLAGS] @ get flags 209 teq r8, #0 @ if preempt count != 0 210 movne r0, #0 @ force flags to 0 211 tst r0, #_TIF_NEED_RESCHED 212 blne svc_preempt 213#endif 214 215 svc_exit r5, irq = 1 @ return from exception 216 UNWIND(.fnend ) 217ENDPROC(__irq_svc) 218 219 .ltorg 220 221#ifdef CONFIG_PREEMPT 222svc_preempt: 223 mov r8, lr 2241: bl preempt_schedule_irq @ irq en/disable is done inside 225 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 226 tst r0, #_TIF_NEED_RESCHED 227 reteq r8 @ go again 228 b 1b 229#endif 230 231__und_fault: 232 @ Correct the PC such that it is pointing at the instruction 233 @ which caused the fault. If the faulting instruction was ARM 234 @ the PC will be pointing at the next instruction, and have to 235 @ subtract 4. Otherwise, it is Thumb, and the PC will be 236 @ pointing at the second half of the Thumb instruction. We 237 @ have to subtract 2. 238 ldr r2, [r0, #S_PC] 239 sub r2, r2, r1 240 str r2, [r0, #S_PC] 241 b do_undefinstr 242ENDPROC(__und_fault) 243 244 .align 5 245__und_svc: 246#ifdef CONFIG_KPROBES 247 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 248 @ it obviously needs free stack space which then will belong to 249 @ the saved context. 250 svc_entry 64 251#else 252 svc_entry 253#endif 254 @ 255 @ call emulation code, which returns using r9 if it has emulated 256 @ the instruction, or the more conventional lr if we are to treat 257 @ this as a real undefined instruction 258 @ 259 @ r0 - instruction 260 @ 261#ifndef CONFIG_THUMB2_KERNEL 262 ldr r0, [r4, #-4] 263#else 264 mov r1, #2 265 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 266 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 267 blo __und_svc_fault 268 ldrh r9, [r4] @ bottom 16 bits 269 add r4, r4, #2 270 str r4, [sp, #S_PC] 271 orr r0, r9, r0, lsl #16 272#endif 273 adr r9, BSYM(__und_svc_finish) 274 mov r2, r4 275 bl call_fpe 276 277 mov r1, #4 @ PC correction to apply 278__und_svc_fault: 279 mov r0, sp @ struct pt_regs *regs 280 bl __und_fault 281 282__und_svc_finish: 283 ldr r5, [sp, #S_PSR] @ Get SVC cpsr 284 svc_exit r5 @ return from exception 285 UNWIND(.fnend ) 286ENDPROC(__und_svc) 287 288 .align 5 289__pabt_svc: 290 svc_entry 291 mov r2, sp @ regs 292 pabt_helper 293 svc_exit r5 @ return from exception 294 UNWIND(.fnend ) 295ENDPROC(__pabt_svc) 296 297 .align 5 298.LCcralign: 299 .word cr_alignment 300#ifdef MULTI_DABORT 301.LCprocfns: 302 .word processor 303#endif 304.LCfp: 305 .word fp_enter 306 307/* 308 * User mode handlers 309 * 310 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 311 */ 312 313#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 314#error "sizeof(struct pt_regs) must be a multiple of 8" 315#endif 316 317 .macro usr_entry 318 UNWIND(.fnstart ) 319 UNWIND(.cantunwind ) @ don't unwind the user space 320 sub sp, sp, #S_FRAME_SIZE 321 ARM( stmib sp, {r1 - r12} ) 322 THUMB( stmia sp, {r0 - r12} ) 323 324 ATRAP( mrc p15, 0, r7, c1, c0, 0) 325 ATRAP( ldr r8, .LCcralign) 326 327 ldmia r0, {r3 - r5} 328 add r0, sp, #S_PC @ here for interlock avoidance 329 mov r6, #-1 @ "" "" "" "" 330 331 str r3, [sp] @ save the "real" r0 copied 332 @ from the exception stack 333 334 ATRAP( ldr r8, [r8, #0]) 335 336 @ 337 @ We are now ready to fill in the remaining blanks on the stack: 338 @ 339 @ r4 - lr_<exception>, already fixed up for correct return/restart 340 @ r5 - spsr_<exception> 341 @ r6 - orig_r0 (see pt_regs definition in ptrace.h) 342 @ 343 @ Also, separately save sp_usr and lr_usr 344 @ 345 stmia r0, {r4 - r6} 346 ARM( stmdb r0, {sp, lr}^ ) 347 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 348 349 @ Enable the alignment trap while in kernel mode 350 ATRAP( teq r8, r7) 351 ATRAP( mcrne p15, 0, r8, c1, c0, 0) 352 353 @ 354 @ Clear FP to mark the first stack frame 355 @ 356 zero_fp 357 358#ifdef CONFIG_IRQSOFF_TRACER 359 bl trace_hardirqs_off 360#endif 361 ct_user_exit save = 0 362 .endm 363 364 .macro kuser_cmpxchg_check 365#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \ 366 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 367#ifndef CONFIG_MMU 368#warning "NPTL on non MMU needs fixing" 369#else 370 @ Make sure our user space atomic helper is restarted 371 @ if it was interrupted in a critical region. Here we 372 @ perform a quick test inline since it should be false 373 @ 99.9999% of the time. The rest is done out of line. 374 cmp r4, #TASK_SIZE 375 blhs kuser_cmpxchg64_fixup 376#endif 377#endif 378 .endm 379 380 .align 5 381__dabt_usr: 382 usr_entry 383 kuser_cmpxchg_check 384 mov r2, sp 385 dabt_helper 386 b ret_from_exception 387 UNWIND(.fnend ) 388ENDPROC(__dabt_usr) 389 390 .align 5 391__irq_usr: 392 usr_entry 393 kuser_cmpxchg_check 394 irq_handler 395 get_thread_info tsk 396 mov why, #0 397 b ret_to_user_from_irq 398 UNWIND(.fnend ) 399ENDPROC(__irq_usr) 400 401 .ltorg 402 403 .align 5 404__und_usr: 405 usr_entry 406 407 mov r2, r4 408 mov r3, r5 409 410 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the 411 @ faulting instruction depending on Thumb mode. 412 @ r3 = regs->ARM_cpsr 413 @ 414 @ The emulation code returns using r9 if it has emulated the 415 @ instruction, or the more conventional lr if we are to treat 416 @ this as a real undefined instruction 417 @ 418 adr r9, BSYM(ret_from_exception) 419 420 @ IRQs must be enabled before attempting to read the instruction from 421 @ user space since that could cause a page/translation fault if the 422 @ page table was modified by another CPU. 423 enable_irq 424 425 tst r3, #PSR_T_BIT @ Thumb mode? 426 bne __und_usr_thumb 427 sub r4, r2, #4 @ ARM instr at LR - 4 4281: ldrt r0, [r4] 429 ARM_BE8(rev r0, r0) @ little endian instruction 430 431 @ r0 = 32-bit ARM instruction which caused the exception 432 @ r2 = PC value for the following instruction (:= regs->ARM_pc) 433 @ r4 = PC value for the faulting instruction 434 @ lr = 32-bit undefined instruction function 435 adr lr, BSYM(__und_usr_fault_32) 436 b call_fpe 437 438__und_usr_thumb: 439 @ Thumb instruction 440 sub r4, r2, #2 @ First half of thumb instr at LR - 2 441#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 442/* 443 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms 444 * can never be supported in a single kernel, this code is not applicable at 445 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be 446 * made about .arch directives. 447 */ 448#if __LINUX_ARM_ARCH__ < 7 449/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ 450#define NEED_CPU_ARCHITECTURE 451 ldr r5, .LCcpu_architecture 452 ldr r5, [r5] 453 cmp r5, #CPU_ARCH_ARMv7 454 blo __und_usr_fault_16 @ 16bit undefined instruction 455/* 456 * The following code won't get run unless the running CPU really is v7, so 457 * coding round the lack of ldrht on older arches is pointless. Temporarily 458 * override the assembler target arch with the minimum required instead: 459 */ 460 .arch armv6t2 461#endif 4622: ldrht r5, [r4] 463ARM_BE8(rev16 r5, r5) @ little endian instruction 464 cmp r5, #0xe800 @ 32bit instruction if xx != 0 465 blo __und_usr_fault_16 @ 16bit undefined instruction 4663: ldrht r0, [r2] 467ARM_BE8(rev16 r0, r0) @ little endian instruction 468 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 469 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update 470 orr r0, r0, r5, lsl #16 471 adr lr, BSYM(__und_usr_fault_32) 472 @ r0 = the two 16-bit Thumb instructions which caused the exception 473 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) 474 @ r4 = PC value for the first 16-bit Thumb instruction 475 @ lr = 32bit undefined instruction function 476 477#if __LINUX_ARM_ARCH__ < 7 478/* If the target arch was overridden, change it back: */ 479#ifdef CONFIG_CPU_32v6K 480 .arch armv6k 481#else 482 .arch armv6 483#endif 484#endif /* __LINUX_ARM_ARCH__ < 7 */ 485#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ 486 b __und_usr_fault_16 487#endif 488 UNWIND(.fnend) 489ENDPROC(__und_usr) 490 491/* 492 * The out of line fixup for the ldrt instructions above. 493 */ 494 .pushsection .fixup, "ax" 495 .align 2 4964: str r4, [sp, #S_PC] @ retry current instruction 497 ret r9 498 .popsection 499 .pushsection __ex_table,"a" 500 .long 1b, 4b 501#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 502 .long 2b, 4b 503 .long 3b, 4b 504#endif 505 .popsection 506 507/* 508 * Check whether the instruction is a co-processor instruction. 509 * If yes, we need to call the relevant co-processor handler. 510 * 511 * Note that we don't do a full check here for the co-processor 512 * instructions; all instructions with bit 27 set are well 513 * defined. The only instructions that should fault are the 514 * co-processor instructions. However, we have to watch out 515 * for the ARM6/ARM7 SWI bug. 516 * 517 * NEON is a special case that has to be handled here. Not all 518 * NEON instructions are co-processor instructions, so we have 519 * to make a special case of checking for them. Plus, there's 520 * five groups of them, so we have a table of mask/opcode pairs 521 * to check against, and if any match then we branch off into the 522 * NEON handler code. 523 * 524 * Emulators may wish to make use of the following registers: 525 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 526 * r2 = PC value to resume execution after successful emulation 527 * r9 = normal "successful" return address 528 * r10 = this threads thread_info structure 529 * lr = unrecognised instruction return address 530 * IRQs enabled, FIQs enabled. 531 */ 532 @ 533 @ Fall-through from Thumb-2 __und_usr 534 @ 535#ifdef CONFIG_NEON 536 get_thread_info r10 @ get current thread 537 adr r6, .LCneon_thumb_opcodes 538 b 2f 539#endif 540call_fpe: 541 get_thread_info r10 @ get current thread 542#ifdef CONFIG_NEON 543 adr r6, .LCneon_arm_opcodes 5442: ldr r5, [r6], #4 @ mask value 545 ldr r7, [r6], #4 @ opcode bits matching in mask 546 cmp r5, #0 @ end mask? 547 beq 1f 548 and r8, r0, r5 549 cmp r8, r7 @ NEON instruction? 550 bne 2b 551 mov r7, #1 552 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 553 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 554 b do_vfp @ let VFP handler handle this 5551: 556#endif 557 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 558 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 559 reteq lr 560 and r8, r0, #0x00000f00 @ mask out CP number 561 THUMB( lsr r8, r8, #8 ) 562 mov r7, #1 563 add r6, r10, #TI_USED_CP 564 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 565 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 566#ifdef CONFIG_IWMMXT 567 @ Test if we need to give access to iWMMXt coprocessors 568 ldr r5, [r10, #TI_FLAGS] 569 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 570 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 571 bcs iwmmxt_task_enable 572#endif 573 ARM( add pc, pc, r8, lsr #6 ) 574 THUMB( lsl r8, r8, #2 ) 575 THUMB( add pc, r8 ) 576 nop 577 578 ret.w lr @ CP#0 579 W(b) do_fpe @ CP#1 (FPE) 580 W(b) do_fpe @ CP#2 (FPE) 581 ret.w lr @ CP#3 582#ifdef CONFIG_CRUNCH 583 b crunch_task_enable @ CP#4 (MaverickCrunch) 584 b crunch_task_enable @ CP#5 (MaverickCrunch) 585 b crunch_task_enable @ CP#6 (MaverickCrunch) 586#else 587 ret.w lr @ CP#4 588 ret.w lr @ CP#5 589 ret.w lr @ CP#6 590#endif 591 ret.w lr @ CP#7 592 ret.w lr @ CP#8 593 ret.w lr @ CP#9 594#ifdef CONFIG_VFP 595 W(b) do_vfp @ CP#10 (VFP) 596 W(b) do_vfp @ CP#11 (VFP) 597#else 598 ret.w lr @ CP#10 (VFP) 599 ret.w lr @ CP#11 (VFP) 600#endif 601 ret.w lr @ CP#12 602 ret.w lr @ CP#13 603 ret.w lr @ CP#14 (Debug) 604 ret.w lr @ CP#15 (Control) 605 606#ifdef NEED_CPU_ARCHITECTURE 607 .align 2 608.LCcpu_architecture: 609 .word __cpu_architecture 610#endif 611 612#ifdef CONFIG_NEON 613 .align 6 614 615.LCneon_arm_opcodes: 616 .word 0xfe000000 @ mask 617 .word 0xf2000000 @ opcode 618 619 .word 0xff100000 @ mask 620 .word 0xf4000000 @ opcode 621 622 .word 0x00000000 @ mask 623 .word 0x00000000 @ opcode 624 625.LCneon_thumb_opcodes: 626 .word 0xef000000 @ mask 627 .word 0xef000000 @ opcode 628 629 .word 0xff100000 @ mask 630 .word 0xf9000000 @ opcode 631 632 .word 0x00000000 @ mask 633 .word 0x00000000 @ opcode 634#endif 635 636do_fpe: 637 ldr r4, .LCfp 638 add r10, r10, #TI_FPSTATE @ r10 = workspace 639 ldr pc, [r4] @ Call FP module USR entry point 640 641/* 642 * The FP module is called with these registers set: 643 * r0 = instruction 644 * r2 = PC+4 645 * r9 = normal "successful" return address 646 * r10 = FP workspace 647 * lr = unrecognised FP instruction return address 648 */ 649 650 .pushsection .data 651ENTRY(fp_enter) 652 .word no_fp 653 .popsection 654 655ENTRY(no_fp) 656 ret lr 657ENDPROC(no_fp) 658 659__und_usr_fault_32: 660 mov r1, #4 661 b 1f 662__und_usr_fault_16: 663 mov r1, #2 6641: mov r0, sp 665 adr lr, BSYM(ret_from_exception) 666 b __und_fault 667ENDPROC(__und_usr_fault_32) 668ENDPROC(__und_usr_fault_16) 669 670 .align 5 671__pabt_usr: 672 usr_entry 673 mov r2, sp @ regs 674 pabt_helper 675 UNWIND(.fnend ) 676 /* fall through */ 677/* 678 * This is the return code to user mode for abort handlers 679 */ 680ENTRY(ret_from_exception) 681 UNWIND(.fnstart ) 682 UNWIND(.cantunwind ) 683 get_thread_info tsk 684 mov why, #0 685 b ret_to_user 686 UNWIND(.fnend ) 687ENDPROC(__pabt_usr) 688ENDPROC(ret_from_exception) 689 690/* 691 * Register switch for ARMv3 and ARMv4 processors 692 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 693 * previous and next are guaranteed not to be the same. 694 */ 695ENTRY(__switch_to) 696 UNWIND(.fnstart ) 697 UNWIND(.cantunwind ) 698 add ip, r1, #TI_CPU_SAVE 699 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 700 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 701 THUMB( str sp, [ip], #4 ) 702 THUMB( str lr, [ip], #4 ) 703 ldr r4, [r2, #TI_TP_VALUE] 704 ldr r5, [r2, #TI_TP_VALUE + 4] 705#ifdef CONFIG_CPU_USE_DOMAINS 706 ldr r6, [r2, #TI_CPU_DOMAIN] 707#endif 708 switch_tls r1, r4, r5, r3, r7 709#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 710 ldr r7, [r2, #TI_TASK] 711 ldr r8, =__stack_chk_guard 712 ldr r7, [r7, #TSK_STACK_CANARY] 713#endif 714#ifdef CONFIG_CPU_USE_DOMAINS 715 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 716#endif 717 mov r5, r0 718 add r4, r2, #TI_CPU_SAVE 719 ldr r0, =thread_notify_head 720 mov r1, #THREAD_NOTIFY_SWITCH 721 bl atomic_notifier_call_chain 722#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 723 str r7, [r8] 724#endif 725 THUMB( mov ip, r4 ) 726 mov r0, r5 727 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 728 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 729 THUMB( ldr sp, [ip], #4 ) 730 THUMB( ldr pc, [ip] ) 731 UNWIND(.fnend ) 732ENDPROC(__switch_to) 733 734 __INIT 735 736/* 737 * User helpers. 738 * 739 * Each segment is 32-byte aligned and will be moved to the top of the high 740 * vector page. New segments (if ever needed) must be added in front of 741 * existing ones. This mechanism should be used only for things that are 742 * really small and justified, and not be abused freely. 743 * 744 * See Documentation/arm/kernel_user_helpers.txt for formal definitions. 745 */ 746 THUMB( .arm ) 747 748 .macro usr_ret, reg 749#ifdef CONFIG_ARM_THUMB 750 bx \reg 751#else 752 ret \reg 753#endif 754 .endm 755 756 .macro kuser_pad, sym, size 757 .if (. - \sym) & 3 758 .rept 4 - (. - \sym) & 3 759 .byte 0 760 .endr 761 .endif 762 .rept (\size - (. - \sym)) / 4 763 .word 0xe7fddef1 764 .endr 765 .endm 766 767#ifdef CONFIG_KUSER_HELPERS 768 .align 5 769 .globl __kuser_helper_start 770__kuser_helper_start: 771 772/* 773 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular 774 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. 775 */ 776 777__kuser_cmpxchg64: @ 0xffff0f60 778 779#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 780 781 /* 782 * Poor you. No fast solution possible... 783 * The kernel itself must perform the operation. 784 * A special ghost syscall is used for that (see traps.c). 785 */ 786 stmfd sp!, {r7, lr} 787 ldr r7, 1f @ it's 20 bits 788 swi __ARM_NR_cmpxchg64 789 ldmfd sp!, {r7, pc} 7901: .word __ARM_NR_cmpxchg64 791 792#elif defined(CONFIG_CPU_32v6K) 793 794 stmfd sp!, {r4, r5, r6, r7} 795 ldrd r4, r5, [r0] @ load old val 796 ldrd r6, r7, [r1] @ load new val 797 smp_dmb arm 7981: ldrexd r0, r1, [r2] @ load current val 799 eors r3, r0, r4 @ compare with oldval (1) 800 eoreqs r3, r1, r5 @ compare with oldval (2) 801 strexdeq r3, r6, r7, [r2] @ store newval if eq 802 teqeq r3, #1 @ success? 803 beq 1b @ if no then retry 804 smp_dmb arm 805 rsbs r0, r3, #0 @ set returned val and C flag 806 ldmfd sp!, {r4, r5, r6, r7} 807 usr_ret lr 808 809#elif !defined(CONFIG_SMP) 810 811#ifdef CONFIG_MMU 812 813 /* 814 * The only thing that can break atomicity in this cmpxchg64 815 * implementation is either an IRQ or a data abort exception 816 * causing another process/thread to be scheduled in the middle of 817 * the critical sequence. The same strategy as for cmpxchg is used. 818 */ 819 stmfd sp!, {r4, r5, r6, lr} 820 ldmia r0, {r4, r5} @ load old val 821 ldmia r1, {r6, lr} @ load new val 8221: ldmia r2, {r0, r1} @ load current val 823 eors r3, r0, r4 @ compare with oldval (1) 824 eoreqs r3, r1, r5 @ compare with oldval (2) 8252: stmeqia r2, {r6, lr} @ store newval if eq 826 rsbs r0, r3, #0 @ set return val and C flag 827 ldmfd sp!, {r4, r5, r6, pc} 828 829 .text 830kuser_cmpxchg64_fixup: 831 @ Called from kuser_cmpxchg_fixup. 832 @ r4 = address of interrupted insn (must be preserved). 833 @ sp = saved regs. r7 and r8 are clobbered. 834 @ 1b = first critical insn, 2b = last critical insn. 835 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 836 mov r7, #0xffff0fff 837 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 838 subs r8, r4, r7 839 rsbcss r8, r8, #(2b - 1b) 840 strcs r7, [sp, #S_PC] 841#if __LINUX_ARM_ARCH__ < 6 842 bcc kuser_cmpxchg32_fixup 843#endif 844 ret lr 845 .previous 846 847#else 848#warning "NPTL on non MMU needs fixing" 849 mov r0, #-1 850 adds r0, r0, #0 851 usr_ret lr 852#endif 853 854#else 855#error "incoherent kernel configuration" 856#endif 857 858 kuser_pad __kuser_cmpxchg64, 64 859 860__kuser_memory_barrier: @ 0xffff0fa0 861 smp_dmb arm 862 usr_ret lr 863 864 kuser_pad __kuser_memory_barrier, 32 865 866__kuser_cmpxchg: @ 0xffff0fc0 867 868#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 869 870 /* 871 * Poor you. No fast solution possible... 872 * The kernel itself must perform the operation. 873 * A special ghost syscall is used for that (see traps.c). 874 */ 875 stmfd sp!, {r7, lr} 876 ldr r7, 1f @ it's 20 bits 877 swi __ARM_NR_cmpxchg 878 ldmfd sp!, {r7, pc} 8791: .word __ARM_NR_cmpxchg 880 881#elif __LINUX_ARM_ARCH__ < 6 882 883#ifdef CONFIG_MMU 884 885 /* 886 * The only thing that can break atomicity in this cmpxchg 887 * implementation is either an IRQ or a data abort exception 888 * causing another process/thread to be scheduled in the middle 889 * of the critical sequence. To prevent this, code is added to 890 * the IRQ and data abort exception handlers to set the pc back 891 * to the beginning of the critical section if it is found to be 892 * within that critical section (see kuser_cmpxchg_fixup). 893 */ 8941: ldr r3, [r2] @ load current val 895 subs r3, r3, r0 @ compare with oldval 8962: streq r1, [r2] @ store newval if eq 897 rsbs r0, r3, #0 @ set return val and C flag 898 usr_ret lr 899 900 .text 901kuser_cmpxchg32_fixup: 902 @ Called from kuser_cmpxchg_check macro. 903 @ r4 = address of interrupted insn (must be preserved). 904 @ sp = saved regs. r7 and r8 are clobbered. 905 @ 1b = first critical insn, 2b = last critical insn. 906 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. 907 mov r7, #0xffff0fff 908 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 909 subs r8, r4, r7 910 rsbcss r8, r8, #(2b - 1b) 911 strcs r7, [sp, #S_PC] 912 ret lr 913 .previous 914 915#else 916#warning "NPTL on non MMU needs fixing" 917 mov r0, #-1 918 adds r0, r0, #0 919 usr_ret lr 920#endif 921 922#else 923 924 smp_dmb arm 9251: ldrex r3, [r2] 926 subs r3, r3, r0 927 strexeq r3, r1, [r2] 928 teqeq r3, #1 929 beq 1b 930 rsbs r0, r3, #0 931 /* beware -- each __kuser slot must be 8 instructions max */ 932 ALT_SMP(b __kuser_memory_barrier) 933 ALT_UP(usr_ret lr) 934 935#endif 936 937 kuser_pad __kuser_cmpxchg, 32 938 939__kuser_get_tls: @ 0xffff0fe0 940 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 941 usr_ret lr 942 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 943 kuser_pad __kuser_get_tls, 16 944 .rep 3 945 .word 0 @ 0xffff0ff0 software TLS value, then 946 .endr @ pad up to __kuser_helper_version 947 948__kuser_helper_version: @ 0xffff0ffc 949 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 950 951 .globl __kuser_helper_end 952__kuser_helper_end: 953 954#endif 955 956 THUMB( .thumb ) 957 958/* 959 * Vector stubs. 960 * 961 * This code is copied to 0xffff1000 so we can use branches in the 962 * vectors, rather than ldr's. Note that this code must not exceed 963 * a page size. 964 * 965 * Common stub entry macro: 966 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 967 * 968 * SP points to a minimal amount of processor-private memory, the address 969 * of which is copied into r0 for the mode specific abort handler. 970 */ 971 .macro vector_stub, name, mode, correction=0 972 .align 5 973 974vector_\name: 975 .if \correction 976 sub lr, lr, #\correction 977 .endif 978 979 @ 980 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 981 @ (parent CPSR) 982 @ 983 stmia sp, {r0, lr} @ save r0, lr 984 mrs lr, spsr 985 str lr, [sp, #8] @ save spsr 986 987 @ 988 @ Prepare for SVC32 mode. IRQs remain disabled. 989 @ 990 mrs r0, cpsr 991 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 992 msr spsr_cxsf, r0 993 994 @ 995 @ the branch table must immediately follow this code 996 @ 997 and lr, lr, #0x0f 998 THUMB( adr r0, 1f ) 999 THUMB( ldr lr, [r0, lr, lsl #2] ) 1000 mov r0, sp 1001 ARM( ldr lr, [pc, lr, lsl #2] ) 1002 movs pc, lr @ branch to handler in SVC mode 1003ENDPROC(vector_\name) 1004 1005 .align 2 1006 @ handler addresses follow this label 10071: 1008 .endm 1009 1010 .section .stubs, "ax", %progbits 1011__stubs_start: 1012 @ This must be the first word 1013 .word vector_swi 1014 1015vector_rst: 1016 ARM( swi SYS_ERROR0 ) 1017 THUMB( svc #0 ) 1018 THUMB( nop ) 1019 b vector_und 1020 1021/* 1022 * Interrupt dispatcher 1023 */ 1024 vector_stub irq, IRQ_MODE, 4 1025 1026 .long __irq_usr @ 0 (USR_26 / USR_32) 1027 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1028 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1029 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1030 .long __irq_invalid @ 4 1031 .long __irq_invalid @ 5 1032 .long __irq_invalid @ 6 1033 .long __irq_invalid @ 7 1034 .long __irq_invalid @ 8 1035 .long __irq_invalid @ 9 1036 .long __irq_invalid @ a 1037 .long __irq_invalid @ b 1038 .long __irq_invalid @ c 1039 .long __irq_invalid @ d 1040 .long __irq_invalid @ e 1041 .long __irq_invalid @ f 1042 1043/* 1044 * Data abort dispatcher 1045 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1046 */ 1047 vector_stub dabt, ABT_MODE, 8 1048 1049 .long __dabt_usr @ 0 (USR_26 / USR_32) 1050 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1051 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1052 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1053 .long __dabt_invalid @ 4 1054 .long __dabt_invalid @ 5 1055 .long __dabt_invalid @ 6 1056 .long __dabt_invalid @ 7 1057 .long __dabt_invalid @ 8 1058 .long __dabt_invalid @ 9 1059 .long __dabt_invalid @ a 1060 .long __dabt_invalid @ b 1061 .long __dabt_invalid @ c 1062 .long __dabt_invalid @ d 1063 .long __dabt_invalid @ e 1064 .long __dabt_invalid @ f 1065 1066/* 1067 * Prefetch abort dispatcher 1068 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1069 */ 1070 vector_stub pabt, ABT_MODE, 4 1071 1072 .long __pabt_usr @ 0 (USR_26 / USR_32) 1073 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1074 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1075 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1076 .long __pabt_invalid @ 4 1077 .long __pabt_invalid @ 5 1078 .long __pabt_invalid @ 6 1079 .long __pabt_invalid @ 7 1080 .long __pabt_invalid @ 8 1081 .long __pabt_invalid @ 9 1082 .long __pabt_invalid @ a 1083 .long __pabt_invalid @ b 1084 .long __pabt_invalid @ c 1085 .long __pabt_invalid @ d 1086 .long __pabt_invalid @ e 1087 .long __pabt_invalid @ f 1088 1089/* 1090 * Undef instr entry dispatcher 1091 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1092 */ 1093 vector_stub und, UND_MODE 1094 1095 .long __und_usr @ 0 (USR_26 / USR_32) 1096 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1097 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1098 .long __und_svc @ 3 (SVC_26 / SVC_32) 1099 .long __und_invalid @ 4 1100 .long __und_invalid @ 5 1101 .long __und_invalid @ 6 1102 .long __und_invalid @ 7 1103 .long __und_invalid @ 8 1104 .long __und_invalid @ 9 1105 .long __und_invalid @ a 1106 .long __und_invalid @ b 1107 .long __und_invalid @ c 1108 .long __und_invalid @ d 1109 .long __und_invalid @ e 1110 .long __und_invalid @ f 1111 1112 .align 5 1113 1114/*============================================================================= 1115 * Address exception handler 1116 *----------------------------------------------------------------------------- 1117 * These aren't too critical. 1118 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1119 */ 1120 1121vector_addrexcptn: 1122 b vector_addrexcptn 1123 1124/*============================================================================= 1125 * Undefined FIQs 1126 *----------------------------------------------------------------------------- 1127 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1128 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1129 * Basically to switch modes, we *HAVE* to clobber one register... brain 1130 * damage alert! I don't think that we can execute any code in here in any 1131 * other mode than FIQ... Ok you can switch to another mode, but you can't 1132 * get out of that mode without clobbering one register. 1133 */ 1134vector_fiq: 1135 subs pc, lr, #4 1136 1137 .globl vector_fiq_offset 1138 .equ vector_fiq_offset, vector_fiq 1139 1140 .section .vectors, "ax", %progbits 1141__vectors_start: 1142 W(b) vector_rst 1143 W(b) vector_und 1144 W(ldr) pc, __vectors_start + 0x1000 1145 W(b) vector_pabt 1146 W(b) vector_dabt 1147 W(b) vector_addrexcptn 1148 W(b) vector_irq 1149 W(b) vector_fiq 1150 1151 .data 1152 1153 .globl cr_alignment 1154cr_alignment: 1155 .space 4 1156 1157#ifdef CONFIG_MULTI_IRQ_HANDLER 1158 .globl handle_arch_irq 1159handle_arch_irq: 1160 .space 4 1161#endif 1162