1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 15 * that causes it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <mach/entry-macro.S> 22#include <asm/thread_notify.h> 23#include <asm/unwind.h> 24#include <asm/unistd.h> 25#include <asm/tls.h> 26 27#include "entry-header.S" 28 29/* 30 * Interrupt handling. Preserves r7, r8, r9 31 */ 32 .macro irq_handler 33 get_irqnr_preamble r5, lr 341: get_irqnr_and_base r0, r6, r5, lr 35 movne r1, sp 36 @ 37 @ routine called with r0 = irq number, r1 = struct pt_regs * 38 @ 39 adrne lr, BSYM(1b) 40 bne asm_do_IRQ 41 42#ifdef CONFIG_SMP 43 /* 44 * XXX 45 * 46 * this macro assumes that irqstat (r6) and base (r5) are 47 * preserved from get_irqnr_and_base above 48 */ 49 ALT_SMP(test_for_ipi r0, r6, r5, lr) 50 ALT_UP_B(9997f) 51 movne r0, sp 52 adrne lr, BSYM(1b) 53 bne do_IPI 54 55#ifdef CONFIG_LOCAL_TIMERS 56 test_for_ltirq r0, r6, r5, lr 57 movne r0, sp 58 adrne lr, BSYM(1b) 59 bne do_local_timer 60#endif 619997: 62#endif 63 64 .endm 65 66#ifdef CONFIG_KPROBES 67 .section .kprobes.text,"ax",%progbits 68#else 69 .text 70#endif 71 72/* 73 * Invalid mode handlers 74 */ 75 .macro inv_entry, reason 76 sub sp, sp, #S_FRAME_SIZE 77 ARM( stmib sp, {r1 - lr} ) 78 THUMB( stmia sp, {r0 - r12} ) 79 THUMB( str sp, [sp, #S_SP] ) 80 THUMB( str lr, [sp, #S_LR] ) 81 mov r1, #\reason 82 .endm 83 84__pabt_invalid: 85 inv_entry BAD_PREFETCH 86 b common_invalid 87ENDPROC(__pabt_invalid) 88 89__dabt_invalid: 90 inv_entry BAD_DATA 91 b common_invalid 92ENDPROC(__dabt_invalid) 93 94__irq_invalid: 95 inv_entry BAD_IRQ 96 b common_invalid 97ENDPROC(__irq_invalid) 98 99__und_invalid: 100 inv_entry BAD_UNDEFINSTR 101 102 @ 103 @ XXX fall through to common_invalid 104 @ 105 106@ 107@ common_invalid - generic code for failed exception (re-entrant version of handlers) 108@ 109common_invalid: 110 zero_fp 111 112 ldmia r0, {r4 - r6} 113 add r0, sp, #S_PC @ here for interlock avoidance 114 mov r7, #-1 @ "" "" "" "" 115 str r4, [sp] @ save preserved r0 116 stmia r0, {r5 - r7} @ lr_<exception>, 117 @ cpsr_<exception>, "old_r0" 118 119 mov r0, sp 120 b bad_mode 121ENDPROC(__und_invalid) 122 123/* 124 * SVC mode handlers 125 */ 126 127#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 128#define SPFIX(code...) code 129#else 130#define SPFIX(code...) 131#endif 132 133 .macro svc_entry, stack_hole=0 134 UNWIND(.fnstart ) 135 UNWIND(.save {r0 - pc} ) 136 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 137#ifdef CONFIG_THUMB2_KERNEL 138 SPFIX( str r0, [sp] ) @ temporarily saved 139 SPFIX( mov r0, sp ) 140 SPFIX( tst r0, #4 ) @ test original stack alignment 141 SPFIX( ldr r0, [sp] ) @ restored 142#else 143 SPFIX( tst sp, #4 ) 144#endif 145 SPFIX( subeq sp, sp, #4 ) 146 stmia sp, {r1 - r12} 147 148 ldmia r0, {r1 - r3} 149 add r5, sp, #S_SP - 4 @ here for interlock avoidance 150 mov r4, #-1 @ "" "" "" "" 151 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4) 152 SPFIX( addeq r0, r0, #4 ) 153 str r1, [sp, #-4]! @ save the "real" r0 copied 154 @ from the exception stack 155 156 mov r1, lr 157 158 @ 159 @ We are now ready to fill in the remaining blanks on the stack: 160 @ 161 @ r0 - sp_svc 162 @ r1 - lr_svc 163 @ r2 - lr_<exception>, already fixed up for correct return/restart 164 @ r3 - spsr_<exception> 165 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 166 @ 167 stmia r5, {r0 - r4} 168 .endm 169 170 .align 5 171__dabt_svc: 172 svc_entry 173 174 @ 175 @ get ready to re-enable interrupts if appropriate 176 @ 177 mrs r9, cpsr 178 tst r3, #PSR_I_BIT 179 biceq r9, r9, #PSR_I_BIT 180 181 @ 182 @ Call the processor-specific abort handler: 183 @ 184 @ r2 - aborted context pc 185 @ r3 - aborted context cpsr 186 @ 187 @ The abort handler must return the aborted address in r0, and 188 @ the fault status register in r1. r9 must be preserved. 189 @ 190#ifdef MULTI_DABORT 191 ldr r4, .LCprocfns 192 mov lr, pc 193 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 194#else 195 bl CPU_DABORT_HANDLER 196#endif 197 198 @ 199 @ set desired IRQ state, then call main handler 200 @ 201 msr cpsr_c, r9 202 mov r2, sp 203 bl do_DataAbort 204 205 @ 206 @ IRQs off again before pulling preserved data off the stack 207 @ 208 disable_irq_notrace 209 210 @ 211 @ restore SPSR and restart the instruction 212 @ 213 ldr r2, [sp, #S_PSR] 214 svc_exit r2 @ return from exception 215 UNWIND(.fnend ) 216ENDPROC(__dabt_svc) 217 218 .align 5 219__irq_svc: 220 svc_entry 221 222#ifdef CONFIG_TRACE_IRQFLAGS 223 bl trace_hardirqs_off 224#endif 225#ifdef CONFIG_PREEMPT 226 get_thread_info tsk 227 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 228 add r7, r8, #1 @ increment it 229 str r7, [tsk, #TI_PREEMPT] 230#endif 231 232 irq_handler 233#ifdef CONFIG_PREEMPT 234 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 235 ldr r0, [tsk, #TI_FLAGS] @ get flags 236 teq r8, #0 @ if preempt count != 0 237 movne r0, #0 @ force flags to 0 238 tst r0, #_TIF_NEED_RESCHED 239 blne svc_preempt 240#endif 241 ldr r4, [sp, #S_PSR] @ irqs are already disabled 242#ifdef CONFIG_TRACE_IRQFLAGS 243 tst r4, #PSR_I_BIT 244 bleq trace_hardirqs_on 245#endif 246 svc_exit r4 @ return from exception 247 UNWIND(.fnend ) 248ENDPROC(__irq_svc) 249 250 .ltorg 251 252#ifdef CONFIG_PREEMPT 253svc_preempt: 254 mov r8, lr 2551: bl preempt_schedule_irq @ irq en/disable is done inside 256 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 257 tst r0, #_TIF_NEED_RESCHED 258 moveq pc, r8 @ go again 259 b 1b 260#endif 261 262 .align 5 263__und_svc: 264#ifdef CONFIG_KPROBES 265 @ If a kprobe is about to simulate a "stmdb sp..." instruction, 266 @ it obviously needs free stack space which then will belong to 267 @ the saved context. 268 svc_entry 64 269#else 270 svc_entry 271#endif 272 273 @ 274 @ call emulation code, which returns using r9 if it has emulated 275 @ the instruction, or the more conventional lr if we are to treat 276 @ this as a real undefined instruction 277 @ 278 @ r0 - instruction 279 @ 280#ifndef CONFIG_THUMB2_KERNEL 281 ldr r0, [r2, #-4] 282#else 283 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2 284 and r9, r0, #0xf800 285 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 286 ldrhhs r9, [r2] @ bottom 16 bits 287 orrhs r0, r9, r0, lsl #16 288#endif 289 adr r9, BSYM(1f) 290 bl call_fpe 291 292 mov r0, sp @ struct pt_regs *regs 293 bl do_undefinstr 294 295 @ 296 @ IRQs off again before pulling preserved data off the stack 297 @ 2981: disable_irq_notrace 299 300 @ 301 @ restore SPSR and restart the instruction 302 @ 303 ldr r2, [sp, #S_PSR] @ Get SVC cpsr 304 svc_exit r2 @ return from exception 305 UNWIND(.fnend ) 306ENDPROC(__und_svc) 307 308 .align 5 309__pabt_svc: 310 svc_entry 311 312 @ 313 @ re-enable interrupts if appropriate 314 @ 315 mrs r9, cpsr 316 tst r3, #PSR_I_BIT 317 biceq r9, r9, #PSR_I_BIT 318 319 mov r0, r2 @ pass address of aborted instruction. 320#ifdef MULTI_PABORT 321 ldr r4, .LCprocfns 322 mov lr, pc 323 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 324#else 325 bl CPU_PABORT_HANDLER 326#endif 327 msr cpsr_c, r9 @ Maybe enable interrupts 328 mov r2, sp @ regs 329 bl do_PrefetchAbort @ call abort handler 330 331 @ 332 @ IRQs off again before pulling preserved data off the stack 333 @ 334 disable_irq_notrace 335 336 @ 337 @ restore SPSR and restart the instruction 338 @ 339 ldr r2, [sp, #S_PSR] 340 svc_exit r2 @ return from exception 341 UNWIND(.fnend ) 342ENDPROC(__pabt_svc) 343 344 .align 5 345.LCcralign: 346 .word cr_alignment 347#ifdef MULTI_DABORT 348.LCprocfns: 349 .word processor 350#endif 351.LCfp: 352 .word fp_enter 353 354/* 355 * User mode handlers 356 * 357 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 358 */ 359 360#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 361#error "sizeof(struct pt_regs) must be a multiple of 8" 362#endif 363 364 .macro usr_entry 365 UNWIND(.fnstart ) 366 UNWIND(.cantunwind ) @ don't unwind the user space 367 sub sp, sp, #S_FRAME_SIZE 368 ARM( stmib sp, {r1 - r12} ) 369 THUMB( stmia sp, {r0 - r12} ) 370 371 ldmia r0, {r1 - r3} 372 add r0, sp, #S_PC @ here for interlock avoidance 373 mov r4, #-1 @ "" "" "" "" 374 375 str r1, [sp] @ save the "real" r0 copied 376 @ from the exception stack 377 378 @ 379 @ We are now ready to fill in the remaining blanks on the stack: 380 @ 381 @ r2 - lr_<exception>, already fixed up for correct return/restart 382 @ r3 - spsr_<exception> 383 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 384 @ 385 @ Also, separately save sp_usr and lr_usr 386 @ 387 stmia r0, {r2 - r4} 388 ARM( stmdb r0, {sp, lr}^ ) 389 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 390 391 @ 392 @ Enable the alignment trap while in kernel mode 393 @ 394 alignment_trap r0 395 396 @ 397 @ Clear FP to mark the first stack frame 398 @ 399 zero_fp 400 .endm 401 402 .macro kuser_cmpxchg_check 403#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 404#ifndef CONFIG_MMU 405#warning "NPTL on non MMU needs fixing" 406#else 407 @ Make sure our user space atomic helper is restarted 408 @ if it was interrupted in a critical region. Here we 409 @ perform a quick test inline since it should be false 410 @ 99.9999% of the time. The rest is done out of line. 411 cmp r2, #TASK_SIZE 412 blhs kuser_cmpxchg_fixup 413#endif 414#endif 415 .endm 416 417 .align 5 418__dabt_usr: 419 usr_entry 420 kuser_cmpxchg_check 421 422 @ 423 @ Call the processor-specific abort handler: 424 @ 425 @ r2 - aborted context pc 426 @ r3 - aborted context cpsr 427 @ 428 @ The abort handler must return the aborted address in r0, and 429 @ the fault status register in r1. 430 @ 431#ifdef MULTI_DABORT 432 ldr r4, .LCprocfns 433 mov lr, pc 434 ldr pc, [r4, #PROCESSOR_DABT_FUNC] 435#else 436 bl CPU_DABORT_HANDLER 437#endif 438 439 @ 440 @ IRQs on, then call the main handler 441 @ 442 enable_irq 443 mov r2, sp 444 adr lr, BSYM(ret_from_exception) 445 b do_DataAbort 446 UNWIND(.fnend ) 447ENDPROC(__dabt_usr) 448 449 .align 5 450__irq_usr: 451 usr_entry 452 kuser_cmpxchg_check 453 454 get_thread_info tsk 455#ifdef CONFIG_PREEMPT 456 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 457 add r7, r8, #1 @ increment it 458 str r7, [tsk, #TI_PREEMPT] 459#endif 460 461 irq_handler 462#ifdef CONFIG_PREEMPT 463 ldr r0, [tsk, #TI_PREEMPT] 464 str r8, [tsk, #TI_PREEMPT] 465 teq r0, r7 466 ARM( strne r0, [r0, -r0] ) 467 THUMB( movne r0, #0 ) 468 THUMB( strne r0, [r0] ) 469#endif 470 471 mov why, #0 472 b ret_to_user 473 UNWIND(.fnend ) 474ENDPROC(__irq_usr) 475 476 .ltorg 477 478 .align 5 479__und_usr: 480 usr_entry 481 482 @ 483 @ fall through to the emulation code, which returns using r9 if 484 @ it has emulated the instruction, or the more conventional lr 485 @ if we are to treat this as a real undefined instruction 486 @ 487 @ r0 - instruction 488 @ 489 adr r9, BSYM(ret_from_exception) 490 adr lr, BSYM(__und_usr_unknown) 491 tst r3, #PSR_T_BIT @ Thumb mode? 492 itet eq @ explicit IT needed for the 1f label 493 subeq r4, r2, #4 @ ARM instr at LR - 4 494 subne r4, r2, #2 @ Thumb instr at LR - 2 4951: ldreqt r0, [r4] 496#ifdef CONFIG_CPU_ENDIAN_BE8 497 reveq r0, r0 @ little endian instruction 498#endif 499 beq call_fpe 500 @ Thumb instruction 501#if __LINUX_ARM_ARCH__ >= 7 5022: 503 ARM( ldrht r5, [r4], #2 ) 504 THUMB( ldrht r5, [r4] ) 505 THUMB( add r4, r4, #2 ) 506 and r0, r5, #0xf800 @ mask bits 111x x... .... .... 507 cmp r0, #0xe800 @ 32bit instruction if xx != 0 508 blo __und_usr_unknown 5093: ldrht r0, [r4] 510 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 511 orr r0, r0, r5, lsl #16 512#else 513 b __und_usr_unknown 514#endif 515 UNWIND(.fnend ) 516ENDPROC(__und_usr) 517 518 @ 519 @ fallthrough to call_fpe 520 @ 521 522/* 523 * The out of line fixup for the ldrt above. 524 */ 525 .pushsection .fixup, "ax" 5264: mov pc, r9 527 .popsection 528 .pushsection __ex_table,"a" 529 .long 1b, 4b 530#if __LINUX_ARM_ARCH__ >= 7 531 .long 2b, 4b 532 .long 3b, 4b 533#endif 534 .popsection 535 536/* 537 * Check whether the instruction is a co-processor instruction. 538 * If yes, we need to call the relevant co-processor handler. 539 * 540 * Note that we don't do a full check here for the co-processor 541 * instructions; all instructions with bit 27 set are well 542 * defined. The only instructions that should fault are the 543 * co-processor instructions. However, we have to watch out 544 * for the ARM6/ARM7 SWI bug. 545 * 546 * NEON is a special case that has to be handled here. Not all 547 * NEON instructions are co-processor instructions, so we have 548 * to make a special case of checking for them. Plus, there's 549 * five groups of them, so we have a table of mask/opcode pairs 550 * to check against, and if any match then we branch off into the 551 * NEON handler code. 552 * 553 * Emulators may wish to make use of the following registers: 554 * r0 = instruction opcode. 555 * r2 = PC+4 556 * r9 = normal "successful" return address 557 * r10 = this threads thread_info structure. 558 * lr = unrecognised instruction return address 559 */ 560 @ 561 @ Fall-through from Thumb-2 __und_usr 562 @ 563#ifdef CONFIG_NEON 564 adr r6, .LCneon_thumb_opcodes 565 b 2f 566#endif 567call_fpe: 568#ifdef CONFIG_NEON 569 adr r6, .LCneon_arm_opcodes 5702: 571 ldr r7, [r6], #4 @ mask value 572 cmp r7, #0 @ end mask? 573 beq 1f 574 and r8, r0, r7 575 ldr r7, [r6], #4 @ opcode bits matching in mask 576 cmp r8, r7 @ NEON instruction? 577 bne 2b 578 get_thread_info r10 579 mov r7, #1 580 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 581 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 582 b do_vfp @ let VFP handler handle this 5831: 584#endif 585 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 586 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 587#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 588 and r8, r0, #0x0f000000 @ mask out op-code bits 589 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 590#endif 591 moveq pc, lr 592 get_thread_info r10 @ get current thread 593 and r8, r0, #0x00000f00 @ mask out CP number 594 THUMB( lsr r8, r8, #8 ) 595 mov r7, #1 596 add r6, r10, #TI_USED_CP 597 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 598 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 599#ifdef CONFIG_IWMMXT 600 @ Test if we need to give access to iWMMXt coprocessors 601 ldr r5, [r10, #TI_FLAGS] 602 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 603 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 604 bcs iwmmxt_task_enable 605#endif 606 ARM( add pc, pc, r8, lsr #6 ) 607 THUMB( lsl r8, r8, #2 ) 608 THUMB( add pc, r8 ) 609 nop 610 611 movw_pc lr @ CP#0 612 W(b) do_fpe @ CP#1 (FPE) 613 W(b) do_fpe @ CP#2 (FPE) 614 movw_pc lr @ CP#3 615#ifdef CONFIG_CRUNCH 616 b crunch_task_enable @ CP#4 (MaverickCrunch) 617 b crunch_task_enable @ CP#5 (MaverickCrunch) 618 b crunch_task_enable @ CP#6 (MaverickCrunch) 619#else 620 movw_pc lr @ CP#4 621 movw_pc lr @ CP#5 622 movw_pc lr @ CP#6 623#endif 624 movw_pc lr @ CP#7 625 movw_pc lr @ CP#8 626 movw_pc lr @ CP#9 627#ifdef CONFIG_VFP 628 W(b) do_vfp @ CP#10 (VFP) 629 W(b) do_vfp @ CP#11 (VFP) 630#else 631 movw_pc lr @ CP#10 (VFP) 632 movw_pc lr @ CP#11 (VFP) 633#endif 634 movw_pc lr @ CP#12 635 movw_pc lr @ CP#13 636 movw_pc lr @ CP#14 (Debug) 637 movw_pc lr @ CP#15 (Control) 638 639#ifdef CONFIG_NEON 640 .align 6 641 642.LCneon_arm_opcodes: 643 .word 0xfe000000 @ mask 644 .word 0xf2000000 @ opcode 645 646 .word 0xff100000 @ mask 647 .word 0xf4000000 @ opcode 648 649 .word 0x00000000 @ mask 650 .word 0x00000000 @ opcode 651 652.LCneon_thumb_opcodes: 653 .word 0xef000000 @ mask 654 .word 0xef000000 @ opcode 655 656 .word 0xff100000 @ mask 657 .word 0xf9000000 @ opcode 658 659 .word 0x00000000 @ mask 660 .word 0x00000000 @ opcode 661#endif 662 663do_fpe: 664 enable_irq 665 ldr r4, .LCfp 666 add r10, r10, #TI_FPSTATE @ r10 = workspace 667 ldr pc, [r4] @ Call FP module USR entry point 668 669/* 670 * The FP module is called with these registers set: 671 * r0 = instruction 672 * r2 = PC+4 673 * r9 = normal "successful" return address 674 * r10 = FP workspace 675 * lr = unrecognised FP instruction return address 676 */ 677 678 .pushsection .data 679ENTRY(fp_enter) 680 .word no_fp 681 .popsection 682 683ENTRY(no_fp) 684 mov pc, lr 685ENDPROC(no_fp) 686 687__und_usr_unknown: 688 enable_irq 689 mov r0, sp 690 adr lr, BSYM(ret_from_exception) 691 b do_undefinstr 692ENDPROC(__und_usr_unknown) 693 694 .align 5 695__pabt_usr: 696 usr_entry 697 698 mov r0, r2 @ pass address of aborted instruction. 699#ifdef MULTI_PABORT 700 ldr r4, .LCprocfns 701 mov lr, pc 702 ldr pc, [r4, #PROCESSOR_PABT_FUNC] 703#else 704 bl CPU_PABORT_HANDLER 705#endif 706 enable_irq @ Enable interrupts 707 mov r2, sp @ regs 708 bl do_PrefetchAbort @ call abort handler 709 UNWIND(.fnend ) 710 /* fall through */ 711/* 712 * This is the return code to user mode for abort handlers 713 */ 714ENTRY(ret_from_exception) 715 UNWIND(.fnstart ) 716 UNWIND(.cantunwind ) 717 get_thread_info tsk 718 mov why, #0 719 b ret_to_user 720 UNWIND(.fnend ) 721ENDPROC(__pabt_usr) 722ENDPROC(ret_from_exception) 723 724/* 725 * Register switch for ARMv3 and ARMv4 processors 726 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 727 * previous and next are guaranteed not to be the same. 728 */ 729ENTRY(__switch_to) 730 UNWIND(.fnstart ) 731 UNWIND(.cantunwind ) 732 add ip, r1, #TI_CPU_SAVE 733 ldr r3, [r2, #TI_TP_VALUE] 734 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 735 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 736 THUMB( str sp, [ip], #4 ) 737 THUMB( str lr, [ip], #4 ) 738#ifdef CONFIG_MMU 739 ldr r6, [r2, #TI_CPU_DOMAIN] 740#endif 741 set_tls r3, r4, r5 742#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 743 ldr r7, [r2, #TI_TASK] 744 ldr r8, =__stack_chk_guard 745 ldr r7, [r7, #TSK_STACK_CANARY] 746#endif 747#ifdef CONFIG_MMU 748 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 749#endif 750 mov r5, r0 751 add r4, r2, #TI_CPU_SAVE 752 ldr r0, =thread_notify_head 753 mov r1, #THREAD_NOTIFY_SWITCH 754 bl atomic_notifier_call_chain 755#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 756 str r7, [r8] 757#endif 758 THUMB( mov ip, r4 ) 759 mov r0, r5 760 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 761 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 762 THUMB( ldr sp, [ip], #4 ) 763 THUMB( ldr pc, [ip] ) 764 UNWIND(.fnend ) 765ENDPROC(__switch_to) 766 767 __INIT 768 769/* 770 * User helpers. 771 * 772 * These are segment of kernel provided user code reachable from user space 773 * at a fixed address in kernel memory. This is used to provide user space 774 * with some operations which require kernel help because of unimplemented 775 * native feature and/or instructions in many ARM CPUs. The idea is for 776 * this code to be executed directly in user mode for best efficiency but 777 * which is too intimate with the kernel counter part to be left to user 778 * libraries. In fact this code might even differ from one CPU to another 779 * depending on the available instruction set and restrictions like on 780 * SMP systems. In other words, the kernel reserves the right to change 781 * this code as needed without warning. Only the entry points and their 782 * results are guaranteed to be stable. 783 * 784 * Each segment is 32-byte aligned and will be moved to the top of the high 785 * vector page. New segments (if ever needed) must be added in front of 786 * existing ones. This mechanism should be used only for things that are 787 * really small and justified, and not be abused freely. 788 * 789 * User space is expected to implement those things inline when optimizing 790 * for a processor that has the necessary native support, but only if such 791 * resulting binaries are already to be incompatible with earlier ARM 792 * processors due to the use of unsupported instructions other than what 793 * is provided here. In other words don't make binaries unable to run on 794 * earlier processors just for the sake of not using these kernel helpers 795 * if your compiled code is not going to use the new instructions for other 796 * purpose. 797 */ 798 THUMB( .arm ) 799 800 .macro usr_ret, reg 801#ifdef CONFIG_ARM_THUMB 802 bx \reg 803#else 804 mov pc, \reg 805#endif 806 .endm 807 808 .align 5 809 .globl __kuser_helper_start 810__kuser_helper_start: 811 812/* 813 * Reference prototype: 814 * 815 * void __kernel_memory_barrier(void) 816 * 817 * Input: 818 * 819 * lr = return address 820 * 821 * Output: 822 * 823 * none 824 * 825 * Clobbered: 826 * 827 * none 828 * 829 * Definition and user space usage example: 830 * 831 * typedef void (__kernel_dmb_t)(void); 832 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 833 * 834 * Apply any needed memory barrier to preserve consistency with data modified 835 * manually and __kuser_cmpxchg usage. 836 * 837 * This could be used as follows: 838 * 839 * #define __kernel_dmb() \ 840 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 841 * : : : "r0", "lr","cc" ) 842 */ 843 844__kuser_memory_barrier: @ 0xffff0fa0 845 smp_dmb 846 usr_ret lr 847 848 .align 5 849 850/* 851 * Reference prototype: 852 * 853 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 854 * 855 * Input: 856 * 857 * r0 = oldval 858 * r1 = newval 859 * r2 = ptr 860 * lr = return address 861 * 862 * Output: 863 * 864 * r0 = returned value (zero or non-zero) 865 * C flag = set if r0 == 0, clear if r0 != 0 866 * 867 * Clobbered: 868 * 869 * r3, ip, flags 870 * 871 * Definition and user space usage example: 872 * 873 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 874 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 875 * 876 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 877 * Return zero if *ptr was changed or non-zero if no exchange happened. 878 * The C flag is also set if *ptr was changed to allow for assembly 879 * optimization in the calling code. 880 * 881 * Notes: 882 * 883 * - This routine already includes memory barriers as needed. 884 * 885 * For example, a user space atomic_add implementation could look like this: 886 * 887 * #define atomic_add(ptr, val) \ 888 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 889 * register unsigned int __result asm("r1"); \ 890 * asm volatile ( \ 891 * "1: @ atomic_add\n\t" \ 892 * "ldr r0, [r2]\n\t" \ 893 * "mov r3, #0xffff0fff\n\t" \ 894 * "add lr, pc, #4\n\t" \ 895 * "add r1, r0, %2\n\t" \ 896 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 897 * "bcc 1b" \ 898 * : "=&r" (__result) \ 899 * : "r" (__ptr), "rIL" (val) \ 900 * : "r0","r3","ip","lr","cc","memory" ); \ 901 * __result; }) 902 */ 903 904__kuser_cmpxchg: @ 0xffff0fc0 905 906#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 907 908 /* 909 * Poor you. No fast solution possible... 910 * The kernel itself must perform the operation. 911 * A special ghost syscall is used for that (see traps.c). 912 */ 913 stmfd sp!, {r7, lr} 914 ldr r7, =1f @ it's 20 bits 915 swi __ARM_NR_cmpxchg 916 ldmfd sp!, {r7, pc} 9171: .word __ARM_NR_cmpxchg 918 919#elif __LINUX_ARM_ARCH__ < 6 920 921#ifdef CONFIG_MMU 922 923 /* 924 * The only thing that can break atomicity in this cmpxchg 925 * implementation is either an IRQ or a data abort exception 926 * causing another process/thread to be scheduled in the middle 927 * of the critical sequence. To prevent this, code is added to 928 * the IRQ and data abort exception handlers to set the pc back 929 * to the beginning of the critical section if it is found to be 930 * within that critical section (see kuser_cmpxchg_fixup). 931 */ 9321: ldr r3, [r2] @ load current val 933 subs r3, r3, r0 @ compare with oldval 9342: streq r1, [r2] @ store newval if eq 935 rsbs r0, r3, #0 @ set return val and C flag 936 usr_ret lr 937 938 .text 939kuser_cmpxchg_fixup: 940 @ Called from kuser_cmpxchg_check macro. 941 @ r2 = address of interrupted insn (must be preserved). 942 @ sp = saved regs. r7 and r8 are clobbered. 943 @ 1b = first critical insn, 2b = last critical insn. 944 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. 945 mov r7, #0xffff0fff 946 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 947 subs r8, r2, r7 948 rsbcss r8, r8, #(2b - 1b) 949 strcs r7, [sp, #S_PC] 950 mov pc, lr 951 .previous 952 953#else 954#warning "NPTL on non MMU needs fixing" 955 mov r0, #-1 956 adds r0, r0, #0 957 usr_ret lr 958#endif 959 960#else 961 962 smp_dmb 9631: ldrex r3, [r2] 964 subs r3, r3, r0 965 strexeq r3, r1, [r2] 966 teqeq r3, #1 967 beq 1b 968 rsbs r0, r3, #0 969 /* beware -- each __kuser slot must be 8 instructions max */ 970 ALT_SMP(b __kuser_memory_barrier) 971 ALT_UP(usr_ret lr) 972 973#endif 974 975 .align 5 976 977/* 978 * Reference prototype: 979 * 980 * int __kernel_get_tls(void) 981 * 982 * Input: 983 * 984 * lr = return address 985 * 986 * Output: 987 * 988 * r0 = TLS value 989 * 990 * Clobbered: 991 * 992 * none 993 * 994 * Definition and user space usage example: 995 * 996 * typedef int (__kernel_get_tls_t)(void); 997 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 998 * 999 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 1000 * 1001 * This could be used as follows: 1002 * 1003 * #define __kernel_get_tls() \ 1004 * ({ register unsigned int __val asm("r0"); \ 1005 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 1006 * : "=r" (__val) : : "lr","cc" ); \ 1007 * __val; }) 1008 */ 1009 1010__kuser_get_tls: @ 0xffff0fe0 1011 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init 1012 usr_ret lr 1013 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code 1014 .rep 4 1015 .word 0 @ 0xffff0ff0 software TLS value, then 1016 .endr @ pad up to __kuser_helper_version 1017 1018/* 1019 * Reference declaration: 1020 * 1021 * extern unsigned int __kernel_helper_version; 1022 * 1023 * Definition and user space usage example: 1024 * 1025 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 1026 * 1027 * User space may read this to determine the curent number of helpers 1028 * available. 1029 */ 1030 1031__kuser_helper_version: @ 0xffff0ffc 1032 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 1033 1034 .globl __kuser_helper_end 1035__kuser_helper_end: 1036 1037 THUMB( .thumb ) 1038 1039/* 1040 * Vector stubs. 1041 * 1042 * This code is copied to 0xffff0200 so we can use branches in the 1043 * vectors, rather than ldr's. Note that this code must not 1044 * exceed 0x300 bytes. 1045 * 1046 * Common stub entry macro: 1047 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1048 * 1049 * SP points to a minimal amount of processor-private memory, the address 1050 * of which is copied into r0 for the mode specific abort handler. 1051 */ 1052 .macro vector_stub, name, mode, correction=0 1053 .align 5 1054 1055vector_\name: 1056 .if \correction 1057 sub lr, lr, #\correction 1058 .endif 1059 1060 @ 1061 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1062 @ (parent CPSR) 1063 @ 1064 stmia sp, {r0, lr} @ save r0, lr 1065 mrs lr, spsr 1066 str lr, [sp, #8] @ save spsr 1067 1068 @ 1069 @ Prepare for SVC32 mode. IRQs remain disabled. 1070 @ 1071 mrs r0, cpsr 1072 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1073 msr spsr_cxsf, r0 1074 1075 @ 1076 @ the branch table must immediately follow this code 1077 @ 1078 and lr, lr, #0x0f 1079 THUMB( adr r0, 1f ) 1080 THUMB( ldr lr, [r0, lr, lsl #2] ) 1081 mov r0, sp 1082 ARM( ldr lr, [pc, lr, lsl #2] ) 1083 movs pc, lr @ branch to handler in SVC mode 1084ENDPROC(vector_\name) 1085 1086 .align 2 1087 @ handler addresses follow this label 10881: 1089 .endm 1090 1091 .globl __stubs_start 1092__stubs_start: 1093/* 1094 * Interrupt dispatcher 1095 */ 1096 vector_stub irq, IRQ_MODE, 4 1097 1098 .long __irq_usr @ 0 (USR_26 / USR_32) 1099 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1100 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 1101 .long __irq_svc @ 3 (SVC_26 / SVC_32) 1102 .long __irq_invalid @ 4 1103 .long __irq_invalid @ 5 1104 .long __irq_invalid @ 6 1105 .long __irq_invalid @ 7 1106 .long __irq_invalid @ 8 1107 .long __irq_invalid @ 9 1108 .long __irq_invalid @ a 1109 .long __irq_invalid @ b 1110 .long __irq_invalid @ c 1111 .long __irq_invalid @ d 1112 .long __irq_invalid @ e 1113 .long __irq_invalid @ f 1114 1115/* 1116 * Data abort dispatcher 1117 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1118 */ 1119 vector_stub dabt, ABT_MODE, 8 1120 1121 .long __dabt_usr @ 0 (USR_26 / USR_32) 1122 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 1123 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 1124 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 1125 .long __dabt_invalid @ 4 1126 .long __dabt_invalid @ 5 1127 .long __dabt_invalid @ 6 1128 .long __dabt_invalid @ 7 1129 .long __dabt_invalid @ 8 1130 .long __dabt_invalid @ 9 1131 .long __dabt_invalid @ a 1132 .long __dabt_invalid @ b 1133 .long __dabt_invalid @ c 1134 .long __dabt_invalid @ d 1135 .long __dabt_invalid @ e 1136 .long __dabt_invalid @ f 1137 1138/* 1139 * Prefetch abort dispatcher 1140 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 1141 */ 1142 vector_stub pabt, ABT_MODE, 4 1143 1144 .long __pabt_usr @ 0 (USR_26 / USR_32) 1145 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 1146 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 1147 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 1148 .long __pabt_invalid @ 4 1149 .long __pabt_invalid @ 5 1150 .long __pabt_invalid @ 6 1151 .long __pabt_invalid @ 7 1152 .long __pabt_invalid @ 8 1153 .long __pabt_invalid @ 9 1154 .long __pabt_invalid @ a 1155 .long __pabt_invalid @ b 1156 .long __pabt_invalid @ c 1157 .long __pabt_invalid @ d 1158 .long __pabt_invalid @ e 1159 .long __pabt_invalid @ f 1160 1161/* 1162 * Undef instr entry dispatcher 1163 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1164 */ 1165 vector_stub und, UND_MODE 1166 1167 .long __und_usr @ 0 (USR_26 / USR_32) 1168 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1169 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1170 .long __und_svc @ 3 (SVC_26 / SVC_32) 1171 .long __und_invalid @ 4 1172 .long __und_invalid @ 5 1173 .long __und_invalid @ 6 1174 .long __und_invalid @ 7 1175 .long __und_invalid @ 8 1176 .long __und_invalid @ 9 1177 .long __und_invalid @ a 1178 .long __und_invalid @ b 1179 .long __und_invalid @ c 1180 .long __und_invalid @ d 1181 .long __und_invalid @ e 1182 .long __und_invalid @ f 1183 1184 .align 5 1185 1186/*============================================================================= 1187 * Undefined FIQs 1188 *----------------------------------------------------------------------------- 1189 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1190 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1191 * Basically to switch modes, we *HAVE* to clobber one register... brain 1192 * damage alert! I don't think that we can execute any code in here in any 1193 * other mode than FIQ... Ok you can switch to another mode, but you can't 1194 * get out of that mode without clobbering one register. 1195 */ 1196vector_fiq: 1197 disable_fiq 1198 subs pc, lr, #4 1199 1200/*============================================================================= 1201 * Address exception handler 1202 *----------------------------------------------------------------------------- 1203 * These aren't too critical. 1204 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1205 */ 1206 1207vector_addrexcptn: 1208 b vector_addrexcptn 1209 1210/* 1211 * We group all the following data together to optimise 1212 * for CPUs with separate I & D caches. 1213 */ 1214 .align 5 1215 1216.LCvswi: 1217 .word vector_swi 1218 1219 .globl __stubs_end 1220__stubs_end: 1221 1222 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1223 1224 .globl __vectors_start 1225__vectors_start: 1226 ARM( swi SYS_ERROR0 ) 1227 THUMB( svc #0 ) 1228 THUMB( nop ) 1229 W(b) vector_und + stubs_offset 1230 W(ldr) pc, .LCvswi + stubs_offset 1231 W(b) vector_pabt + stubs_offset 1232 W(b) vector_dabt + stubs_offset 1233 W(b) vector_addrexcptn + stubs_offset 1234 W(b) vector_irq + stubs_offset 1235 W(b) vector_fiq + stubs_offset 1236 1237 .globl __vectors_end 1238__vectors_end: 1239 1240 .data 1241 1242 .globl cr_alignment 1243 .globl cr_no_alignment 1244cr_alignment: 1245 .space 4 1246cr_no_alignment: 1247 .space 4 1248