1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/arm/kernel/bios32.c 4 * 5 * PCI bios-type initialisation for PCI machines 6 * 7 * Bits taken from various places. 8 */ 9 #include <linux/export.h> 10 #include <linux/kernel.h> 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 #include <linux/string_choices.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 17 #include <asm/mach-types.h> 18 #include <asm/mach/map.h> 19 #include <asm/mach/pci.h> 20 21 static int debug_pci; 22 23 /* 24 * We can't use pci_get_device() here since we are 25 * called from interrupt context. 26 */ 27 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) 28 { 29 struct pci_dev *dev; 30 31 list_for_each_entry(dev, &bus->devices, bus_list) { 32 u16 status; 33 34 /* 35 * ignore host bridge - we handle 36 * that separately 37 */ 38 if (dev->bus->number == 0 && dev->devfn == 0) 39 continue; 40 41 pci_read_config_word(dev, PCI_STATUS, &status); 42 if (status == 0xffff) 43 continue; 44 45 if ((status & status_mask) == 0) 46 continue; 47 48 /* clear the status errors */ 49 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 50 51 if (warn) 52 printk("(%s: %04X) ", pci_name(dev), status); 53 } 54 55 list_for_each_entry(dev, &bus->devices, bus_list) 56 if (dev->subordinate) 57 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 58 } 59 60 void pcibios_report_status(u_int status_mask, int warn) 61 { 62 struct pci_bus *bus; 63 64 list_for_each_entry(bus, &pci_root_buses, node) 65 pcibios_bus_report_status(bus, status_mask, warn); 66 } 67 68 /* 69 * We don't use this to fix the device, but initialisation of it. 70 * It's not the correct use for this, but it works. 71 * Note that the arbiter/ISA bridge appears to be buggy, specifically in 72 * the following area: 73 * 1. park on CPU 74 * 2. ISA bridge ping-pong 75 * 3. ISA bridge master handling of target RETRY 76 * 77 * Bug 3 is responsible for the sound DMA grinding to a halt. We now 78 * live with bug 2. 79 */ 80 static void pci_fixup_83c553(struct pci_dev *dev) 81 { 82 /* 83 * Set memory region to start at address 0, and enable IO 84 */ 85 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); 86 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); 87 88 dev->resource[0].end -= dev->resource[0].start; 89 dev->resource[0].start = 0; 90 91 /* 92 * All memory requests from ISA to be channelled to PCI 93 */ 94 pci_write_config_byte(dev, 0x48, 0xff); 95 96 /* 97 * Enable ping-pong on bus master to ISA bridge transactions. 98 * This improves the sound DMA substantially. The fixed 99 * priority arbiter also helps (see below). 100 */ 101 pci_write_config_byte(dev, 0x42, 0x01); 102 103 /* 104 * Enable PCI retry 105 */ 106 pci_write_config_byte(dev, 0x40, 0x22); 107 108 /* 109 * We used to set the arbiter to "park on last master" (bit 110 * 1 set), but unfortunately the CyberPro does not park the 111 * bus. We must therefore park on CPU. Unfortunately, this 112 * may trigger yet another bug in the 553. 113 */ 114 pci_write_config_byte(dev, 0x83, 0x02); 115 116 /* 117 * Make the ISA DMA request lowest priority, and disable 118 * rotating priorities completely. 119 */ 120 pci_write_config_byte(dev, 0x80, 0x11); 121 pci_write_config_byte(dev, 0x81, 0x00); 122 123 /* 124 * Route INTA input to IRQ 11, and set IRQ11 to be level 125 * sensitive. 126 */ 127 pci_write_config_word(dev, 0x44, 0xb000); 128 outb(0x08, 0x4d1); 129 } 130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); 131 132 static void pci_fixup_unassign(struct pci_dev *dev) 133 { 134 dev->resource[0].end -= dev->resource[0].start; 135 dev->resource[0].start = 0; 136 } 137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); 138 139 /* 140 * Prevent the PCI layer from seeing the resources allocated to this device 141 * if it is the host bridge by marking it as such. These resources are of 142 * no consequence to the PCI layer (they are handled elsewhere). 143 */ 144 static void pci_fixup_dec21285(struct pci_dev *dev) 145 { 146 if (dev->devfn == 0) { 147 struct resource *r; 148 149 dev->class &= 0xff; 150 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; 151 pci_dev_for_each_resource(dev, r) { 152 r->start = 0; 153 r->end = 0; 154 r->flags = 0; 155 } 156 } 157 } 158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); 159 160 /* 161 * PCI IDE controllers use non-standard I/O port decoding, respect it. 162 */ 163 static void pci_fixup_ide_bases(struct pci_dev *dev) 164 { 165 struct resource *r; 166 167 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 168 return; 169 170 pci_dev_for_each_resource(dev, r) { 171 if ((r->start & ~0x80) == 0x374) { 172 r->start |= 2; 173 r->end = r->start; 174 } 175 } 176 } 177 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 178 179 /* 180 * Put the DEC21142 to sleep 181 */ 182 static void pci_fixup_dec21142(struct pci_dev *dev) 183 { 184 pci_write_config_dword(dev, 0x40, 0x80000000); 185 } 186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); 187 188 /* 189 * The CY82C693 needs some rather major fixups to ensure that it does 190 * the right thing. Idea from the Alpha people, with a few additions. 191 * 192 * We ensure that the IDE base registers are set to 1f0/3f4 for the 193 * primary bus, and 170/374 for the secondary bus. Also, hide them 194 * from the PCI subsystem view as well so we won't try to perform 195 * our own auto-configuration on them. 196 * 197 * In addition, we ensure that the PCI IDE interrupts are routed to 198 * IRQ 14 and IRQ 15 respectively. 199 * 200 * The above gets us to a point where the IDE on this device is 201 * functional. However, The CY82C693U _does not work_ in bus 202 * master mode without locking the PCI bus solid. 203 */ 204 static void pci_fixup_cy82c693(struct pci_dev *dev) 205 { 206 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 207 u32 base0, base1; 208 209 if (dev->class & 0x80) { /* primary */ 210 base0 = 0x1f0; 211 base1 = 0x3f4; 212 } else { /* secondary */ 213 base0 = 0x170; 214 base1 = 0x374; 215 } 216 217 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 218 base0 | PCI_BASE_ADDRESS_SPACE_IO); 219 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 220 base1 | PCI_BASE_ADDRESS_SPACE_IO); 221 222 dev->resource[0].start = 0; 223 dev->resource[0].end = 0; 224 dev->resource[0].flags = 0; 225 226 dev->resource[1].start = 0; 227 dev->resource[1].end = 0; 228 dev->resource[1].flags = 0; 229 } else if (PCI_FUNC(dev->devfn) == 0) { 230 /* 231 * Setup IDE IRQ routing. 232 */ 233 pci_write_config_byte(dev, 0x4b, 14); 234 pci_write_config_byte(dev, 0x4c, 15); 235 236 /* 237 * Disable FREQACK handshake, enable USB. 238 */ 239 pci_write_config_byte(dev, 0x4d, 0x41); 240 241 /* 242 * Enable PCI retry, and PCI post-write buffer. 243 */ 244 pci_write_config_byte(dev, 0x44, 0x17); 245 246 /* 247 * Enable ISA master and DMA post write buffering. 248 */ 249 pci_write_config_byte(dev, 0x45, 0x03); 250 } 251 } 252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); 253 254 /* 255 * If the bus contains any of these devices, then we must not turn on 256 * parity checking of any kind. Currently this is CyberPro 20x0 only. 257 */ 258 static inline int pdev_bad_for_parity(struct pci_dev *dev) 259 { 260 return ((dev->vendor == PCI_VENDOR_ID_INTERG && 261 (dev->device == PCI_DEVICE_ID_INTERG_2000 || 262 dev->device == PCI_DEVICE_ID_INTERG_2010)) || 263 (dev->vendor == PCI_VENDOR_ID_ITE && 264 dev->device == PCI_DEVICE_ID_ITE_8152)); 265 266 } 267 268 /* 269 * pcibios_fixup_bus - Called after each bus is probed, 270 * but before its children are examined. 271 */ 272 void pcibios_fixup_bus(struct pci_bus *bus) 273 { 274 struct pci_dev *dev; 275 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; 276 277 /* 278 * Walk the devices on this bus, working out what we can 279 * and can't support. 280 */ 281 list_for_each_entry(dev, &bus->devices, bus_list) { 282 u16 status; 283 284 pci_read_config_word(dev, PCI_STATUS, &status); 285 286 /* 287 * If any device on this bus does not support fast back 288 * to back transfers, then the bus as a whole is not able 289 * to support them. Having fast back to back transfers 290 * on saves us one PCI cycle per transaction. 291 */ 292 if (!(status & PCI_STATUS_FAST_BACK)) 293 features &= ~PCI_COMMAND_FAST_BACK; 294 295 if (pdev_bad_for_parity(dev)) 296 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 297 298 switch (dev->class >> 8) { 299 case PCI_CLASS_BRIDGE_PCI: 300 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); 301 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; 302 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); 303 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); 304 break; 305 306 case PCI_CLASS_BRIDGE_CARDBUS: 307 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); 308 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; 309 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); 310 break; 311 } 312 } 313 314 /* 315 * Now walk the devices again, this time setting them up. 316 */ 317 list_for_each_entry(dev, &bus->devices, bus_list) { 318 u16 cmd; 319 320 pci_read_config_word(dev, PCI_COMMAND, &cmd); 321 cmd |= features; 322 pci_write_config_word(dev, PCI_COMMAND, cmd); 323 324 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 325 L1_CACHE_BYTES >> 2); 326 } 327 328 /* 329 * Propagate the flags to the PCI bridge. 330 */ 331 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 332 if (features & PCI_COMMAND_FAST_BACK) 333 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; 334 if (features & PCI_COMMAND_PARITY) 335 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; 336 } 337 338 /* 339 * Report what we did for this bus 340 */ 341 pr_info("PCI: bus%d: Fast back to back transfers %s\n", 342 bus->number, str_enabled_disabled(features & PCI_COMMAND_FAST_BACK)); 343 } 344 EXPORT_SYMBOL(pcibios_fixup_bus); 345 346 /* 347 * Swizzle the device pin each time we cross a bridge. If a platform does 348 * not provide a swizzle function, we perform the standard PCI swizzling. 349 * 350 * The default swizzling walks up the bus tree one level at a time, applying 351 * the standard swizzle function at each step, stopping when it finds the PCI 352 * root bus. This will return the slot number of the bridge device on the 353 * root bus and the interrupt pin on that device which should correspond 354 * with the downstream device interrupt. 355 * 356 * Platforms may override this, in which case the slot and pin returned 357 * depend entirely on the platform code. However, please note that the 358 * PCI standard swizzle is implemented on plug-in cards and Cardbus based 359 * PCI extenders, so it can not be ignored. 360 */ 361 static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin) 362 { 363 struct pci_sys_data *sys = dev->sysdata; 364 int slot, oldpin = *pin; 365 366 if (sys->swizzle) 367 slot = sys->swizzle(dev, pin); 368 else 369 slot = pci_common_swizzle(dev, pin); 370 371 if (debug_pci) 372 printk("PCI: %s swizzling pin %d => pin %d slot %d\n", 373 pci_name(dev), oldpin, *pin, slot); 374 375 return slot; 376 } 377 378 /* 379 * Map a slot/pin to an IRQ. 380 */ 381 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 382 { 383 struct pci_sys_data *sys = dev->sysdata; 384 int irq = -1; 385 386 if (sys->map_irq) 387 irq = sys->map_irq(dev, slot, pin); 388 389 if (debug_pci) 390 printk("PCI: %s mapping slot %d pin %d => irq %d\n", 391 pci_name(dev), slot, pin, irq); 392 393 return irq; 394 } 395 396 static int pcibios_init_resource(int busnr, struct pci_sys_data *sys) 397 { 398 int ret; 399 struct resource_entry *window; 400 401 if (list_empty(&sys->resources)) { 402 pci_add_resource_offset(&sys->resources, 403 &iomem_resource, sys->mem_offset); 404 } 405 406 resource_list_for_each_entry(window, &sys->resources) 407 if (resource_type(window->res) == IORESOURCE_IO) 408 return 0; 409 410 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; 411 sys->io_res.end = (busnr + 1) * SZ_64K - 1; 412 sys->io_res.flags = IORESOURCE_IO; 413 sys->io_res.name = sys->io_res_name; 414 sprintf(sys->io_res_name, "PCI%d I/O", busnr); 415 416 ret = request_resource(&ioport_resource, &sys->io_res); 417 if (ret) { 418 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); 419 return ret; 420 } 421 pci_add_resource_offset(&sys->resources, &sys->io_res, 422 sys->io_offset); 423 424 return 0; 425 } 426 427 static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, 428 struct list_head *head) 429 { 430 struct pci_sys_data *sys = NULL; 431 int ret; 432 int nr, busnr; 433 434 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { 435 struct pci_host_bridge *bridge; 436 437 bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data)); 438 if (WARN(!bridge, "PCI: unable to allocate bridge!")) 439 break; 440 441 sys = pci_host_bridge_priv(bridge); 442 443 sys->busnr = busnr; 444 sys->swizzle = hw->swizzle; 445 sys->map_irq = hw->map_irq; 446 INIT_LIST_HEAD(&sys->resources); 447 448 if (hw->private_data) 449 sys->private_data = hw->private_data[nr]; 450 451 ret = hw->setup(nr, sys); 452 453 if (ret > 0) { 454 455 ret = pcibios_init_resource(nr, sys); 456 if (ret) { 457 pci_free_host_bridge(bridge); 458 break; 459 } 460 461 bridge->map_irq = pcibios_map_irq; 462 bridge->swizzle_irq = pcibios_swizzle; 463 464 if (hw->scan) 465 ret = hw->scan(nr, bridge); 466 else { 467 list_splice_init(&sys->resources, 468 &bridge->windows); 469 bridge->dev.parent = parent; 470 bridge->sysdata = sys; 471 bridge->busnr = sys->busnr; 472 bridge->ops = hw->ops; 473 474 ret = pci_scan_root_bus_bridge(bridge); 475 } 476 477 if (WARN(ret < 0, "PCI: unable to scan bus!")) { 478 pci_free_host_bridge(bridge); 479 break; 480 } 481 482 sys->bus = bridge->bus; 483 484 busnr = sys->bus->busn_res.end + 1; 485 486 list_add(&sys->node, head); 487 } else { 488 pci_free_host_bridge(bridge); 489 if (ret < 0) 490 break; 491 } 492 } 493 } 494 495 void pci_common_init_dev(struct device *parent, struct hw_pci *hw) 496 { 497 struct pci_sys_data *sys; 498 LIST_HEAD(head); 499 500 pci_add_flags(PCI_REASSIGN_ALL_BUS); 501 if (hw->preinit) 502 hw->preinit(); 503 pcibios_init_hw(parent, hw, &head); 504 if (hw->postinit) 505 hw->postinit(); 506 507 list_for_each_entry(sys, &head, node) { 508 struct pci_bus *bus = sys->bus; 509 510 /* 511 * We insert PCI resources into the iomem_resource and 512 * ioport_resource trees in either pci_bus_claim_resources() 513 * or pci_bus_assign_resources(). 514 */ 515 if (pci_has_flag(PCI_PROBE_ONLY)) { 516 pci_bus_claim_resources(bus); 517 } else { 518 struct pci_bus *child; 519 520 pci_bus_size_bridges(bus); 521 pci_bus_assign_resources(bus); 522 523 list_for_each_entry(child, &bus->children, node) 524 pcie_bus_configure_settings(child); 525 } 526 527 pci_bus_add_devices(bus); 528 } 529 } 530 531 #ifndef CONFIG_PCI_HOST_ITE8152 532 void pcibios_set_master(struct pci_dev *dev) 533 { 534 /* No special bus mastering setup handling */ 535 } 536 #endif 537 538 char * __init pcibios_setup(char *str) 539 { 540 if (!strcmp(str, "debug")) { 541 debug_pci = 1; 542 return NULL; 543 } 544 return str; 545 } 546 547 /* 548 * From arch/i386/kernel/pci-i386.c: 549 * 550 * We need to avoid collisions with `mirrored' VGA ports 551 * and other strange ISA hardware, so we always want the 552 * addresses to be allocated in the 0x000-0x0ff region 553 * modulo 0x400. 554 * 555 * Why? Because some silly external IO cards only decode 556 * the low 10 bits of the IO address. The 0x00-0xff region 557 * is reserved for motherboard devices that decode all 16 558 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 559 * but we want to try to avoid allocating at 0x2900-0x2bff 560 * which might be mirrored at 0x0100-0x03ff.. 561 */ 562 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 563 resource_size_t size, resource_size_t align) 564 { 565 struct pci_dev *dev = data; 566 resource_size_t start = res->start; 567 struct pci_host_bridge *host_bridge; 568 569 if (res->flags & IORESOURCE_IO && start & 0x300) 570 start = (start + 0x3ff) & ~0x3ff; 571 572 start = (start + align - 1) & ~(align - 1); 573 574 host_bridge = pci_find_host_bridge(dev->bus); 575 576 if (host_bridge->align_resource) 577 return host_bridge->align_resource(dev, res, 578 start, size, align); 579 580 return start; 581 } 582 583 void __init pci_map_io_early(unsigned long pfn) 584 { 585 struct map_desc pci_io_desc = { 586 .virtual = PCI_IO_VIRT_BASE, 587 .type = MT_DEVICE, 588 .length = SZ_64K, 589 }; 590 591 pci_io_desc.pfn = pfn; 592 iotable_init(&pci_io_desc, 1); 593 } 594