1*d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2c7c3eac6SShawn Guo/* 3c7c3eac6SShawn Guo * Copyright 2013 Freescale Semiconductor, Inc. 4c7c3eac6SShawn Guo */ 5c7c3eac6SShawn Guo 6cfdb7d56SStefan Agner#define VF_UART0_BASE_ADDR 0x40027000 7cfdb7d56SStefan Agner#define VF_UART1_BASE_ADDR 0x40028000 8cfdb7d56SStefan Agner#define VF_UART2_BASE_ADDR 0x40029000 9cfdb7d56SStefan Agner#define VF_UART3_BASE_ADDR 0x4002a000 10cfdb7d56SStefan Agner#define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR 11cfdb7d56SStefan Agner#define VF_UART_BASE(n) VF_UART_BASE_ADDR(n) 12cfdb7d56SStefan Agner#define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT) 13cfdb7d56SStefan Agner 14cfdb7d56SStefan Agner#define VF_UART_VIRTUAL_BASE 0xfe000000 15cfdb7d56SStefan Agner 16c7c3eac6SShawn Guo .macro addruart, rp, rv, tmp 17cfdb7d56SStefan Agner ldr \rp, =VF_UART_PHYSICAL_BASE @ physical 18cfdb7d56SStefan Agner and \rv, \rp, #0xffffff @ offset within 16MB section 19cfdb7d56SStefan Agner add \rv, \rv, #VF_UART_VIRTUAL_BASE 20c7c3eac6SShawn Guo .endm 21c7c3eac6SShawn Guo 22c7c3eac6SShawn Guo .macro senduart, rd, rx 23c7c3eac6SShawn Guo strb \rd, [\rx, #0x7] @ Data Register 24c7c3eac6SShawn Guo .endm 25c7c3eac6SShawn Guo 26c7c3eac6SShawn Guo .macro busyuart, rd, rx 27c7c3eac6SShawn Guo1001: ldrb \rd, [\rx, #0x4] @ Status Register 1 28c7c3eac6SShawn Guo tst \rd, #1 << 6 @ TC 29c7c3eac6SShawn Guo beq 1001b @ wait until transmit done 30c7c3eac6SShawn Guo .endm 31c7c3eac6SShawn Guo 32c7c3eac6SShawn Guo .macro waituart,rd,rx 33c7c3eac6SShawn Guo .endm 34