xref: /linux/arch/arm/include/debug/msm.S (revision e9e4e44309f866b115d08ab4a54834008c50a8a4)
1/*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 */
17
18	.macro	addruart, rp, rv, tmp
19#ifdef CONFIG_DEBUG_UART_PHYS
20	ldr	\rp, =CONFIG_DEBUG_UART_PHYS
21	ldr	\rv, =CONFIG_DEBUG_UART_VIRT
22#endif
23	.endm
24
25	.macro	senduart, rd, rx
26ARM_BE8(rev	\rd, \rd )
27#ifdef CONFIG_DEBUG_QCOM_UARTDM
28	@ Write the 1 character to UARTDM_TF
29	str	\rd, [\rx, #0x70]
30#else
31	str	\rd, [\rx, #0x0C]
32#endif
33	.endm
34
35	.macro	waituart, rd, rx
36#ifdef CONFIG_DEBUG_QCOM_UARTDM
37	@ check for TX_EMT in UARTDM_SR
38	ldr	\rd, [\rx, #0x08]
39ARM_BE8(rev     \rd, \rd )
40	tst	\rd, #0x08
41	bne	1002f
42	@ wait for TXREADY in UARTDM_ISR
431001:	ldr	\rd, [\rx, #0x14]
44ARM_BE8(rev     \rd, \rd )
45	tst	\rd, #0x80
46	beq 	1001b
471002:
48	@ Clear TX_READY by writing to the UARTDM_CR register
49	mov	\rd, #0x300
50ARM_BE8(rev     \rd, \rd )
51	str	\rd, [\rx, #0x10]
52	@ Write 0x1 to NCF register
53	mov 	\rd, #0x1
54ARM_BE8(rev     \rd, \rd )
55	str	\rd, [\rx, #0x40]
56	@ UARTDM reg. Read to induce delay
57	ldr	\rd, [\rx, #0x08]
58#else
59	@ wait for TX_READY
601001:	ldr	\rd, [\rx, #0x08]
61ARM_BE8(rev     \rd, \rd )
62	tst	\rd, #0x04
63	beq	1001b
64#endif
65	.endm
66
67	.macro	busyuart, rd, rx
68	.endm
69