xref: /linux/arch/arm/include/debug/msm.S (revision 825f4e0271b0de3f7f31d963dcdaa0056fe9b73a)
1/*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 */
17
18	.macro	addruart, rp, rv, tmp
19#ifdef CONFIG_DEBUG_UART_PHYS
20	ldr	\rp, =CONFIG_DEBUG_UART_PHYS
21	ldr	\rv, =CONFIG_DEBUG_UART_VIRT
22#endif
23	.endm
24
25	.macro	senduart, rd, rx
26#ifdef CONFIG_DEBUG_QCOM_UARTDM
27	@ Write the 1 character to UARTDM_TF
28	str	\rd, [\rx, #0x70]
29#else
30	str	\rd, [\rx, #0x0C]
31#endif
32	.endm
33
34	.macro	waituart, rd, rx
35#ifdef CONFIG_DEBUG_QCOM_UARTDM
36	@ check for TX_EMT in UARTDM_SR
37	ldr	\rd, [\rx, #0x08]
38	tst	\rd, #0x08
39	bne	1002f
40	@ wait for TXREADY in UARTDM_ISR
411001:	ldr	\rd, [\rx, #0x14]
42	tst	\rd, #0x80
43	beq 	1001b
441002:
45	@ Clear TX_READY by writing to the UARTDM_CR register
46	mov	\rd, #0x300
47	str	\rd, [\rx, #0x10]
48	@ Write 0x1 to NCF register
49	mov 	\rd, #0x1
50	str	\rd, [\rx, #0x40]
51	@ UARTDM reg. Read to induce delay
52	ldr	\rd, [\rx, #0x08]
53#else
54	@ wait for TX_READY
551001:	ldr	\rd, [\rx, #0x08]
56	tst	\rd, #0x04
57	beq	1001b
58#endif
59	.endm
60
61	.macro	busyuart, rd, rx
62	.endm
63