xref: /linux/arch/arm/include/debug/msm.S (revision 6fdcba32711044c35c0e1b094cbd8f3f0b4472c9)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
6 * Author: Brian Swetland <swetland@google.com>
7 */
8
9	.macro	addruart, rp, rv, tmp
10	ldr	\rp, =CONFIG_DEBUG_UART_PHYS
11	ldr	\rv, =CONFIG_DEBUG_UART_VIRT
12	.endm
13
14	.macro	senduart, rd, rx
15ARM_BE8(rev	\rd, \rd )
16	@ Write the 1 character to UARTDM_TF
17	str	\rd, [\rx, #0x70]
18	.endm
19
20	.macro	waituart, rd, rx
21	@ check for TX_EMT in UARTDM_SR
22	ldr	\rd, [\rx, #0x08]
23ARM_BE8(rev     \rd, \rd )
24	tst	\rd, #0x08
25	bne	1002f
26	@ wait for TXREADY in UARTDM_ISR
271001:	ldr	\rd, [\rx, #0x14]
28ARM_BE8(rev     \rd, \rd )
29	tst	\rd, #0x80
30	beq 	1001b
311002:
32	@ Clear TX_READY by writing to the UARTDM_CR register
33	mov	\rd, #0x300
34ARM_BE8(rev     \rd, \rd )
35	str	\rd, [\rx, #0x10]
36	@ Write 0x1 to NCF register
37	mov 	\rd, #0x1
38ARM_BE8(rev     \rd, \rd )
39	str	\rd, [\rx, #0x40]
40	@ UARTDM reg. Read to induce delay
41	ldr	\rd, [\rx, #0x08]
42	.endm
43
44	.macro	busyuart, rd, rx
45	.endm
46