16d07917eSStephen Boyd/* 26d07917eSStephen Boyd * 36d07917eSStephen Boyd * Copyright (C) 2007 Google, Inc. 46d07917eSStephen Boyd * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 56d07917eSStephen Boyd * Author: Brian Swetland <swetland@google.com> 66d07917eSStephen Boyd * 76d07917eSStephen Boyd * This software is licensed under the terms of the GNU General Public 86d07917eSStephen Boyd * License version 2, as published by the Free Software Foundation, and 96d07917eSStephen Boyd * may be copied, distributed, and modified under those terms. 106d07917eSStephen Boyd * 116d07917eSStephen Boyd * This program is distributed in the hope that it will be useful, 126d07917eSStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 136d07917eSStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 146d07917eSStephen Boyd * GNU General Public License for more details. 156d07917eSStephen Boyd * 166d07917eSStephen Boyd */ 176d07917eSStephen Boyd 186d07917eSStephen Boyd .macro addruart, rp, rv, tmp 19*7098cff2SIvan T. Ivanov#ifdef CONFIG_DEBUG_UART_PHYS 20*7098cff2SIvan T. Ivanov ldr \rp, =CONFIG_DEBUG_UART_PHYS 21*7098cff2SIvan T. Ivanov ldr \rv, =CONFIG_DEBUG_UART_VIRT 226d07917eSStephen Boyd#endif 236d07917eSStephen Boyd .endm 246d07917eSStephen Boyd 256d07917eSStephen Boyd .macro senduart, rd, rx 26*7098cff2SIvan T. Ivanov#ifdef CONFIG_DEBUG_QCOM_UARTDM 276d07917eSStephen Boyd @ Write the 1 character to UARTDM_TF 286d07917eSStephen Boyd str \rd, [\rx, #0x70] 296d07917eSStephen Boyd#else 306d07917eSStephen Boyd str \rd, [\rx, #0x0C] 316d07917eSStephen Boyd#endif 326d07917eSStephen Boyd .endm 336d07917eSStephen Boyd 346d07917eSStephen Boyd .macro waituart, rd, rx 35*7098cff2SIvan T. Ivanov#ifdef CONFIG_DEBUG_QCOM_UARTDM 366d07917eSStephen Boyd @ check for TX_EMT in UARTDM_SR 376d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 386d07917eSStephen Boyd tst \rd, #0x08 396d07917eSStephen Boyd bne 1002f 406d07917eSStephen Boyd @ wait for TXREADY in UARTDM_ISR 416d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x14] 426d07917eSStephen Boyd tst \rd, #0x80 436d07917eSStephen Boyd beq 1001b 446d07917eSStephen Boyd1002: 456d07917eSStephen Boyd @ Clear TX_READY by writing to the UARTDM_CR register 466d07917eSStephen Boyd mov \rd, #0x300 476d07917eSStephen Boyd str \rd, [\rx, #0x10] 486d07917eSStephen Boyd @ Write 0x1 to NCF register 496d07917eSStephen Boyd mov \rd, #0x1 506d07917eSStephen Boyd str \rd, [\rx, #0x40] 516d07917eSStephen Boyd @ UARTDM reg. Read to induce delay 526d07917eSStephen Boyd ldr \rd, [\rx, #0x08] 536d07917eSStephen Boyd#else 546d07917eSStephen Boyd @ wait for TX_READY 556d07917eSStephen Boyd1001: ldr \rd, [\rx, #0x08] 566d07917eSStephen Boyd tst \rd, #0x04 576d07917eSStephen Boyd beq 1001b 586d07917eSStephen Boyd#endif 596d07917eSStephen Boyd .endm 606d07917eSStephen Boyd 616d07917eSStephen Boyd .macro busyuart, rd, rx 626d07917eSStephen Boyd .endm 63