1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright (C) 2016 Broadcom */ 3#include <linux/serial_reg.h> 4#include <asm/cputype.h> 5 6/* Physical register offset and virtual register offset */ 7#define REG_PHYS_BASE 0xf0000000 8#define REG_PHYS_BASE_V7 0x08000000 9#define REG_VIRT_BASE 0xfc000000 10#define REG_PHYS_ADDR(x) ((x) + REG_PHYS_BASE) 11#define REG_PHYS_ADDR_V7(x) ((x) + REG_PHYS_BASE_V7) 12 13/* Product id can be read from here */ 14#define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000) 15#define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000) 16 17#define UARTA_3390 REG_PHYS_ADDR(0x40a900) 18#define UARTA_72116 UARTA_7255 19#define UARTA_7250 REG_PHYS_ADDR(0x40b400) 20#define UARTA_7255 REG_PHYS_ADDR(0x40c000) 21#define UARTA_7260 UARTA_7255 22#define UARTA_7268 UARTA_7255 23#define UARTA_7271 UARTA_7268 24#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) 25#define UARTA_7216 UARTA_7278 26#define UARTA_72164 UARTA_7278 27#define UARTA_72165 UARTA_7278 28#define UARTA_7364 REG_PHYS_ADDR(0x40b000) 29#define UARTA_7366 UARTA_7364 30#define UARTA_74165 UARTA_7278 31#define UARTA_74371 REG_PHYS_ADDR(0x406b00) 32#define UARTA_7439 REG_PHYS_ADDR(0x40a900) 33#define UARTA_7445 REG_PHYS_ADDR(0x40ab00) 34 35#define UART_SHIFT 2 36 37#define checkuart(rp, rv, family_id, family) \ 38 /* Load family id */ \ 39 ldr rp, =family_id ; \ 40 /* Compare SUN_TOP_CTRL value against it */ \ 41 cmp rp, rv ; \ 42 /* Passed test, load address */ \ 43 ldreq rp, =UARTA_##family ; \ 44 /* Jump to save UART address */ \ 45 beq 91f 46 47 .macro addruart, rp, rv, tmp 48 adr \rp, 99f @ actual addr of 99f 49 ldr \rv, [\rp] @ linked addr is stored there 50 sub \rv, \rv, \rp @ offset between the two 51 ldr \rp, [\rp, #4] @ linked brcmstb_uart_config 52 sub \tmp, \rp, \rv @ actual brcmstb_uart_config 53 ldr \rp, [\tmp] @ Load brcmstb_uart_config 54 cmp \rp, #1 @ needs initialization? 55 bne 100f @ no; go load the addresses 56 mov \rv, #0 @ yes; record init is done 57 str \rv, [\tmp] 58 59 /* Check for V7 memory map if B53 */ 60 mrc p15, 0, \rv, c0, c0, 0 @ get Main ID register 61 ldr \rp, =ARM_CPU_PART_MASK 62 and \rv, \rv, \rp 63 ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU 64 cmp \rv, \rp 65 bne 10f 66 67 /* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */ 68 mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR 69 ands \rv, \rv, #REG_PHYS_BASE 70 ldreq \rp, =SUN_TOP_CTRL_BASE_V7 71 72 /* Check SUN_TOP_CTRL base */ 7310: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA 74 ldr \rv, [\rp, #0] @ get register contents 75ARM_BE8( rev \rv, \rv ) 76 and \rv, \rv, #0xffffff00 @ strip revision bits [7:0] 77 78 /* Chip specific detection starts here */ 7920: checkuart(\rp, \rv, 0x33900000, 3390) 8021: checkuart(\rp, \rv, 0x07211600, 72116) 8122: checkuart(\rp, \rv, 0x72160000, 7216) 8223: checkuart(\rp, \rv, 0x07216400, 72164) 8324: checkuart(\rp, \rv, 0x07216500, 72165) 8425: checkuart(\rp, \rv, 0x72500000, 7250) 8526: checkuart(\rp, \rv, 0x72550000, 7255) 8627: checkuart(\rp, \rv, 0x72600000, 7260) 8728: checkuart(\rp, \rv, 0x72680000, 7268) 8829: checkuart(\rp, \rv, 0x72710000, 7271) 8930: checkuart(\rp, \rv, 0x72780000, 7278) 9031: checkuart(\rp, \rv, 0x73640000, 7364) 9132: checkuart(\rp, \rv, 0x73660000, 7366) 9233: checkuart(\rp, \rv, 0x07416500, 74165) 9334: checkuart(\rp, \rv, 0x07437100, 74371) 9435: checkuart(\rp, \rv, 0x74390000, 7439) 9536: checkuart(\rp, \rv, 0x74450000, 7445) 96 97 /* No valid UART found */ 9890: mov \rp, #0 99 /* fall through */ 100 101 /* Record whichever UART we chose */ 10291: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys 103 cmp \rp, #0 @ Valid UART address? 104 bne 92f @ Yes, go process it 105 str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt 106 b 100f @ Done 10792: and \rv, \rp, #0xffffff @ offset within 16MB section 108 add \rv, \rv, #REG_VIRT_BASE 109 str \rv, [\tmp, #8] @ Store in brcmstb_uart_virt 110 b 100f 111 112 .align 11399: .word . 114 .word brcmstb_uart_config 115 .ltorg 116 117 /* Load previously selected UART address */ 118100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys 119 ldr \rv, [\tmp, #8] @ Load brcmstb_uart_virt 120 .endm 121 122 .macro store, rd, rx:vararg 123ARM_BE8( rev \rd, \rd ) 124 str \rd, \rx 125 .endm 126 127 .macro load, rd, rx:vararg 128 ldr \rd, \rx 129ARM_BE8( rev \rd, \rd ) 130 .endm 131 132 .macro senduart,rd,rx 133 store \rd, [\rx, #UART_TX << UART_SHIFT] 134 .endm 135 136 .macro busyuart,rd,rx 1371002: load \rd, [\rx, #UART_LSR << UART_SHIFT] 138 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE 139 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE 140 bne 1002b 141 .endm 142 143 .macro waituarttxrdy,rd,rx 144 .endm 145 146 .macro waituartcts,rd,rx 147 .endm 148 149/* 150 * Storage for the state maintained by the macros above. 151 * 152 * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c. 153 * That's because this header is included from multiple files, and we only 154 * want a single copy of the data. In particular, the UART probing code above 155 * assumes it's running using physical addresses. This is true when this file 156 * is included from head.o, but not when included from debug.o. So we need 157 * to share the probe results between the two copies, rather than having 158 * to re-run the probing again later. 159 * 160 * In the decompressor, we put the symbol/storage right here, since common.c 161 * isn't included in the decompressor build. This symbol gets put in .text 162 * even though it's really data, since .data is discarded from the 163 * decompressor. Luckily, .text is writeable in the decompressor, unless 164 * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug. 165 */ 166#if defined(ZIMAGE) 167brcmstb_uart_config: 168 /* Debug UART initialization required */ 169 .word 1 170 /* Debug UART physical address */ 171 .word 0 172 /* Debug UART virtual address */ 173 .word 0 174#endif 175